JP2680539B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to an L-shaped insulator having an improved insulator on a side wall of a gate electrode.
The present invention relates to a MOS transistor having a DD (Lightly Doped Drain) structure. 2. Description of the Related Art In recent years, as the density of integrated circuits has increased, the gate length has become shorter and shorter, and the shortening of the gate length has various adverse effects. This shortening of the gate length has various adverse effects. First, the threshold voltage V _TH is lowered due to the short channel effect. Second,
When operating in the saturation region, the electrons generated by the drain current increase with the increase of the electric field strength in the pinch-off region.
The hole pair receives energy from the electric field, and is attracted toward the substrate by the electric field between the substrates to become a substrate current. Third,
Further, when a high voltage is applied to the drain region, electric field concentration occurs in the vicinity of the drain in the pinch-off region, causing an increase in gate current, which leads to instability of V _TH and accelerated deterioration of the gate insulating film. Fourth, a considerable number of holes flow into the source region as the substrate current is increased,
A forward bias is applied between the substrates, electrons are injected from the source region to the substrate, n ⁺ pn ⁺ bipolar transistor operation occurs due to the source region, the substrate, and the drain region, and the breakdown voltage of the MOS transistor is defined. (E. Sun. et ald. "Breakdown Mechani
sm in Short- Channel MOS Transistor "I
E ³ Tech. Dig. Int Electron Device M
eeting., Washington D.E. C. 1978, p478). For this reason, the greatest problem of the short channel MOS transistor is to alleviate the electric field concentration near the drain region in the pinch-off region and increase the breakdown voltage. Conventionally, a semiconductor device such as that shown in FIG. 7 has been known as a MOS transistor. 1 in the figure
Is, for example, a p-type semiconductor substrate. An element isolation region 2 is provided on the surface of the substrate 1, and a plurality of island regions 3 separated by the element isolation region 2 have a depth of 0.19 μm and a surface impurity concentration of 10 ²⁰ cm ⁻³ of n ⁺ type. Source and drain regions 4 and 5 are provided separately from each other. Island area 3
A gate electrode 7 is provided on the top of the gate insulating film 6 having a thickness of 20 nm. An interlayer insulating film 8 is provided on the substrate 1 including the gate electrode 7 and the like. Contact holes 9 are formed in portions of the interlayer insulating film 8 corresponding to the source and drain regions 4 and 5 and the gate electrode 7, respectively. The source / drain regions 4 are formed on the interlayer insulating film 8 through contact holes 9.
5 and the Al wiring 10 connected to the gate electrode 7, respectively. However, according to the MOS transistor of FIG. 7, a characteristic diagram showing the relationship between the length of the gate electrode and the breakdown voltage as shown in FIG. 8A is obtained. Was given. According to the figure, when the length of the gate electrode is gradually reduced to 2 μm and 1 μm, the breakdown voltage draws a gentle arc and gradually decreases. This means that in a bipolar transistor having a sole region, a substrate, and a drain region as an emitter, a base, and a collector, the base length becomes short and the current amplification factor becomes large, so that the breakdown voltage between the collector and the emitter decreases. Is equivalent to. Here, the base length is related to the extension of the depletion layer from the collector (drain region). For this reason, conventionally, in order to increase the drain voltage of the pinch-off region described above, a MOS transistor having an LDD structure has been proposed as shown in FIG. Source and drain regions 11 and 12 of this transistor
Is the first impurity having a relatively low impurity concentration (10 ¹⁷ to 10 ¹⁸ cm ⁻³ ) and a relatively shallow diffusion depth (0.22 μm) on the surface provided in the island region 3 near the gate electrode 7, respectively. layer
13 ₁ , 14 ₁ , and the impurity concentration of the surface provided in the vicinity of these first impurity layers 13 ₁ , 14 ₁ is high (about 10 ²⁰
cm ⁻³ ) and the second diffusion layers 13 ₂ and 14 ₂ having a large diffusion depth (0.45 μm). Here, the first
The impurity layers 13 ₁ and 14 _{1 of} are the drain regions of the pinch-off region.
It works to reduce the electric field concentration in the vicinity of 12. By the way, in the transistor of FIG.
A SiO ₂ film is generally used as the insulator 15 formed on the side wall of the gate electrode 7, and the characteristics of the transistor are deteriorated by the hot carriers trapped in the insulator 15 on the side wall of the gate electrode. In other words, the hot carriers generated on the source and drain sides of the transistor are
The injected charges are unable to move to other places and increase more and more, and the charges affect the potential of the channel and change the transistor characteristics. The present invention has been made in view of the above circumstances, and avoids the accumulation of charges in the insulator on the side wall of the gate electrode, and the potential of the channel is affected by the charges to deteriorate the transistor characteristics. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can avoid the above. According to the present invention, a step of forming a plurality of island regions separated by element isolation regions on a surface, a step of forming a gate electrode on the island regions, and the islands are provided. Forming a first impurity layer on the surface of the region so as to be self-aligned with the gate electrode and reach the end of the island region, the first impurity layer constituting each of the source and drain regions;
Forming a CVD-insulating film on the side wall of the gate electrode, and forming the gate electrode and C on the surface of the first impurity layer.
A step of forming a second impurity layer which is formed in self-alignment with the VD-insulating film and is shallower and higher in concentration than the first impurity layer; a step of forming an interlayer insulating film on the entire surface;
And the interlayer insulating film corresponding to the portion where the drain region is to be formed
To selectively form contact holes
Process and from the contact hole to the island region,
While penetrating the second impurity layer,
Be careful not to have a deeper and deeper impurity concentration than the other parts.
And a step of introducing a pure material . DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a MOS transistor having an LDD structure according to an embodiment of the present invention will be described below in the order of steps shown in FIG.
(D) and FIG. 2 will be described. (1). First, an element isolation region 22 is formed on the surface of a p-type Si substrate 21 by a selective oxidation method or the like, and then an oxide film 24 having a thickness of 20 nm is formed on the surface of an island region 23 isolated by the element isolation region 22.
Was formed. Subsequently, a polycrystalline silicon layer 25 having a thickness of 400 nm was formed on the entire surface (shown in FIG. 1A). Next, a resist pattern (not shown) was formed on the portion of the polycrystalline silicon layer 25 where the gate electrode was to be formed by photolithography. After that, the polycrystalline silicon layer 25 was selectively removed by etching using the resist pattern as a mask to form a gate electrode 26. Further, after removing the resist pattern, the oxide film 24 was selectively removed using the gate electrode 26 as a mask to form a gate insulating film 27. Continued,
An n-type impurity such as phosphorus is applied to the gate electrode at an accelerating voltage of 25K.
ion implantation under the conditions of eV and a dose amount of 8 × 10 ¹⁷ cm ^-2 ,
Low concentration first ion-implanted layers 28 and 29 were formed (see FIG. 1).
(B) Illustration). Arsenic may be ion-implanted instead of phosphorus. (2). Next, in an oxidizing atmosphere at 900 ° C., 6
After heat treatment for 0 minutes, an oxide film (S
iO ₂ film) 30 _1, and the surrounding oxide film (SiO ₂ film of the gate electrode 26 which is exposed) 30 ₂ to form a said ion-implanted layer to activate the phosphorous ions in the 28 and 29 first low concentration Impurity layers 31 ₁ and 32 ₁ were formed respectively. Then,
100-500 nm thick CVD-Si ₃ N ₄ film 33 on the entire surface
("Physics of Semiconductor Device", by JO
90 after forming HN WILEY & SONS (see 1981)
The CVD-Si ₃ N ₄ film 33 was baked and solidified at 0 ° C. for 30 minutes (FIG. 1C). Next, reactive ion etching (R
The Si ₃ N ₄ film 33 was etched away by IE) until the substrate 21 and the gate electrode were exposed. As a result, Si ₃ N _{4 is formed on} the side wall of the gate electrode 26 through the SiO ₂ film 30 _2.
Film 33 is left (hereinafter, this film is referred to as a residual the Si ₃ N ₄ film 33), remaining the Si ₃ N ₄ film 33 and the source, SiO ₂ film 30 ₁ remained between the drain region to be formed unit. The residual Si
The shape of the ₃ N ₄ film 33 is determined by the thickness of this film.
After that, ions are implanted into the exposed surface of the substrate 21 using the gate electrode 26 and the residual Si ₃ N ₄ film 33 as a mask under the conditions of an acceleration voltage of 50 KeV and a dose amount of 3 × 10 ¹⁵ cm ^-2 , and a high concentration second Ion-implanted layers 34 and 35 were formed (FIG. 1D). (3). Next, heat treatment such as a ring getter and a glass flow was performed at 900 ° C. for about 90 minutes. As a result,
Arsenic ions in the second ion-implanted layers 34 and 35 are activated to form high-concentration second impurity layers 31 ₂ and 32 ₂ , and the first impurity layers 31 ₁ and 32 ₁ also have a depth. The second impurity layers 31 ₂ and 32 ₂ are slightly spread in the direction to surround the bottoms and the gate-side sides of the second impurity layers 31 ₂ and 32 _2.
Source region 36 consisting of ₁ and 31 ₂ , first and second impurity layers
A drain region 37 composed of 32 ₁ and 32 ₂ was formed, respectively.
Here, the surface concentration of the low-concentration first impurity layers 31 ₁ and 32 ₁ is approximately 1 × 10 ¹⁸ cm ⁻³ , and the diffusion depth is 0.22 μm. On the other hand, the high-concentration second impurity layers 31 ₂ and 32 _{2 have} a surface concentration of about 10 ²⁰ cm ⁻³ and a diffusion depth of 0.21 μm.
The controllability with respect to the depth of the _first impurity layers 31 ₁ and 32 ₁ can be suppressed within ± 15% by the current technology. Then, after forming an interlayer insulating film 38 on the entire surface, the source, the second impurity layer 31 _2, 32 ₂ and the interlayer insulating film 38 corresponding to a portion of each of the gate electrode 26 of the drain region 36 and 37 An Al wiring 40, which was opened and connected through a contact hole 39, was formed to manufacture a MOS type transistor of LDD structure (shown in FIG. 2). The LDD structure MOS type transistor thus manufactured has the following effects. . In the above embodiment, the CVD-Si ₃ N ₄ film is formed on the entire surface of the substrate.
33 is formed, and S is formed on the side wall of the gate electrode 26 by RIE.
Residual Si ₃ N ₄ film having a large dielectric constant through the iO ₂ film 30 _2.
After forming 33 ', this residual Si ₃ N ₄ film is heat-treated.
SiO ₂ between 33 ′ and the source region 36 and the drain region 37
And a step of forming a film 30 _1. Therefore, the presence of the residual Si ₃ N ₄ film 33 ′ on the side wall of the gate electrode 26 makes the drain electric field near the gate electrode 26 extremely small.
This is because when the residual Si ₃ N ₄ film 33 'is used, the maximum electric field on the surface of the silicon substrate is reduced and the region width is reduced. As a result, when a predetermined potential difference is applied between the source region 36 and the drain region 37 and an on-current is passed between the regions 36 and 37, impact ionization in the vicinity of the drain is suppressed, which causes generation of hot carriers. Decrease. .. Further, the remaining the Si ₃ N ₄ film 33 'and the source region 36, the presence of the SiO ₂ film 30 ₁ between the drain region 37, Si ₃ N ₄ and the potential barrier is high relative to Si.
Therefore, even if hot carriers are generated in the vicinity of the drain, the injection probability that these hot carriers penetrate the SiO ₂ film 30 ₁ and reach the remaining Si ₃ N ₄ film 33 ′ becomes extremely small. the Si ₃ N ₄ film 33 'of the internal or residual the Si ₃ N ₄ film 33' and the hot carriers are trapped in the interface between the SiO ₂ film 30 ₁ is extremely small, and reliability is improved. [0014] Si substrate using the gate electrode 26 as a mask
Low concentration first impurity layer 31 ₁ , 32 _{1 on the} surface of the island region 23 of 21
To form the gate electrode 26 and the remaining Si ₃ N ₄ film 33 '.
The second impurity layer 31 having a high concentration and a diffusion depth shallower than that of the first impurity layer constituting the first impurity layer and the source / drain regions 36, 37 is formed on the surface of the island region 23 using the mask as a mask. ₂ and 32 ₂ are formed so that the bottom and the side on the gate side are surrounded by the first impurity layer. Therefore, FIG.
A characteristic diagram showing the relationship between the length of the gate electrode and the breakdown voltage as shown in (C) of FIG. From the figure, it can be confirmed that even if the length of the gate electrode is shortened to 2 μm and 1 μm, the break voltage is improved as in the conventional MOS transistor shown in FIG. 7 and FIG. It is considered that this is related to the extension of the depletion layers of the first impurity layers 31 ₁ and 32 ₁ . Note that (a) and (b) in the same figure show the case of the MOS type transistors of FIGS. 7 and 9. [0015] As shown in FIG. 3, it can be confirmed that the phenomenon of V _TH due to the short channel effect is improved. In addition, (b) and (c) in FIG.
The case of the OS type transistor and the MOS type transistor of FIG. 2 is shown. [0016] As shown in FIG. 4, the dependence of the peak value of the substrate current Isub on the length of the gate electrode is small.
Although not shown, it goes without saying that the gate current is also improved. [0017] The sheet resistance of the second impurity layer of the MOS transistor of FIG. 9 was about 25Ω / □, but it did not affect the transistor characteristics. . Since the etching selectivity of the Si ₃ N ₄ film 33 is higher than that of the field oxide film, the Si formed on the entire surface of the substrate
When etching the ₃ N ₄ film 33 by RIE, it is assumed that Si is used.
_{Even if the 3} N ₄ film 33 is over-etched, the etching of the field oxide film can be minimized. .. After forming the residual Si ₃ N ₄ film 33 ′, the diffusion coefficient of the oxidant during the heat treatment is SiO ₂ > polycrystalline Si> Si ₃
Since it is N ₄ , the area under the remaining Si ₃ N ₄ film 33 'is not easily oxidized, and the characteristic deterioration due to the bird's beak intrusion can be prevented. Although the oxide film is removed using the gate electrode as a mask in the above embodiment, the present invention is not limited to this, and ion implantation may be performed without removing the oxide film. Further, normally, in order to prevent punch-through, a single ion implantation or a double implantation of a deep implantation and a shallow implantation is performed in the channel portion, but the relation with the first and second impurity layers in the drain region of the MOS transistor of FIG. If the process is determined so that the above condition holds, no problem will occur and a further short channel MOS transistor can be obtained. The MOS type transistor according to the present invention is not limited to that shown in FIG. 2, but for example, as shown in FIG. 6, the second impurity layers 63, 63 of the source and drain regions 61, 62, respectively.
The structure may be such that the portions corresponding to the contact holes 39 of 64 are formed deeper. The source / drain regions 61 and 62 are formed after the step of FIG.
38, and the interlayer insulating film 38 corresponding to the source / drain regions 61 and 62 is selectively etched to form contact holes.
It can be formed by forming 39, and ion-implanting phosphorus, for example, through the contact hole 39 and then performing heat treatment. Further, instead of ion implantation of phosphorus, phosphorus may be diffused. According to such a transistor, the diffusion depth of the portions of the source / drain regions 61 and 62 corresponding to the contact holes 39 is deeper, so that when the Al wiring 40 is formed,
Can be prevented from penetrating. Further, as shown in FIG. 6, the diffusion depth of the source / drain regions 45 and 48 may be shallower than that of the first impurity layers 31 ₁ and 32 ₁ . Here, the second impurity layer 4
The diffusion depth of 7,48 is considerably shallower than the diffusion depth of the first impurity layers 31 ₁ , 32 ₁ , and the source / drain regions 4
When the resistances of 5 and 46 affect the transistor characteristics, the resistance can be lowered by forming a tungsten (W) layer and a PtSi layer on the source / drain regions 45 and 46. In the above embodiment, polycrystalline silicon was used as the material for the gate electrode, but the material is not limited to this, and a melting point metal such as Mo or W or a silicide thereof may be used. As described in detail above, according to the present invention, it is possible to avoid the accumulation of charges in the insulator on the side wall of the gate electrode,
The charge prevents the potential of the channel from being affected and the transistor characteristics from deteriorating, and further reduces the breakdown voltage drop due to the reduction of the gate electrode.
It is possible to provide a method of manufacturing a semiconductor device having various effects such as improvement of V _TH reduction due to the short channel effect.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing, in the order of steps, a method for manufacturing an LDD-structure MOS transistor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the final step of the LDD-structured MOS transistor according to FIG. FIG. 3 is a characteristic diagram showing the relationship between the length of the gate electrode and the breakdown voltage of the transistor of FIG. FIG. 4 is a characteristic diagram showing the relationship between the gate electrode length and ΔV _TH of the conventional transistor and the transistor of FIG. 2. 5 is a characteristic diagram showing the relationship between the length of the gate electrode and the peak value of the substrate current of the conventional transistor and the transistor of FIG. FIG. 6 is a MOS having an LDD structure according to another embodiment of the present invention.
FIG. FIG. 7 is a sectional view of a conventional MOS transistor. FIG. 8 is a characteristic diagram showing the relationship between the length of the gate electrode and the breakdown voltage of a conventional MOS transistor. FIG. 9 is a sectional view of a conventional MOS transistor having an LDD structure. [Explanation of symbols] 21 ... Si substrate (semiconductor substrate), 22 ... Element isolation region,
23 ... Island region, 24, 30 ₁ , 30 ₂ ... Oxide film, 25 ... Polycrystalline silicon layer, 26 ... Gate electrode, 27 ... Gate insulating film,
28, 29, 35, 35 ... Ion-implanted layer, 31 ₁ , 31 ₂ , 32
₁ , 32 ₂ , 43, 44, 47, 48 ... Impurity layer, 33 ... Si ₃ N
₄ film, 33 '... Remaining Si ₃ N ₄ film (second insulator),
36,41,45… source region, 37,42,46… drain region,
38 ... Interlayer insulation film, 39 ... Contact hole, 40 ...
Al wiring.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Takayoshi Higuchi               72 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Stock               Inside the Toshiba Horikawacho factory                (56) References JP-A-53-108380 (JP, A)                 JP-A-58-79766 (JP, A)                 JP-A-57-159066 (JP, A)                 JP-A-51-137384 (JP, A)                 JP-A-56-130971 (JP, A)                 JP 59-6580 (JP, A)

Claims (1)

(57) [Claims] Forming a plurality of island regions separated by element isolation regions on the surface, forming a gate electrode on the island regions, and self-aligning with the gate electrodes on the island region surface and the island regions Forming a first impurity layer forming part of each of the source and drain regions so as to reach the end of the gate electrode, a step of forming a CVD-insulating film on the sidewall of the gate electrode, and the first impurity. A second layer, which is formed on the surface of the layer in a self-aligned manner with the gate electrode and the CVD-insulating film, is shallower than the first impurity layer, and has a high concentration.
Process to form the impurity layer and the inter-layer insulation film is formed on the entire surface
Corresponding to the process for forming the source and drain regions.
Contact by selectively etching the interlayer insulating film
The process of forming the hole and before this contact hole
The second impurity layer is penetrated to the island region and
Deeper and deeper impurity concentration than other parts of the second impurity layer
And a step of introducing an impurity so that the semiconductor device has a method of manufacturing a semiconductor device.