JP2000277533A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor device of a structure wherein a reduction in resistance, such as a source resistance, and an enhancement in a gate breakdown voltage in breakdown voltage can be contrived in an easy process, and the manufacturing process of the device. SOLUTION: The manufacturing method of a compound semiconductor device has a step of forming an SiOx film 5 on a GaAs substrate 1, a step of forming an SiN film 8, which has a film thickness distribution of its film thickness being increased in order in the direction of separating from the contact part with a gate electrode on the film 5 and prevents As atoms from being diffused in the outside, and a step wherein a heat treatment is performed, silicon within the film 5 is diffused in the substrate 1 and high-concentration impurity layers 9a and 9d and doped layers 9a having a sheet resistance value that is continuously changed from the side of the gate electrode to the sides of the layers 9s and 9d are formed in the substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device and an apparatus for manufacturing the same, and more particularly, to a structure of a field-effect transistor effective for lowering the source resistance and increasing the gate breakdown voltage of the field-effect transistor, and its structure. It relates to a manufacturing method.

[0002]

2. Description of the Related Art Generally, a MES type field effect transistor (hereinafter referred to as a MESFET) using GaAs or the like has a high gate length accuracy and a low resistance such as a source resistance by minimizing the influence of a surface depletion layer. Also, there is a demand for a higher gate breakdown voltage.

For this reason, in the conventional MESFET, the carrier concentration of the high impurity concentration active layer constituting the drain region and the source region is higher on one side or both sides of the channel layer at the gate electrode contact portion than on the channel layer. By interposing a doping layer that is lower than the concentration and that is not in contact with the gate electrode, the resistance such as the source resistance is reduced, and the gate breakdown voltage is increased.

FIG. 7 is a cross-sectional view showing a conventional MESFET manufacturing method for each process. Based on FIG.
A method for manufacturing an ESFET will be described.

First, a 150-nm thick SiN film 52 for through ion implantation is formed on a GaAs substrate 51 by plasma CVD or the like (see FIG. 7A).

Subsequently, a photoresist is applied on the SiN film 52 and patterned so as to open the channel layer. Then, using the photoresist 53 as a mask, first, an ion implantation method is performed from the surface side of the GaAs substrate 51. Li,
Mg is implanted to a predetermined depth to form a p ⁻ -type buffer layer, and then Si is implanted from the surface to a uniform depth shallower than the buffer layer by the same ion implantation method. A channel layer 54 is formed (see FIG. 7B). The implantation conditions of the buffer layer are Mg as a dopant, the implantation energy is 170 keV and the implantation amount is 1 × 10 ¹² cm ^−2, and the implantation condition of the channel layer 54 is Si as the dopant, the implantation energy is 100 keV and the implantation amount is 2
× 10 ¹² cm ^-2 .

Next, the photoresist 53 and SiN
After removing the film 52, a 500-nm thick SIN film 55 is deposited by a plasma CVD method or the like so as to withstand the annealing process again, and then the photoresist is patterned for forming a dummy gate. Thereafter, the photoresist 56 is masked, and Si is removed by Ga ion implantation.
Implantation is performed to a predetermined depth from the surface of the As substrate 51 to form drain and source regions (high impurity concentration active layers) 57d and 57s, which are n-type ion implantation layers (see FIG. 7C). The distance between the drain region 57d and the source region 57s is 2.5 μm. The implantation conditions of these high impurity concentration active layers are implantation energy of 90 keV and implantation amount of 5 × 10 ¹³ cm.
^-2 .

Subsequently, the photoresist 56 serving as a dummy gate is etched by oxygen plasma to obtain
After thinning from μm to 1.5 μm, the doping layers 58, 58 having a carrier concentration higher than that of the channel layer and lower than the carrier concentration of the high impurity concentration layers constituting the drain region 57d and the source region 57s are formed by adding Si to one line. It is formed by injecting to a similar depth (see FIG. 7D). The implantation conditions for the doping layer are an implantation energy of 70 keV and an implantation amount of 2 × 10 ¹² cm ⁻² .

Further, the photoresist 56 serving as a dummy gate is subjected to oxygen plasma by 1.5 μm to 0.5 μm.
After thinning to a thickness of m, a SiO ₂ film 59 having a thickness of about 2500 ° is formed on the entire surface of the photoresist 56 and the SiN film 55 by ECR-CVD (see FIG. 7E).

Next, the photoresist of the dummy gate is removed, lift-off is performed, and lamp annealing is performed in a state where the SiN film 55 is exposed. Lamp annealing is performed at 850 ° C. for about 5 seconds in an N ₂ atmosphere. Subsequently, SiN at a position corresponding to the drain region 57d and the source region 57s is formed.
The film 55 and the SiO ₂ film 59 are removed by etching to expose the surfaces of the drain region 57d and the source region 57s.
A drain electrode 60d and a source electrode 60s made of a uGe / Ni / Au multilayer metal film are formed. Further, the SiN film 55 in the gate region is removed by etching to expose the surface, and a gate electrode 61 made of a multilayer metal film of Ti / Pd / Au is formed (see FIG. 7F).

[0011]

In order to reduce the source resistance and the like and to increase the gate breakdown voltage, the carrier concentration on one or both sides of the channel layer at the gate electrode contact portion is higher than that of the channel layer. In addition, it is effective to interpose a doping layer which is lower than the carrier concentration of the high impurity concentration layer constituting the drain region and the source region and is not in contact with the gate electrode. In addition, if the doping layer can form a distribution in which the carrier concentration of the doping layer increases stepwise from the gate electrode side to the high-concentration layer side, the resistance such as the source resistance and the gate withstand voltage can be further increased.

However, since the doping is uniformly performed in the ion implantation technique, it is necessary to repeat the ion implantation technique and the dry etching technique in order to form a doping layer in which the carrier concentration changes stepwise. In addition, the process step and the dry etching step become complicated, and variations occur.

According to the present invention, the yield is improved by an easy process.
A compound semiconductor device capable of forming a doping layer having a high carrier concentration from the gate electrode side to the high-concentration layer side between the gate electrode and the high-concentration layer, thereby achieving a reduction in source resistance and the like and an increase in gate withstand voltage; and It is an object of the present invention to provide a manufacturing method thereof.

[0014]

According to the present invention, there is provided a compound semiconductor device comprising: a gate electrode provided on an operation layer made of a group III-V compound semiconductor; a high-concentration impurity layer provided in the operation layer; And a doping layer whose sheet resistance continuously changes from the gate electrode side to the high-concentration impurity layer side between the gate electrode end and the high-concentration impurity layer is provided.

Further, the method of manufacturing a compound semiconductor device according to the present invention is characterized in that a non-doped S
forming a silicon oxide film (SiOx film) in which i is diffused; Forming a film for preventing external diffusion, and performing heat treatment to diffuse silicon in the SiOx film into the compound semiconductor substrate, and to form a high-concentration impurity layer in the substrate and a sheet resistance from the gate electrode side to the high-concentration impurity layer side. Forming a doping layer whose value changes continuously.

Further, according to the present invention, a dummy gate pattern having an uppermost width wider than a width in contact with the substrate is formed, and the dummy gate pattern is used as a mask to separate from the gate electrode contact portion on the SiOx film by lift-off. In this case, it is possible to form a film having a film thickness distribution in which the film thickness is gradually increased in the direction in which the diffusion of the group V atoms is prevented.

Further, the method of manufacturing a compound semiconductor device according to the present invention is characterized in that a non-doped S
forming a silicon oxide film (SiOx film) in which i is diffused, forming a T-shaped gate electrode on the compound semiconductor substrate, and using the gate electrode as a mask on the SiOx film by a lift-off method. Forming a film having a film thickness distribution in which a film thickness is gradually increased in a direction away from a contact portion of the gate electrode with the substrate to prevent external diffusion of group V atoms; Diffusing silicon in the SiOx film to form a high-concentration impurity layer and a doping layer in which a sheet resistance value continuously changes from the gate electrode side to the high-concentration impurity layer side in the substrate. Features.

As disclosed in JP-A-6-326132, a SiOx film (x <2) on a GaAs substrate
When a heat treatment is performed by stacking a SiN film and a SiN film, Si atoms diffuse into the GaAs substrate, and a conductive layer can be formed. When an SiN film for preventing As from being externally diffused is not laminated on the SiOx film, Si diffusion does not occur, and the doping amount (Si diffusion) changes according to the thickness of the SiN film. FIG. 4 shows the thickness of the SiN film laminated on the SiOx film and GaAs.
4 shows a relationship between sheet resistance values of a conductive layer diffused in an s substrate. As shown in FIG. 4, by providing a film thickness distribution on the upper SiN film and performing a heat treatment, the sheet resistance changes, that is, a distribution can be provided in the carrier concentration of the doping layer. By gradually increasing the thickness of the SiN film from the end of the gate electrode to the high-concentration layer and performing a heat treatment, the area between the end of the gate electrode and the high-concentration layer is continuously doped from the gate electrode side to the high-concentration layer side. A distribution in which the carrier concentration of the layer is increased can be formed. The change in the carrier concentration of the doping layer changes the doping depth when doping the GaAs substrate with Si by diffusion.

As described above, according to the present invention, the carrier concentration of the doping layer changes continuously from the gate electrode side to the high concentration layer between the end of the gate electrode and the high concentration layer, with a high yield by an easy process. It is possible to provide a compound semiconductor device such as a field-effect transistor in which a doping layer can be formed, a source resistance and the like can be reduced, and a gate withstand voltage can be increased, and element characteristics can be improved.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing the compound semiconductor device according to the first embodiment of the present invention for each manufacturing process. In the first embodiment, a GaAs substrate is used as a typical example of a compound semiconductor, and is applied to a field-effect transistor manufactured by a self-alignment process using a dummy gate inversion pattern. A first embodiment of the present invention will be described with reference to FIGS.

First, a 150-nm thick SiN film 2 for through ion implantation is formed on a GaAs substrate 1 by plasma CVD (see FIG. 1A). This SiN film 2
Are the following film forming conditions: SiH ₄ : 15 sccm, NH ₃ : 2
00 sccm, N ₂ : 100 sccm, RF power: 2
The film is formed at 50 W and a film forming temperature of 300 ° C.

Subsequently, a photoresist is coated on the SiN film 2, exposed and developed so as to open a channel portion, and patterned, and then, using the photoresist 3 as a mask, firstly from the surface side of the GaAs substrate 1. Mg is implanted to a predetermined depth by an ion implantation method to form a p ^- type buffer layer. Successively, Si is implanted from the surface thereof to a uniform depth shallower than the buffer layer by the same ion implantation method to form a channel layer 4 serving as an n-type operation layer (see FIG. 1B). . The injection conditions for the buffer layer are as follows:
Mg is used as a dopant, and the implantation energy is 170
The implantation is performed at a keV and an implantation amount of 1 × 10 ¹² cm ^−2. The implantation conditions of the channel layer 4 are Si using a dopant, the implantation energy is 100 keV, and the implantation amount is 2 × 10 ¹² cm ⁻² .

Next, after the photoresist 3 and the SiN film 2 are removed, an SiOx film 5 having a thickness of 150 ° and a SiN film 6 having a thickness of 50 ° are deposited by a plasma CVD method.
In this SiOx film 5, x <2, and the following film forming conditions: SiH ₄ : 10 sccm, N ₂ O: 20 sccm, R
The film is formed at an F power of 150 W and a film forming temperature of 300 ° C. The SiN film 6 is formed under the following film forming conditions: SiH ₄ : 1
_{5sccm, NH 3: 200sccm, N} 2: 100sc
cm, RF power: 250 W, film forming temperature: 300 ° C. Then, a PGMEA-based photoresist is applied on the SiN film 6 with a thickness of 1.5 μm, and then exposed and developed so as to form a dummy gate pattern. A dummy gate pattern 7 having a taper is formed by patterning the photoresist (see FIG. 1C).

As shown in FIG. 2, when the dummy gate pattern 7 is patterned so that the gate length becomes 0.4 μm, the dummy gate pattern 7 becomes tapered at an angle of 60 ° with respect to the GaAs substrate 1, and the resist At the top, the gate edge
It is formed to protrude from a at a width of 0.87 μm.

Thereafter, an SiN film 8 having a thickness of about 500 ° is formed on the entire surface of the substrate by ECR-CVD. that time,
Since the resist pattern 7 has a taper, the SiN film 8 is not deposited in the vicinity of the gate electrode, and the thickness distribution of the SiN film 8 becomes thicker as the distance from the gate electrode increases, and is formed in a self-aligned manner (see FIG. 1D). ).

This SiN film 8 is formed under the following film forming conditions: SiH
₄ : 10 to ₂₀ sccm, N2: 25 sccm, microwave power: 300 to 600 W, magnet current: 16
A, Film formation temperature: room temperature. In this embodiment, SiH ₄ : 10 sccm, N ₂ : 25 sccm, microwave power: 300 W, magnet current: 16 A, film formation temperature: room temperature.

The SiN film 8 is deposited to suppress the external diffusion of As, and any other material than the SiN film may be used as long as it has the same effect.
A film, a WSi film, a WSiN film, or the like can be used.

Next, the SiN film on the resist is removed by a lift-off method, and a lamp annealing (RTA) process is performed at 880 ° C. for about 5 seconds in an N ₂ atmosphere. By this heat treatment, Si is diffused from the SiOx film 5 into the GaAs substrate 1. As described above, depending on the thickness of the SiN film 8,
Changes the doping depth (doping depth). The portions of the SiN film 8 located at the drain region 9d and the source region 9s are A
It has a thickness enough to suppress the external diffusion of s, and a high concentration diffusion layer is formed. Then, the SiN film 8
As the film thickness of the layer gradually decreases, a doping layer 9a in which the depth of the red pink layer becomes shallower due to this film thickness distribution can be formed (see FIG. 1E). As a result, the doping layer 9a in which the carrier concentration of the doping layer continuously increases from the gate electrode side to both sides between the gate electrode end and the drain region 9d and the source region 9s formed of a high concentration diffusion layer. Is formed.

Subsequently, the SiN film 8, SiN film 6, and SiOx film 5 located at positions corresponding to the drain region 9d and the source region 9s, respectively, are etched and removed.
d, Exposing the surface of the source region 9s, AuGe / Ni
A drain electrode 10d and a source electrode 10s made of a multilayer metal film of / Au are formed. Further, the SiN in the gate region
The film 6 and the SiOx film 5 are removed by etching to expose the surface, and a gate electrode 11 composed of a multilayer metal film of Ti / Pd / Au is formed (see FIG. 1F).

According to the above-described method, a field effect transistor having a doping layer in which the carrier concentration of the doping layer continuously changes from the gate electrode side to the high concentration layer between the end of the gate electrode and the high concentration layer can be formed. . As a result,
The resistance of the source and the like can be reduced and the gate withstand voltage can be increased, and the element characteristics can be improved.

In the above-described embodiment, the dummy gate pattern 7 is formed as a dummy gate pattern 7 in order to provide the SiN film formed on SiOx with the film thickness being gradually increased from the end of the gate.
Although it is formed in a tapered shape by using an MEA-based single-layer resist, as shown in FIG.
Using two resists, a lower layer is coated with a PMGI-based resist 7a with a thickness of 1.3 μm, and a PMMA-based resist 7b is coated thereon with a thickness of 0.5 μm.
When a dummy gate pattern having a gate length of 0.4 μm is patterned, the first layer is exposed and developed to a width of 0.4 μm, and the second layer is developed and developed to a width of 2 μm. An umbrella portion will be formed. When an SiN film 8 is formed on the entire surface of the substrate using the dummy gate pattern 7 in the same manner as described above, an SiN film 8 having a film thickness distribution is formed.

FIGS. 5 and 6 are sectional views showing a compound semiconductor device according to a second embodiment of the present invention for each manufacturing process. In the second embodiment, as a typical example of a compound semiconductor, the present invention is applied to a field-effect transistor manufactured by a self-alignment process using a dummy gate inversion pattern using a GaAs substrate. A second embodiment of the present invention will be described with reference to FIGS.

First, a 150-nm thick SiN film 2 for through ion implantation is formed on a GaAs substrate 1 by plasma CVD (see FIG. 5A). This SiN film 2
Are the following film forming conditions: SiH ₄ : 15 sccm, NH ₃ : 2
00 sccm, N ₂ : 100 sccm, RF power: 2
The film is formed at 50 W and a film forming temperature of 300 ° C.

Subsequently, a photoresist is coated on the SiN film 2, exposed and developed so as to open a channel portion, and patterned, and then, using the photoresist 3 as a mask, firstly from the surface side of the GaAs substrate 1. Mg is implanted to a predetermined depth by an ion implantation method to form a p ⁻ -type buffer layer. Successively, Si is implanted from the surface to a uniform depth shallower than the buffer layer by the same ion implantation method to form the channel layer 4 serving as an n-type operation layer (see FIG. 5B). . The injection conditions for the buffer layer are as follows:
Mg is used as a dopant, and the implantation energy is 170
The implantation is performed at a keV and an implantation amount of 1 × 10 ¹² cm ^−2. The implantation conditions of the channel layer 4 are Si using a dopant, the implantation energy is 100 keV, and the implantation amount is 2 × 10 ¹² cm ⁻² .

Next, the photoresist pattern 3 is removed. Subsequently, a photoresist is applied to the entire surface of the substrate, exposed, developed, and patterned to form a dummy gate having a width of 1.5 μm. The thickness is reduced from 1.5 μm to 0.5 μm. After that, resist and Si
An SiO ₂ film having a thickness of about 2500 ° is formed on the entire surface of the N film by the ECR-CVD method, and then a SiO ₂ film 15 having a pattern obtained by inverting the dummy gate is formed by a lift-off method (see FIG. 5C).

Next, after removing the SiN film 2 at the gate portion formed by the SiO ₂ film 15 by RIE, the thickness is 1500/4500/50 by sputtering.
Multilayer metal film 1 composed of 0 ° WSiN / Au / WSiN
6 is deposited on the entire surface (see FIG. 5D).

After that, patterning technology and RIE
The multi-layered metal film 16 made of WSiN / Au / WSiN other than the gate electrode is removed by etching using a method and an ion milling method to form a T-shaped gate electrode 17 (see FIG. 5E).

Further, after removing the SiO ₂ film 15 and the SiN film 2 in which the dummy gate pattern is inverted by a BHF process, the film thickness is 150/5 by a plasma CVD method.
A 0 ° SiOx / SiN film 18 is formed (FIG. 5F).
reference). In this SiOx film, as in the above-described first embodiment, x <2, and the following film forming conditions, SiH
₄ : 10 sccm, N ₂ O: 20 sccm, RF power:
The film is formed at 150 W and a film forming temperature of 300 ° C. Also, S
The iN film was formed under the following film forming conditions: SiH ₄ : 15 sccm, N
H ₃ : 200 sccm, N ₂ : 100 sccm, RF power: 250 W, film formation temperature: 300 ° C.

Subsequently, a thickness of 10 mm was formed by ECR-CVD.
A SiN film of about 00 ° (may be 500 ° as in the first embodiment) is formed. At this time, the SiN film 19 is not deposited on the foot portion of the T-shaped gate electrode 17, and the thickness distribution of the SiN film 19 is formed in a self-aligned manner. That is,
The SiN film 19 is not deposited in the vicinity of the foot of the T-shaped gate electrode 17, and the thickness distribution of the SiN film 19 becomes thicker as the distance from the vicinity of the foot of the gate electrode 17 increases. )reference).

The SiN film 19 is formed under the following film forming conditions:
_{H 4: 10~20sccm, N 2:} 25sccm, microwave power: 300～600W, magnet current: 16
A, Film formation temperature: room temperature. In this embodiment, SiH ₄ : 10 sccm, N ₂ : 25 sccm, microwave power: 300 W, magnet current: 16 A, film formation temperature: room temperature.

The SiN film 19 is deposited in order to suppress the external diffusion of As, as in the first embodiment described above.
Other than N film, for example, AlN film, WSi
A film, a WSiN film, or the like can be used.

Next, a lamp annealing (RTA) treatment is performed at 880 ° C. for about 5 seconds in an N ₂ atmosphere. By this heat treatment, Si is diffused from the SiOx film 18 into the GaAs substrate 1. As described above, the diffusion amount (doping depth) of Si changes according to the thickness of the SiN film 19. The portion of the SiN film 8 located at the drain region 9d and the source region 9s has a thickness enough to suppress the external diffusion of As, and a high concentration diffusion layer is formed. And SiN
As the film thickness of the film 19 gradually decreases, the doping layer 9a in which the depth of the lido pink layer becomes shallower due to this film thickness distribution.
Can be formed (see FIG. 6B). As a result, the doping layer 9a in which the carrier concentration of the doping layer continuously increases from the gate electrode side to both sides between the gate electrode end and the drain region 9d and the source region 9s formed of a high concentration diffusion layer. Is formed.

Subsequently, the SiN film 19 and the SiOx film at the positions corresponding to the drain region 9d and the source region 9s, respectively.
The film / SiN film 18 is etched and removed, and the drain region 9 is removed.
d, Exposing the surface of the source region 9s, AuGe / Ni
A drain electrode 10d and a source electrode 10s made of a multilayer metal film of / Au are formed (see FIG. 6C).

According to the above-described method, a field effect transistor having a doping layer in which the carrier concentration of the doping layer continuously changes from the gate electrode side to the high concentration layer between the end of the gate electrode and the high concentration layer can be formed. . As a result,
The resistance of the source and the like can be reduced and the gate withstand voltage can be increased, and the element characteristics can be improved.

In the above embodiment, the SiN film formed to suppress the external diffusion of As is formed by ECR-CVD.
Although formed by the method, the SiN film having a distribution in the film thickness can be deposited by controlling the conditions of the gas pressure and the like also in the plasma CVD method.

In the above-described embodiment, II
A GaAs substrate was used as the group IV compound semiconductor,
The present invention relates to InP, AlAs, AlGaAs,
InAlAs-based compound semiconductors and such III-V
The present invention can be similarly applied to an apparatus using a heterojunction substrate including a plurality of layers of a group III compound semiconductor.

In the above embodiment, the substrate on which the operation layer is formed by ion implantation has been described. However, a substrate manufactured by an evitaxial technique may be used. Further, the present invention can be applied to devices such as HEMTs and TMTs in addition to MESFETs.

[0048]

As described above, according to the present invention, the yield is increased by an easy process, and the doping in which the gate electrode side has a low concentration and the continuous concentration distribution continuously increases toward the high concentration layer between the gate electrode and the high concentration layer. A layer can be formed, the source resistance and the like can be reduced, the gate breakdown voltage can be increased, and the element characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a compound semiconductor device according to a first embodiment of the present invention for each manufacturing process.

FIG. 2 is a sectional view showing a dummy gate pattern used in the first embodiment of the present invention.

FIG. 3 is a sectional view showing a dummy gate pattern used in the first embodiment of the present invention.

FIG. 4 shows the thickness of a SiN film laminated on a SiOx film and Ga
FIG. 4 is a characteristic diagram showing a relationship between sheet resistance values of a conductive layer diffused into an As substrate.

FIG. 5 is a cross-sectional view showing a compound semiconductor device according to a second embodiment of the present invention for each manufacturing process.

FIG. 6 is a cross-sectional view showing a compound semiconductor device according to a second embodiment of the present invention for each manufacturing step.

FIG. 7 is a cross-sectional view showing a conventional MESFET manufacturing method for each process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 GaAs substrate 4 Channel layer 5 SiOx film 6 SiN film 7 Dummy gate pattern 8 SiN film 9s Source region 9d Drain region 9a Doped layer 10s Source electrode 10d Drain electrode 11 Gate electrode

Continued on the front page F-term (reference) 5F102 FA01 FA03 GB01 GC01 GD01 GJ04 GJ05 GJ06 GK05 GL05 GS04 GT03 GV07 GV08 HA04 HC00 HC07 HC19 HC21

Claims (4)

[Claims] A gate electrode provided on an operation layer made of a group III-V compound semiconductor; and a high-concentration impurity layer provided in the operation layer. A compound semiconductor device, comprising: a doping layer having a sheet resistance value continuously changing from a gate electrode side to a high-concentration impurity layer side between the layer and the layer. 2. A silicon oxide film (SiOx) in which non-doped Si is diffused on a III-V compound semiconductor substrate.
Forming a film on the SiOx film having a film thickness distribution in which the film thickness gradually increases in a direction away from the gate electrode contact portion to prevent external diffusion of group V atoms. Heat-treating the compound semiconductor substrate with the SiO 2
forming a doping layer in which a sheet resistance value changes continuously from the high-concentration impurity layer and the gate electrode side to the high-concentration impurity layer side in the substrate by diffusing silicon in the x film;
A method for manufacturing a compound semiconductor device, comprising: 3. A dummy gate pattern having an uppermost width wider than a width in contact with the substrate is formed, and the SiO2 is lifted off using the dummy gate pattern as a mask.
3. The film according to claim 2, wherein a film is formed on the x film, the film having a film thickness distribution in which the film thickness is gradually increased in a direction away from the gate electrode contact portion to prevent external diffusion of group V atoms. A method for manufacturing a compound semiconductor device. 4. A silicon oxide film (SiOx) in which non-doped Si is diffused on a III-V compound semiconductor substrate.
Forming a T-shaped gate electrode on the compound semiconductor substrate, and separating the gate electrode from the contact portion of the gate electrode on the SiOx film by lift-off using the gate electrode as a mask. Forming a film having a film thickness distribution in which the film thickness sequentially increases in a direction to prevent external diffusion of group V atoms, and performing heat treatment to diffuse silicon in the SiOx film into the compound semiconductor substrate. Forming a high-concentration impurity layer and a doping layer having a sheet resistance continuously changing from the gate electrode side to the high-concentration impurity layer side in the substrate.