JPS58130572A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the device which is operated at a high speed, in a heterojunction comprising a first semiconductor layer which does not include impurities and has a narrow band gap and a second semiconductor layer which is connected to the first layer and has a wide band gap, by sequentially increasing the impurity distribution in the second semiconductor layer in the order of the part beneath a gate electrode, the region between the gate electrode and an ohmic electrode, and the part beneath the ohmic electrode. CONSTITUTION:On a semiinsulating GaAs substrate 1, an undoped GaAs layer 2, which is the first semiconductor layer having the narrow band gap, is epitaxially grown. An undoped Ga0.7Al0.3 As layer 3, which is the second semiconductor layer having the wide band gap is grown on the layer 2. Then the entire surface is coated by an SiO2 film 4. A gate pattern 5 comprising Ti or W is provided on the central part of the surface of the film 4. A mask 12 for ion implantation is formed around the pattern 5, and Si ion implanting layers 6 and 7 are formed. The impurity distribution at this time is controlled so that it is different from each other beneath each electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a semiconductor device suitable for use as a logic system for an ultra-high-speed computer, and a method of using the semiconductor device.

A conventional high carrier mobility device with a heterojunction is a so-called Metal-Mobility device in which an electrode is in direct contact with a semiconductor layer.
8emiconductor PET (~4ES-F
ET). For this reason, if the gate capacitance is large and the gate positive bias is increased, the gate current will flow, and therefore, as the gate bias is increased, the device current will increase. First, it had to be used at a voltage lower than the withstand voltage of the electrode. for example,
T, Mimura et al., Japanese Journal
al of Applied Physics No. 20
This type of semiconductor device is disclosed in Vol. 5, L317-319 (1981).

The present invention is formed by a first semiconductor layer (FIG. 1, 2) having a narrow bandgap that does not substantially contain impurities and a second semiconductor layer (FIG. 1, 3) having a wide bandgap in contact therewith. This is an improvement of a type of semiconductor device in which two-dimensional carriers generated at a heterojunction interface are controlled by carrier control means. A potential well is formed at the heterojunction interface into which carriers flow from the wide band gear and semi-thin layer.

An object of the present invention is to reduce the gate capacitance and increase the device current by increasing the positive bias of the gate by using an insulated gate as the Sirotchi electrode of the high carrier mobility transistor, thereby making it possible to increase the speed. .

This method simultaneously increases the breakdown voltage between the gate and drain and between the source and drain. Another object of the present invention is to reduce Coulomb scattering of carriers by eliminating impurities in the semiconductor layer directly below the goo 1.

The gist of the feature of the present invention is that the impurity distribution in the second semiconductor layer increases in the following order: under the gate electrode, in the region between the gate and ohmic electrode, and under the ohmic electrode;
Another method is to insert an insulating film between the gate electrode and the semiconductor layer.

The step-like impurity doping is achieved by generating a two-dimensional electron gas that serves as carriers close to the gate electrode, and by reducing the corresponding impurity concentration between the gate and the source and drain. , which has the role of preventing punch-through between the source and drain.

Hereinafter, the present invention will be explained in detail using Examples.

As shown in FIG. 1, a semi-insulating GaAs substrate 1 (plane orientation 1
00), an undoped GaAa layer 2 (thickness 0.1 μm) (corresponding to the first semiconductor layer) is grown by the molecular beam epitaxy method (MBE method), and further undoped GaAa layer 2 (corresponding to the first semiconductor layer) ,,As layer 3 (thickness 0.05μ
m) (corresponding to the second semiconductor layer having a wide bandgap). Next, it is moved from the crystal growth chamber in the MBE apparatus to the substrate processing chamber in the same MHI apparatus without being exposed to the atmosphere, where a 5tO2 film 4 with a thickness of 100λ is deposited by the Prazu rcVD method. Thereafter, Ti and W are deposited as gate metals, and a gate pattern 5 is formed by lithography (see FIG.
a)). Next, an ion implantation mask 12 is made by lithography. Accordingly, isolation of the element is performed. Using this mask 12, silicon ions are implanted at an acceleration voltage of 10 keV, and the dose is set to I
10"cm-" (Fig. 1(b)). The distribution of the implanted ions in the thickness direction at this time is shown in FIG. Since the implanted layer is extremely thin, it has a steep impurity distribution. Next, after removing the mask 12, a mask 13 with only the ohmic electrode portion opened is created, and the oxidized layer 4 is etched using the mask 13. After that, silicon ions were accelerated at an acceleration voltage of 10 keV and at a dose of lX1o l2.
Insert it so that it becomes cm-2 (Fig. 1 (C)).

Because there is no 5in2 film, the silicon is implanted closer to the heterojunction than in the first implant. Under the conditions of this example, only 20 nm from the heterojunction interface appears as a region where donor ions do not exist.

After removing the resist mask 13 after implantation, annealing is performed to activate the implanted ions (see Fig. 1(d)).
)). Thereafter, a resist mask for the ohmic electrode is created, and the ohmic electrode is formed by a normal lift-off method (FIG. 1(e)). Below, bonding pads, wiring, etc. are manufactured. The transconductance gm of the obtained device was 150 On@/nm at 77 nm, and the transconductance gm of the 21-stage ring-o-silator using this semiconductor device was 150 On@/nm.
The delay time of the step (at the bottom) was 15n3.

9 shown in FIG. 2(e) is 2 generated at the heterojunction interface.
Dimensional electron gas 10 indicates a region where this two-dimensional electron gas is not generated.

the second semiconductor layer of the first semiconductor layer having a narrow bandgap;
A third semiconductor layer having a wide band gear may be provided opposite to the interface with the hand/curtain layer.

Further, this layer may be a semiconductor layer of a conductivity type opposite to that of the second semiconductor layer. An example of this will be explained next. FIG. 3 is a sectional view of such an example device. 11 is a newly provided third semiconductor layer. In FIG. 3, the same symbols as in FIG. 1 indicate the same parts.

Undoped A-o4 was deposited on a semi-insulating 1np substrate 1 (plane orientation 100) by metal organic pyrolysis (MO-CVD) method.
81n (1,,2 AB layer (thickness o, 5 μm) 11. Undoped Ga,,,in,!13As layer (thickness 0, 1
μrn ) 2 e undoped Aj, 4. In(1,
1I2As layer (thickness 0.057!m) 3 was formed, and Sio was formed thereon.

A film (10 nm thick) is deposited. The process under μ is the same as the previous example.

Since the device manufactured in this example has a buffer layer 11 made of a wide band gear and semicircular material, it is characterized in that residual current is extremely small when a gate bias is applied in the negative direction. Similar effects can be obtained by using semiconductor layers of opposite conductivity types.

[Brief explanation of the drawing]

FIGS. 1A to 1E are cross-sectional views of a semiconductor device according to an embodiment of the present invention, showing the manufacturing process thereof. FIG. 2 is a diagram showing the distribution of implanted ions in the depth direction in the apparatus shown in the embodiment, and FIG. 3 is a sectional view showing another embodiment. 1: Semi-insulating substrate, 2: Undoped narrow band gap layer, 3: Undoped wide band gap layer. 4: Insulating film, 5: Gate electrode, 6: First implantation layer, 7: Second implantation layer, 8: Ohmic electrode, 9: Two-dimensional electron gas generated at the hetero interface, 10: Two-dimensional electron gas Non-occurring regions, 11: wide bandgap semiconductor layer, 12 and 13: photoresist mask. -

Claims (1)

[Scope of Claims] 1. Occurrence at the Peter junction interface between a first semiconductor layer that does not substantially contain impurities and has a narrow bandgap, and a second semiconductor layer that is in contact with this and has a wide bandgap. In a semiconductor device in which a dimensional carrier gas is controlled by a carrier control means, the impurity distribution in the second semiconductor layer increases in the following order: under the gate electrode, in the region between the gate electrode and the ohmic electrode, and under the ohmic electrode;
A semiconductor device further comprising an insulating film between the gate electrode and the semi-active layer. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that the first semiconductor layer includes a third semiconductor layer having a conductivity type opposite to that of the second semiconductor layer or having a wide bandgap that does not substantially contain impurities.