JP2541260B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a field effect transistor.

[Outline of Invention]

The present invention is a method for manufacturing a semiconductor device, in which a gate material to be formed in an atmosphere containing a raw material gas is irradiated with an electron beam to deposit a resist material serving as a mask for forming the gate, and the electron beam irradiation is performed. By forming the channel region by reducing the carrier concentration of the δ-doped layer immediately below the portion, a field effect transistor having a fine gate length can be obtained.

[Conventional technology]

A conventional field-effect transistor is manufactured by self-alignment for the purpose of reducing the resistance between the source and the gate by sandwiching the distance between the source and the drain. Specifically, after the gate is formed, n-type impurity ions are implanted using the gate as a mask to form n ⁺ source and drain regions in the semiconductor layers on both sides of the gate.

[Problems to be solved by the invention]

According to the conventional manufacturing method described above, the gate and source regions,
In order to prevent a short circuit between the drain regions, it is necessary to form sidewalls, which complicates the process and lowers the yield. In order to prevent a short circuit, it is sufficient to form a δ-doped channel region, but since the ion implantation step and the annealing step are indispensable in the manufacturing process, there is a possibility that the steep impurity distribution of the formed δ-doped layer may collapse. There is. Also, the gate length Lg of the conventional semiconductor device is 1 to 1/4 μm, but since the sidewall width is several hundred Å × 2 (being on both sides of the gate), a gate length of about 1000 Å or less is not acceptable. Get as close as possible. In order to reduce the gate length Lg to 1000 Å or less, electron beam writing is required. However, because the high-resolution resist has poor resistance to reactive ion etching (RIE), an extremely fine gate is formed by lift-off. There is.
However, according to this method, it is impossible to form by self-alignment.

The present invention provides a method for manufacturing a semiconductor device that can solve the above problems.

[Means for solving problems]

In the method of manufacturing the semiconductor device (13) according to the present invention, δ
Insulating semiconductor layers (3a) vertically on both sides of the doped layer (4),
(3b), a step of forming a gate metal layer (8) on the surface of the insulating semiconductor layer (3b), and an electron beam (8) at the gate portion to be formed in an atmosphere containing a source gas. And deposit the resist material (10),
A step of forming a channel region (12) by reducing the carrier concentration of the δ-doped layer (4) immediately below the resist material (10) by an electron beam (9), and using this resist material (10) as a mask The method is characterized by comprising the step of selectively removing the layer (8) to form the gate (11).

A method of depositing a resist material (10) on a substrate by irradiating it with an electron beam (9) in an atmosphere containing a source gas has already been proposed (for example, Japanese Patent Application No. 62-
See 299405).

[Action]

As shown in the means for solving the above problems, the electron beam (9) is deposited by irradiating the gate portion to be formed in the atmosphere containing the source gas with the electron beam (9). Since the carrier concentration of the δ-doped layer (4) immediately below the resist material (10) is reduced by 9) to form the channel region (12), the resist material (10 serving as a mask for forming the gate (11) is formed. ) And the channel region (12) can be formed simultaneously. Moreover, since the channel region (12) is formed by self-alignment, the effective source region (5A) and drain region (6A) are formed.
It is also possible to form an interval between them, that is, a gate length Lg of 1000 Å or less.

[Embodiment] An embodiment of the present invention will be described with reference to the drawings.

First, as shown in FIG. 1A, after an insulating AlGaAs layer (2) is formed on a GaAs substrate (1), a carrier (electron in this example) band (conduction band in this example) is not formed on the insulating AlGaAs layer (2). The GaAs layer (3a), which is a semiconductor layer that produces continuity, is formed without doping impurities, and δ-doped with high-concentration impurities.
A Si layer (n _S 10 ¹³ cm ^-2 ) (4) is formed, and an insulating GaAs layer (3b) is further formed thereon.

Next, as shown in FIG. 1B, the ohmic metal layer (7) is formed on the portion where the source region (5) and the drain region (6) are to be formed by photolithography at an interval of about 1 to 0.5 μm.
After selectively forming a) and (7b), they are heated and alloyed to form a source region (5) and a drain region (6) in the insulating GaAs layers (3a) and (3b).

Then, as shown in FIG. 1C, a gate metal is formed on the front surface.
After depositing Al to form an Al layer (8), the resist material (10) is deposited by irradiating only a gate portion to be formed with an electron beam (9) in an atmosphere containing alkylnaphthalene as a source gas, for example. , Δ-doped Si layer (4) located directly under the resist material (10) by this electron beam (9)
By damaging the carrier and lowering the carrier concentration (the concentration decreases by about one digit, n _S becomes about 10 ¹² cm ^-2, and this concentration itself can also be controlled by the electron beam energy and number density). (11) The δ-doped Si layer (4) immediately below can be used as a channel region (12) that can be sufficiently pinched off by a gate bias.

Next, as shown in FIG. 1D, a gate (11) is formed by etching the Al layer (8) using this resist material (10) as a mask, and a field effect transistor (gate) having an extremely small gate length Lg ( 13) is prepared.

According to the field effect transistor (13) of the above-mentioned embodiment, n _S of the original δ-doped Si layer (4) which is not damaged by the irradiation of the electron beam (9) is about 10 ¹³ cm ^-2 ,
The volume concentration by be distributed in the region of about several tens ^{Å, n10 13 cm -2 / 50Å10} 13/50 × 10 -8 cm -3 = 2 × 10 19
Corresponding to cm ^-3 , almost the same as metal. Therefore, the effective channel region (12) between the source region (5A) and the drain region (6A) has the gate length Lg. As described above, since the channel region (12) can be formed by self-alignment, Lg can be formed at 1000 Å or less, and the short channel effect can be suppressed.

That is, according to the above manufacturing method, the channel region (12) that is sufficiently pinched off by the irradiation of the electron beam (9), the effective source region (5A), the drain region (6A), and the gate (1).
A resist material (10) serving as a mask for forming 1) can be simultaneously formed by self-alignment.
The steps required to manufacture the present field effect transistor include the required epitaxial layers (2), (3
After forming a), (4), and (3b) and forming the source region (5) and the drain region (6), there are two steps of irradiation process of electron beam (9) and etching process of Al layer (8). Since the process is sufficient and the film can be formed by self-alignment, the manufacturing process can be significantly simplified.

〔The invention's effect〕

According to the present invention, a resist material serving as a mask for forming a channel region directly below a gate and a gate can be formed by self-alignment. Since the distance between the effective source region and the effective drain region becomes the gate length, a semiconductor device having a minute gate length of 1000Å or less can be obtained. Moreover, according to this manufacturing method, since the depth from the surface to the channel region is shallow, the influence of multiple scattering at the time of electron beam irradiation is reduced, and the controllability of the gate length is improved. Moreover, since the main steps can be performed by self-alignment, the manufacturing becomes extremely simple.

[Brief description of drawings]

FIG. 1 is a process drawing of the embodiment. (1) is a GaAs substrate, (3a) and (3b) are insulating GaAs layers,
(4) is a δ-doped Si layer, (5) is a source region, (6) is a drain region, (8) is an Al layer, (9) is an electron beam,
(10) is a resist material, (11) is a gate, (12) is a channel region, and (13) is a field effect transistor.

Claims (1)

(57) [Claims] 1. A step of forming an insulating semiconductor layer on and under a δ-doped layer, a step of forming a gate metal layer on the surface of the insulating semiconductor layer, and a step of forming the gate metal layer in an atmosphere containing a source gas. A step of irradiating the gate portion with an electron beam to deposit a resist material and, at the same time, decreasing the carrier concentration of the δ-doped layer immediately below the resist material by the electron beam to form a channel region, and using the resist material as a mask And a step of selectively removing the gate metal layer to form a gate.