JPS6018970A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the semiconductor device having uniform characteristics and the minimum parasitic resistance by a method wherein the edge of an N<+> active layer is brought close to a gate electrode in the extreme limits and, at the same time, their positional relations are determined in a self-matching manner. CONSTITUTION:SiO2 12 containing Sn is coated on a high resistance GaAs 11, and an Si ion implantation layer 13 is formed through the film 12. An aperture is provided on the SiO2 film 12, a heat treatment is performed, and an N-layer 14 and an N<+> layer 15 are formed. The above is formed thicker than the impurity diffusion length in GaAs by covering Si3N4 thereon, and an Si3N4 film 6 is left on the side face of the SiO2 film 12 by performing an anisotropic etching. At this time, the N<+> layer 15 and the N-layer 14 are partially covered by the film 16. Then, an Al gate electrode 17 is provided, and an ohmic source electrode 18 and a drain electrode 19 are attached to the N<+> layer 15. According to this constitution, as the N<+> active layer 15 and the gate electrode 17 can be brought closer in the utmost limits by controlling the thickness of the second film 16, the parasitic resistance can be reduced to the extreme limits. Also, as the position of the gate electrode and the N<+> active layer can be effectively determined by self- matching, no irregularity in parasitic resistance is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device such as a diode, a field effect transistor, or a semiconductor integrated circuit in which these are integrated.

In recent years, the development of ultra-high-speed integrated circuits using gallium arsenide (GaAs), which has an electron mobility 3 to 5 times that of silicon (Si), has been progressing.
) is generally manufactured by forming an n-type trench conductive layer on a semi-insulating GaAs substrate, and building and integrating components such as diodes and field effect transistors on the conductive layer. In order to improve the performance of a cough IC, it is necessary to reduce the parasitic resistance of the constituent elements. FIG. 1 shows the structure of a typical field effect transistor designed to reduce parasitic resistance. In Figure 1, semi-insulating or high-resistance GaA
n +1! in contact with the nWGaAs layer 2 formed on B1!
! ! A GaAs layer 3 is formed, a gate electrode 5 is provided on the nuGaAs layer, a source electrode 4 and a drain electrode 6 are provided on the n+ GaAs layer, and the source and drain electrodes and the n+ GaAs layer are in ohmic contact. none,
Electrons injected from the source electrode pass through the n-type GaAs layer under the gate electrode, which forms a 7-way junction with the n-type GaA 8 layer, that is, the channel, and reach the drain. Therefore, in order to further reduce the parasitic resistance of the field effect transistor shown in FIG. It is necessary to place the gate electrode close to the gate electrode so that the gate reverse breakdown voltage of the field effect transistor does not become a practical problem. The field effect transistor shown in FIG. 1 is an n-type GaAs
In order to manufacture this with a high yield, it is necessary to provide a sufficient distance between the edge of the n''-1 GaAs layer and the gate electrode, and the value of the parasitic resistance must be adjusted to match the position of the gate electrode. Because it depends on the precision of the field effect transistor, its characteristics vary.
C had the drawback that its performance could not be sufficiently improved.

The object of the present invention is to eliminate the above-mentioned drawbacks, bring the edge of the %n+a active layer as close as possible to the gate electrode, and determine the positional relationship in a self-aligned manner, thereby achieving good performance and characteristics with minimum parasitic resistance. An object of the present invention is to provide a method for manufacturing a uniform semiconductor device.

A method for manufacturing a semiconductor device according to a first aspect of the present invention includes the steps of: depositing a first film containing an impurity that becomes a conductive layer in the semiconductor on a high-resistance semiconductor; A process of ion-implanting an impurity having the same conductivity type as the impurity contained in the first film, a process of removing a part of the first film, a process of heat treatment, a process of depositing a second film, a step of removing the second film by anisotropic dry etching to expose the semiconductor surface; a step of providing an electrode covering the exposed semiconductor surface; and a step of removing a part of the first film. A method for manufacturing a semiconductor device according to a second aspect of the present invention, which includes the step of providing at least another electrode, is a method of including an impurity on a high-resistance semiconductor that has one conductivity in the semiconductor. A step of depositing a first film, a step of removing a part of the first film, and using the first film as a mask, ionize the impurity having the same conductivity type as the impurity having the same conductivity type. a step of implanting, a step of heat treatment, a step of depositing a second film, a step of removing the second film by anisotropic dry etching to expose the semiconductor narrow surface f: and the exposed semiconductor. The method includes a step of providing one electrode covering the surface, and a step of removing a portion of the first film to provide at least another electrode.

Next, embodiments of the present invention will be described in detail using the drawings.

2(a) to 2(e) are cross-sectional views showing the process order for explaining one embodiment of the first invention of the present invention. As shown in FIG. 2(a), high resistance GaAs 11 is GaAs
After depositing, for example, a silicon dioxide (SiOz) film as the first film 12 containing tin (8n), which becomes an n-type impurity in GaAs, Si ions, which can mainly become an n-type impurity in GaAs, are deposited as the first film 12. (Ion implantation is performed through the Jz film to form the S1 ion implantation layer 13.

Next, as shown in FIG. 2(b), after removing a part of the SiO2 film, that is, the first film 12 on at least a part of the region where the gate electrode will be provided later, the GaAS is removed. 800℃15 in an atmosphere that does not decompose, such as an arsenic atmosphere
A heat treatment is performed for a minute to activate the silicon in the Si ion-implanted layer 13 to form an NFL active layer 14, and to diffuse the impurity Sn in the first film into GaAs to form an N+ type active layer 15.

Next, as shown in FIG. 2(C), the exposed G a A
For example, a silicon nitride film (SisN4
) or deposit a second film 16 of 5r (Jz film) without pouring ViBn.

Note that from the step of removing a part of the first film 12 to the step of depositing the second film shown in FIG. 2 (1) to fcl in FIG. Even if the second film 16 is subsequently deposited and then subjected to heat treatment, the n-type active layer 14 and the n + -type active layer 15 are obtained in the same manner as described above. In the heat treatment in this case, the GaAs surface is covered with the first film or the second film, so it is not necessarily necessary to perform the heat treatment in an arsenic atmosphere.

Next, as shown in FIG. 2(d), the second layer 16 is removed by anisotropic dry etching to expose a portion of the n-type active layer. At this time, the first film 12 must not be completely removed. Using anisotropic dry etching, the first film 1
The second film 16 on the side surface of FIG. That is, in the heat treatment described above, the impurities in the Ml film are mixed with GaA in the direction perpendicular to the first film.
In addition to diffusing in GaAs, the impurity that has entered GaAs also diffuses in GaAs in a direction parallel to the first film, that is, in a lateral direction parallel to the GaAs plane.

The lateral diffusion distance is essentially determined by the heat treatment temperature for 1 hour. Therefore, by setting the lateral diffusion distance in advance and depositing the second film thicker than this diffusion distance, the diffusion distance can be increased. removing the second film by anisotropic etching as described above;
Second film 16kn+ left when GaAs surface is exposed
Next, as shown in FIG. 2(e), at least the exposed n-type active layer is covered with, for example, an aluminum layer.
A gate electrode 17 is formed in the n/l active layer to form a Schottky junction, and after removing a part of the first film to expose the entire n-type active layer, it is brought into ohmic contact with the n-type active layer 15. In these five methods, a Schottky contact gate type field effect transistor can be fabricated by forming a source electrode 18 and a drain electrode 19. By controlling the thickness of the second film, the n-type active layer 15 can be fabricated by controlling the thickness of the second film. Since it is possible to bring the gate electrode 17 as close as possible without contacting the gate electrode 17, parasitic resistance can be reduced to the maximum (C), and it is possible to effectively reduce the parasitic resistance (C)! Since the positions of the pole and the n+ active layer are determined in a self-aligned manner, there is no variation in parasitic resistance.

Note that the distribution of impurities in the first film does not have to be uniform, and even if they are localized in layers, that is, even if the impurities have a multilayer structure, by changing the temperature and time of the heat treatment,
Since the depth of the nu active layer can be controlled, the effects of the present invention do not change even if the films with the configurations shown in FIG. 3 fa), (b), and (C) are considered as the first film. It is clear that there is no such thing. In FIGS. 3(a), (b), and (C), 22 is a film containing impurities, 23 is a film not containing cough impurities, 21 is high resistance GaAs, and 1 is a film 22 containing impurities. The impurity-free films 23 do not necessarily have to have the same composition.

In FIG. 3(a), the film 22 containing impurities has a high resistance G a A
3(b), the film 23 not containing impurities is in contact with high resistance GaAs, and the film 23 containing impurities is in contact with GaAs 1 and 2.
2 covers the impurity-free film 23, FIG. 3C shows that the impurity-free film is in contact with the high-resistance GaAs,
This is the case when a film containing impurities is sandwiched between films containing no impurities.

FIGS. 4(a) to 4(e) are sectional views shown in order of steps for explaining an embodiment of the second invention of the present invention.

As shown in FIG. 4(a), for example, 3iυ containing Snf in GaAs is deposited on high-resistance GaAs 11.
After depositing the second film as the first film 12, the first film in the region where the gate electrode is to be formed is removed to expose a part of the high resistance QaAsll.

Next, as shown in FIG. 4(b), using the first film 12 as a mask, a high-resistance GaAs film is passed through the entire opening of the first film.
Silicon ions are implanted into the silicon ion-implanted layer 1.
form 3.

Next, as shown in FIG. 4(C), a second film 16 is deposited and heat treated to form a silicon ion implanted layer 13.
At the same time, for example, Sn and gold are diffused from the first film 12 to form an n+ active layer 15.

Note that here, high-resistance Ga is introduced through the opening of the first film.
After ion-implanting silicon into As11, heat treatment may be performed in an arsenic atmosphere, and then the second film may be deposited.

Next, as shown in FIG. 4(d), most of the second film is removed by anisotropic dry etching to expose the n-type active layer 14. At this time, a part of the second film 16 remains.Next, as shown in FIG. 4(e), a gate electrode 17 is formed covering the exposed n-type active layer 14, and then the first A field effect transistor can be manufactured by removing a portion of the film 12 and forming a source electrode 18 and a drain electrode 19.

In this example, the same effects as in the example shown in FIGS. It is clear that the gist of the present invention is not impaired even if iodine, selenium, etc. are used in place of Sn + Sj.

As explained above, according to the present invention, the end of the n-type active layer can be brought extremely close to the gate electrode, and the positional relationship can be determined independently, thereby achieving excellent performance with minimum parasitic resistance. In addition, it is possible to manufacture semiconductor devices with uniform characteristics.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of an example of a conventional semiconductor device, and Figure 2 (a
) to (e) are cross-sectional views shown in step 1 for fully explaining one embodiment of the first invention of the present invention, and FIG. 3(a), fbl
1(C) is a cross-sectional view showing another structure of the first olfaction formed in one step of the present invention, and FIGS.
FIG. 3 is a cross-sectional view shown in order of steps to explain an embodiment of the invention. 1... Semi-insulating or high resistance GaAs, 2
......n-type GaAs layer, 3...n-type G
aAs layer, 4...source electrode, 5...
Gate electrode, 6...Drain electrode, 11...
...High resistance GaAsJ 12...First film,
13... Silicon ion implantation layer, 14...
...n is active layer, 15...n type active layer, 16
...Second membrane. 17...Gate electrode, 18...Source electrode, 19...Drain electrode, 21...
・High resistance GaAs, 22... film containing impurities,
23...Membrane containing no impurities.

Claims (4)

[Claims] (1) A step of depositing a first film containing an impurity that has one conductivity in the semiconductor on a high-resistance semiconductor, and passing through the first film the impurity that has the same conductivity type as the first film. a step of ion-implanting an impurity, a step of removing a part of the first film, a heat treatment step, a step of depositing a second film, and removing the second film by anisotropic dry etching. exposing the semiconductor surface; providing one electrode covering the exposed semiconductor surface; and removing a portion of the first film to provide at least another electrode. A method for manufacturing a semiconductor device characterized by (2) A step of depositing a first film containing an impurity that becomes a conductive layer in the semiconductor on a high-resistance semiconductor, a step of removing a part of the first film, and a step of removing a part of the first film. A step of ion-implanting an impurity having the same conductivity type as the impurity having the same conductivity type as the above-mentioned impurity having a conductivity type, a step of heat treatment, a step of depositing a second film, and a step of depositing a second film by anisotropic dry etching. a step of removing the film to expose the semiconductor surface; a step of providing one electrode covering the exposed semiconductor surface; and a step of providing one electrode over the exposed semiconductor surface;
a step of removing a portion of the film to provide at least another electrode. (3) The step of removing part of the first film and the step of depositing the second film are the steps of removing part of the first film and the step of depositing the second film.
A method for manufacturing a semiconductor device according to claim 1 or claim 2, which comprises a step of depositing a film and a step of heat treatment. (4) - The first film containing an impurity that becomes a conductive type contains an impurity in a part of the film=fF+Claim No. (
A method for manufacturing a semiconductor device according to item 1) or item (2).