JPH0799751B2 - Method for manufacturing field effect compound semiconductor device - Google Patents
Method for manufacturing field effect compound semiconductor deviceInfo
- Publication number
- JPH0799751B2 JPH0799751B2 JP60031949A JP3194985A JPH0799751B2 JP H0799751 B2 JPH0799751 B2 JP H0799751B2 JP 60031949 A JP60031949 A JP 60031949A JP 3194985 A JP3194985 A JP 3194985A JP H0799751 B2 JPH0799751 B2 JP H0799751B2
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- layer
- semiconductor layer
- gate electrode
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 150000001875 compounds Chemical class 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title description 10
- 230000005669 field effect Effects 0.000 title description 9
- 238000000034 method Methods 0.000 title description 9
- 239000000758 substrate Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 14
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 8
- 239000000969 carrier Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電界効果型の化合物半導体装置の製造方法に係
るものであり、特にキャリアをホットに注入し、高速で
ゲート下を通り抜ける電界効果型化合物半導体装置（以
下ホットカソードFETという）の製造方法に関する。The present invention relates to a method for manufacturing a field effect type compound semiconductor device, and in particular, it is a field effect type device in which carriers are hot-injected and pass under a gate at high speed. The present invention relates to a method for manufacturing a compound semiconductor device (hereinafter referred to as hot cathode FET).
最近、ヘテロ接合を用いた化合物半導体装置に関する研
究が盛んになってきている。Recently, research on compound semiconductor devices using a heterojunction has been actively conducted.
例えば、AlGaAsとGaAsのヘテロ接合を用いてAlGaAsをホ
ットカソード（ソース）となし、高速でゲート下を電子
が通り抜ける横型のホットカソードFETが考えられる。
第３図にそのホットカソードFETの模式的断面構３図を
示す。１は半絶縁性（SI）GaAs基板、２はｎ−GaAs層、
３はソースまたはドレインのn+−AlGaAs層であり、n+−
AlGaAs層３に形成された溝10内のｎ−GaAs層２の表面に
WSi（ダンクステンシリサイド）のゲート電極５が形成
されている。６はWSiゲート電極５をマスクにしてイオ
ン注入でセルフアライン的に形成した高濃度のSi+の注
入領域であり、7,8はソース，ドレインの電極である。For example, a lateral hot cathode FET in which AlGaAs is used as a hot cathode (source) by using a heterojunction of AlGaAs and GaAs and electrons pass through under the gate at high speed is considered.
FIG. 3 shows a schematic cross-sectional structure diagram 3 of the hot cathode FET. 1 is a semi-insulating (SI) GaAs substrate, 2 is an n-GaAs layer,
3 is a n + -AlGaAs layer of the source and the drain, n + -
On the surface of the n-GaAs layer 2 in the groove 10 formed in the AlGaAs layer 3.
A gate electrode 5 of WSi (Dunksten silicide) is formed. Reference numeral 6 is a high-concentration Si + implantation region formed by ion implantation in a self-aligned manner by using the WSi gate electrode 5 as a mask, and 7 and 8 are source and drain electrodes.
ところが、第３図の構造の素子では、ソースのn+−AlGa
As層３から高いエネルギーで注入されたホットキャリア
がゲート電極５の下を高速に通り抜けても、ドレイン電
極８に注入される前に、ドレインのn+−AlGaAs層３とｎ
−GaAs層２との界面に形成されるバリアのため該界面部
で散乱されスピードが落ちてしまう結果、超高速な動作
が妨げられることがわかった。However, in the device having the structure shown in FIG. 3, the source n + -AlGa
Even if hot carriers injected with high energy from the As layer 3 pass through under the gate electrode 5 at high speed, they are n + -AlGaAs layers 3 and n of the drain before being injected into the drain electrode 8.
-It was found that the barrier formed at the interface with the GaAs layer 2 scatters at the interface to slow down the speed, and as a result, ultra-high speed operation is hindered.
本発明の目的は、ソースから注入されたホットキャリア
がゲート下を通り抜け、ドレインに達してもバリアによ
る速度低下がなく、超高速動作が可能な電界効果型化合
物半導体装置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a field effect compound semiconductor device capable of operating at an ultra-high speed, in which hot carriers injected from a source pass under a gate and reach the drain without speed reduction due to a barrier. It is in.
上記目的を達成するために本発明においては、以下の構
成を採用している。即ち、半絶縁性の化合物半導体基板
上に活性層となる第１導電型の第１化合物半導体層を形
成する工程と、 該活性層上に、該第１化合物半導体層より禁制帯幅が広
い第２化合物半導体層を形成する工程と、 該第２化合物半導体層を選択的にエッチングして前記活
性層を部分的に表出させ、表出した該活性層上にゲート
電極を形成する工程と、 該ゲート電極をマスクとして第１導電型の不純物をイオ
ン注入する工程と、 前記ゲート電極の一方の側の前記第２化合物半導体層上
にソース電極を形成するとともに、該ゲート電極をはさ
んで他方の側の前記第２化合物半導体層を選択的に除去
することにより露出した活性層上にドレイン電極を形成
する工程と を含むことを特徴とする電界効果型化合物半導体装置の
製造方法としての構成を有する。In order to achieve the above object, the present invention employs the following configurations. That is, a step of forming a first conductive type first compound semiconductor layer to be an active layer on a semi-insulating compound semiconductor substrate, and a step of forming a forbidden band width wider than the first compound semiconductor layer on the active layer. A step of forming a second compound semiconductor layer, a step of selectively etching the second compound semiconductor layer to partially expose the active layer, and forming a gate electrode on the exposed active layer, Ion-implanting a first conductivity type impurity using the gate electrode as a mask; forming a source electrode on the second compound semiconductor layer on one side of the gate electrode; And a step of forming a drain electrode on the exposed active layer by selectively removing the second compound semiconductor layer on the side of the field effect type compound semiconductor device. Have
上記のように、ドレイン電極を禁止帯幅が広い化合物半
導体層を介することなく、直接チャネルの活性層用化合
物半導体層に接続する工程により、ドレイン側のバリア
がない素子の製造方法が得られる。ソースの禁止帯幅が
広い半導体よりホットに注入されたキャリアは、高速に
ゲート電極下を走行し、ドレイン電極に高速のまま注入
される。したがって、本発明によれば超高速に動作する
電界効果型化合物半導体装置の製造方法が提供できる。As described above, the step of directly connecting the drain electrode to the compound semiconductor layer for the active layer of the channel without interposing the compound semiconductor layer having a wide band gap can provide a method for manufacturing an element having no drain-side barrier. The carriers injected hotter than the semiconductor having a wide band gap of the source travel under the gate electrode at a high speed and are injected into the drain electrode at a high speed. Therefore, according to the present invention, it is possible to provide a method for manufacturing a field effect compound semiconductor device which operates at an ultra-high speed.
第１図（Ａ）〜（Ｃ）は本発明の実施例としての電界効
果型化合物半導体装置の製造方法における製造工程を示
すものである。1 (A) to 1 (C) show manufacturing steps in a method for manufacturing a field effect compound semiconductor device as an embodiment of the present invention.
第１図（Ａ）参照 半絶縁性（SI）GaAs基板11の上にｎ−GaAs層12（50
0〜1000Åの膜厚,1〜５×1017cm-3のキャリア濃度）を
成長し、次に、n+−AlGaAs層13（2000Åの膜厚,2×1018
cm-3のキャリア濃度）を成長し、ゲート電極形成部をエ
ッチングで除去する。See Fig. 1 (A). On the semi-insulating (SI) GaAs substrate 11, the n-GaAs layer 12 (50
A thickness of 0 to 1000Å, a carrier concentration of 1 to 5 × 10 17 cm -3 ) and then n + -AlGaAs layer 13 (2000Å film thickness, 2 × 10 18
(cm −3 carrier concentration) is grown, and the gate electrode formation portion is removed by etching.
第１図（Ｂ）参照 ゲート電極のWSi（タングステンシリサイド）15を4
000Åの膜厚に形成する。See Fig. 1 (B).
Formed to a film thickness of 000Å.
Si+イオンを１×1013cm-2で170keVのエネルギーで
全面に照射する。その後、ランプアニールで950℃,5秒
間加熱して注入不純物を活性化する。このイオン注入に
よる高濃度のn+−GaAs領域16は、n+−AlGaAs層13の表面
から4000Åの深さになりイオン注入のピークはn+−AlGa
As層13とｎ−GaAs層12の界面付近となる。WSi15はイオ
ン注入を阻止し、その下にはSi+は注入されない。The entire surface is irradiated with Si + ions at an energy of 170 keV at 1 × 10 13 cm -2 . After that, the implanted impurities are activated by heating at 950 ° C. for 5 seconds by lamp annealing. N + -GaAs region 16 of high concentration by the ion implantation, the peak of the ion implantation made from the surface of the n + -AlGaAs layer 13 to a depth of 4000Å is n + -AlGa
It is near the interface between the As layer 13 and the n-GaAs layer 12. WSi15 blocks the ion implantation, below which Si + is not implanted.
なお、ゲート長は１μｍ以下となし、ホットに注入され
たキャリアが散乱を受けて遅くならないようにすると良
い。Note that the gate length is set to be 1 μm or less so that carriers injected hot cannot be scattered and delayed.
第１図（Ｃ）参照。See FIG. 1 (C).
ドレイン領域のn+−AlGaAs層13にn+−GaAs領域16が
表出するように溝19を形成し、該溝19内のn+−GaAs領域
の表面にドレイン電極18,例えばAuGe（厚さ200Å）/Au
（厚さ2800Å）を形成する。またソースのn+−AlGaAs層
13上にソース電極17,例えばAuGe（厚さ200Å）/Au（厚
さ2800Å）を形成する。A groove 19 is formed in the n + -AlGaAs layer 13 of the drain region so that the n + -GaAs region 16 is exposed, and the drain electrode 18, for example, AuGe (thickness) is formed on the surface of the n + -GaAs region in the groove 19. 200Å) / Au
Form (thickness 2800Å). Also, the source n + − AlGaAs layer
A source electrode 17, for example, AuGe (thickness 200 Å) / Au (thickness 2800 Å) is formed on 13.
第２図に、以上の工程により形成されたホットカソード
FETのバンド図を示す。従来（点線）のようにドレイン
側にバリアがないので、ホットに注入された電子がゲー
ト下を通り抜け、ドレインに達してもバリアによる速度
低下がない。通常のドリフト速度は１×1017cm/sである
のに対し、ホットエレクトロンの速度は８×107cm/sと
８倍も速いので、本発明によるデバイスは従来のFETよ
りスイッチング時間が短いデバイスとなる。Fig. 2 shows the hot cathode formed by the above process.
The band figure of FET is shown. Since there is no barrier on the drain side as in the conventional case (dotted line), there is no reduction in speed due to the barrier even when hot injected electrons pass under the gate and reach the drain. The normal drift velocity is 1 × 10 17 cm / s, while the hot electron velocity is 8 × 10 7 cm / s, which is 8 times faster, so the device according to the present invention has a shorter switching time than the conventional FET. Become a device.
ソースのAlGaAs13からホットにエレクトロンが注入され
るには第２図のバリア高さφｃが0.36eV以下，例えば0.
3eVとすれば良いが、AlGaAs（AlxGa1-xAs）のｘ値をｘ
＝0.3にすればφｃ＝0.25eV〜0.3eVとなり、ホットエレ
クトロンを注入することができる。To inject hot electrons from the source AlGaAs 13, the barrier height φc in FIG. 2 is 0.36 eV or less, for example, 0.
It may be 3 eV, but x value of AlGaAs (Al x Ga 1-x As) is x
= 0.3, φc = 0.25 eV to 0.3 eV, and hot electrons can be injected.
以上のごとく、本発明では、ホットカソードFETのドレ
インのバリアを無くすようにしたので、ソースから注入
されたホットキャリアがゲート下を通り抜け、ドレイン
に達してもバリアによる速度低下がなく、デバイスの超
高速動作が可能となる。As described above, in the present invention, the barrier of the drain of the hot cathode FET is eliminated, so that even if hot carriers injected from the source pass under the gate and reach the drain, there is no speed reduction due to the barrier, and the High-speed operation becomes possible.
第１図（Ａ）〜（Ｃ）は本発明の実施例としての電界効
果型化合物半導体装置の製造方法における製造工程を示
す模式的断面構造図 第２図は本発明の実施例により形成された電界効果型化
合物半導体装置の模式的バンド構造図 第３図は従来のホットカソードFETの模式的断面構造図 1,11……SI−GaAs基板 2,12……ｎ−GaAs層 3,13……n+−AlGaAs層 5,15……WSi（ゲート電極） 6,16……n+−GaAs領域（高濃度Si+の注入領域） 7,17……ソース電極 8,18……ドレイン電極 10,19……溝1 (A) to 1 (C) are schematic cross-sectional structural views showing manufacturing steps in a method for manufacturing a field effect compound semiconductor device as an embodiment of the present invention. FIG. 2 is formed by an embodiment of the present invention. Schematic band structure diagram of field effect compound semiconductor device Fig. 3 is a schematic cross-sectional structure diagram of a conventional hot cathode FET 1,11 …… SI-GaAs substrate 2,12 …… n-GaAs layer 3,13 …… n + −AlGaAs layer 5,15 …… WSi (gate electrode) 6,16 …… n + −GaAs region (high-concentration Si + implantation region) 7,17 …… Source electrode 8,18 …… Drain electrode 10, 19 ... Groove
Claims (1)
なる第１導電型の第１化合物半導体層を形成する工程
と、 該活性層上に、該第１化合物半導体層より禁制帯幅が広
い第２化合物半導体層を形成する工程と、 該第２化合物半導体層を選択的にエッチングして前記活
性層を部分的に表出させ、表出した該活性層上にゲート
電極を形成する工程と、 該ゲート電極をマスクとして第１導電型の不純物をイオ
ン注入する工程と、 前記ゲート電極の一方の側の前記第２化合物半導体層上
にソース電極を形成するとともに、該ゲート電極をはさ
んで他方の側の前記第２化合物半導体層を選択的に除去
することにより露出した活性層上にドレイン電極を形成
する工程と を含むことを特徴とする電界効果型化合物半導体装置の
製造方法。1. A step of forming a first conductivity type first compound semiconductor layer to be an active layer on a semi-insulating compound semiconductor substrate, and a forbidden band width from the first compound semiconductor layer on the active layer. Forming a second compound semiconductor layer having a wide area, and selectively etching the second compound semiconductor layer to partially expose the active layer, and forming a gate electrode on the exposed active layer A step of ion-implanting a first conductivity type impurity using the gate electrode as a mask, a source electrode is formed on the second compound semiconductor layer on one side of the gate electrode, and the gate electrode is removed. And a step of forming a drain electrode on the exposed active layer by selectively removing the second compound semiconductor layer on the other side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60031949A JPH0799751B2 (en) | 1985-02-20 | 1985-02-20 | Method for manufacturing field effect compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60031949A JPH0799751B2 (en) | 1985-02-20 | 1985-02-20 | Method for manufacturing field effect compound semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61191075A JPS61191075A (en) | 1986-08-25 |
| JPH0799751B2 true JPH0799751B2 (en) | 1995-10-25 |
Family
ID=12345208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60031949A Expired - Fee Related JPH0799751B2 (en) | 1985-02-20 | 1985-02-20 | Method for manufacturing field effect compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0799751B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181069A (en) * | 1983-03-30 | 1984-10-15 | Fujitsu Ltd | Semiconductor device |
-
1985
- 1985-02-20 JP JP60031949A patent/JPH0799751B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61191075A (en) | 1986-08-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0324782B2 (en) | ||
| EP0228624B1 (en) | field effect transistor | |
| US4771324A (en) | Heterojunction field effect device having an implanted region within a device channel | |
| JPH0799751B2 (en) | Method for manufacturing field effect compound semiconductor device | |
| JP3952383B2 (en) | Compound field effect semiconductor device | |
| JP4120899B2 (en) | Compound semiconductor field effect transistor and method of manufacturing the same | |
| JP3034546B2 (en) | Method for manufacturing field effect transistor | |
| KR910006698B1 (en) | Semiconductor device | |
| JP2541260B2 (en) | Manufacturing method of semiconductor device | |
| JPH0213927B2 (en) | ||
| JP2708492B2 (en) | Method for manufacturing semiconductor device | |
| JP3653652B2 (en) | Semiconductor device | |
| JP2503594B2 (en) | Semiconductor integrated device and manufacturing method thereof | |
| JPH0810701B2 (en) | Method for manufacturing junction field effect transistor | |
| JP2514948B2 (en) | Method for manufacturing semiconductor device | |
| JP3109097B2 (en) | Method for manufacturing field effect transistor and etching method | |
| JPS63115384A (en) | Manufacture of semiconductor device | |
| JP3113689B2 (en) | Semiconductor device | |
| JP2616032B2 (en) | Method for manufacturing field effect transistor | |
| JPS60234374A (en) | Manufacture of semiconductor device | |
| JPH0332233B2 (en) | ||
| JP2508173B2 (en) | Method for manufacturing semiconductor device | |
| JP3112075B2 (en) | Field effect transistor and method of manufacturing the same | |
| JPH0446460B2 (en) | ||
| JPS63240076A (en) | Schottky-gate field-effect transistor and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |