JP2508173B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an ultra-high frequency ultra-high speed semiconductor device using a compound semiconductor.

[Conventional technology]

The selectively-doped structure composed of a heterojunction of n-AlGaAs and undoped GaAs travels in GaAs with few electron impurities, and therefore has high mobility and high speed, and is used for low noise devices and high speed devices.

FIG. 2 is a sectional view of an example of a conventional field effect transistor.

Undoped GaAs layer 2, n ⁺ -AlGa on semi-insulating GaAs substrate 1
An As layer 3 is provided, and a gate electrode 11 and source / drain ohmic electrodes 12 and 13 are provided. Electrons are layers 2 and 3
It travels from the source to the drain on the side of the GaAs layer 2 at the heterojunction interface and undergoes modulation by the gate electrode 11 to operate as a transistor. In this transistor, it is extremely important to reduce the source resistance in order to improve low noise and high speed.

[Problems to be Solved by the Invention]

Conventionally, the source and drain electrodes 12 and 13 are formed by vapor-depositing Au-Ge or the like on the n ⁺ -AlGaAs layer, heat-treating it, and alloying it with the n ⁺ -AlGaAs layer 3 and the undoped GaAs layer 2. It was However, in this method, since the electrode is directly formed on the undoped GaAs layer 2, the contact resistance is not sufficiently small and the interface between the alloy layer and the crystal layer has a rough surface. . To improve this, there is a method of selectively re-growing n ⁺ -GaAs after etching the crystal layers of the source and drain electrodes 12 and 13, but the quality of the re-growing interface may be poor. .

An object of the present invention is to provide a method for manufacturing a semiconductor device having a small source resistance without deteriorating the quality of the interface between the alloy layer and the crystal layer in the electrode formation portion.

[Means for solving the problem]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a step on a high resistance substrate and a step of forming a molecular beam of a second element in an atmosphere of a first element constituting a compound semiconductor with respect to a main surface of the substrate. A step of irradiating from an oblique direction to form a first semiconductor layer covering the step and the main surface; and a molecular beam of the second element and a molecular beam of a dopant from an oblique direction with respect to the main surface of the substrate. While irradiating, a molecular beam of a third element, which is one component of the third semiconductor layer having an electron affinity smaller than that of the first semiconductor layer, is irradiated from a direction that does not reach the side surface of the step, and the side surface of the step is exposed. Forming a second doped semiconductor layer and forming a third semiconductor layer on the flat surface of the main surface.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1A to 1E are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

As shown in FIG. 1A, steps are formed in the semi-insulating GaAs substrate 1.

Next, as shown in FIG. 1 (b), a molecular beam epitaxy method is used to irradiate a Ga beam from an oblique direction with respect to the step in an As atmosphere to deposit an undoped GaAs layer 2 covering the step.

Next, as shown in FIG. 1 (c), similarly using the molecular beam epitaxy method, a Ga beam and a Si beam serving as a dopant are irradiated obliquely to the step in an As atmosphere, and at the same time, Irradiate the Al beam from a direction that does not hit the side surface of the step, and n ⁺ -GaAS layer 4 is applied to the side surface of the step.
An n ⁺ -AlGaAs layer 3 is deposited on the flat surface.

Next, as shown in FIG. 1 (d), the Al beam is cut off, and the Ga beam and the Si beam are irradiated in an As atmosphere from an oblique direction with respect to the step to form an n ⁺ -GaAs layer as a cap layer. 5 is deposited.

Next, as shown in FIG. 1 (e), a flat surface of n ⁺ -GaAs is formed.
Selectively etching layer 5 to expose n ⁺ -AlGaAs layer 3,
The gate electrode 11 is formed there. Further, the source and drain electrodes 12 and 13 are formed on the n ⁺ -GaAs layer 5 to complete the field effect transistor.

As shown in Fig. 1 (c), n ⁺ -
The GaAs layer 4 grows, and this serves as an n ⁺ contact layer. This layer 4 introduced As after being evacuated
Since it is formed by continuous epitaxy in an As atmosphere, the interface has good quality and low contact resistance and source resistance.

In the above embodiment, steps are formed only on the source side,
Although the case where the n ⁺ contact layer is formed has been described, it is also possible to form the n ⁺ contact layer on the drain side.

〔The invention's effect〕

As described above, the present invention, which is to act as a n ⁺ contact layer to form a n ⁺ -GaAs layer on the side surface of the step forms a step, the gate electrode is n ⁺ AlGaAs
Since the source and drain electrodes are respectively formed in the n ⁺ -GaAs layer in the layer, there is an effect that a source resistance is small and a low-noise and high-speed operation semiconductor device can be manufactured.

[Brief description of drawings]

1 (a) to 1 (e) are sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional field effect transistor. 1 ... Semi-insulating GaAs substrate, 2 ... Undoped GaAs layer, 3 ... n ⁺
-AlGaAs layer, 4,5 ... n ⁺ -GaAs layer, 11 ... Gate electrode, 12 ...
Source electrode, 13 ... Drain electrode.

Claims (1)

(57) [Claims] 1. A step of forming a step on a high resistance substrate,
In the atmosphere of the first element forming the compound semiconductor,
Irradiating the main surface of the substrate from a diagonal direction with respect to the main surface of the substrate to form a first semiconductor layer covering the step and the main surface, and the molecular beam of the second element and the molecules of the dopant. And a molecular beam of a third element, which is a component of a third semiconductor layer having an electron affinity smaller than that of the first semiconductor layer, is applied to the main surface of the substrate in an oblique direction. Irradiation is performed from a direction in which the side surface becomes a shadow and does not reach the side surface, and a second semiconductor layer having the same composition as the first semiconductor doped with the dopant is formed on the side surface of the step to form a flat surface on the main surface. And a step of forming a third semiconductor layer.