JPH01202872A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device, which has small source resistance and low noises is operated at high speed, by forming an n<+>-GaAs layer onto the side face of a step and working the n<+>-GaAs layer as an n<+> contact layer. CONSTITUTION:A step is implanted with Ga beams from the oblique direction in an As atmosphere, an undoped GaAs layer 2 coating the step is deposited, Ga beams and Si beams are applied similarly while Al beams are applied, and an n<+>-GaAs layer 4 is deposited onto the side face of the step and an n<+>- AlGaAs layer 3 onto a flat surface. Al beams are interrupted, the step is implanted with Ga beams and Si beams from the oblique direction in the As atmosphere, and an n<+>-GaAs layer 5 as a cap layer is deposited. The n<+>-GaAs layer 5 on a flat surface is etched selectively to expose the n<+>-AlGaAs layer 3, and a gate electrode 11 is formed onto the exposed layer 3. Consequently, the n<+>-GaAs layer 4 is grown on the side face of the step, and the layer 4 functions as an n<+> contact layer. Accordingly, the interface is improved, contact resistance is lowered, and a source resistance is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an ultrahigh frequency and ultrahigh speed semiconductor device using a compound semiconductor.

[Conventional technology]

fi'-"AI! The selectively doped structure consisting of a heterojunction of GaAS and undoped GaAs has GaAs with few electronic impurities.
Because it travels through As, it has high mobility and high speed, and is used in low-noise and high-speed devices.

FIG. 2 is a cross-sectional view of an example of a conventional field effect transistor.

An undoped GaAs layer 2 on a semi-insulating GaAs substrate 1.
n”-AeGaAs layer 3 is provided, and the gate electrode 11
And source and drain ohmic electrodes 12 and 13 are provided. The electrons are in GaAs at the heterojunction interface between layers 2 and 3.
It runs along the layer 2 side from the source toward the train, and is modulated by the gate electrode 11 to perform a transistor operation. Now, in order to improve low noise and high speed in this transistor, it is extremely important to reduce the source resistance.

[Problem to be solved by the invention]

Conventionally, the source and drain electrodes 12.13 are made of Au-
Ge, etc. are deposited on the n''-AI!GaAs layer and heat treated to form the n''-AI! GaAs layer 3 and undoped G
It was formed by alloying with the aAs layer 2. However, in this method, since the electrode is directly connected to the undoped GaAs layer 2, the contact resistance is not small enough and the interface between the alloy layer and the crystal layer becomes a highly uneven surface. . One way to improve this is to selectively re-grow n''-GaAs after etching the crystal layer in the source and drain electrodes 12.1'3, but there is a risk that the quality of the re-grown interface will be poor. There is.

An object of the present invention is to provide a method for manufacturing a semiconductor device with low source resistance without impairing the quality of the interface between the alloy layer and the crystal layer in the electrode forming portion.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a step on a high-resistance substrate, and applying a molecular beam of a second element to the main surface of the substrate in an atmosphere of a first element constituting a compound semiconductor. forming a first semiconductor layer covering the step and the main surface by irradiating from an oblique direction; and irradiating the second element molecular beam and the dopant molecular beam from an oblique direction with respect to the main surface of the substrate. while irradiating the first
A molecular beam of a third element, which is a component of a third semiconductor layer having a lower electron affinity than that of the semiconductor layer, is irradiated from a direction that does not touch the side surface of the step, so that the side surface of the step is doped with a second semiconductor layer. and forming a third semiconductor layer on the flat main surface.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1E are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.

As shown in FIG. 1(a), steps are formed on a semi-insulating GaAs substrate 1. As shown in FIG.

Next, as shown in Fig. 1(b), molecular beam shrimp taxi
Using the method, a Ga beam is irradiated obliquely to the step in an As atmosphere to form an undoped Ga beam covering the step.
Deposit As layer 2.

Next, as shown in FIG. 1(C), using the same molecular beam epitaxy method, a Ga beam and a Si beam serving as a dopant are irradiated obliquely to the step in an As atmosphere. The Ae beam is irradiated from a direction that does not touch the side of the step, and the side of the step is exposed to n”-G.
An aAS layer 4 is deposited, and a GaAs layer 3 is deposited on the flat surface.

Next, as shown in FIG. 1(d), AI! The beam is blocked, and the step is irradiated with a Ga beam and a Si beam from an oblique direction in an As atmosphere to form an n'' cap layer.
- deposit a GaAs layer 5;

Next, as shown in FIG. 1(e), the n”-Ga on the flat surface is
The As layer 5 is selectively etched to expose the n+-Aj'GaAs layer 3, and a gate electrode 11 is formed thereon. Further, source and drain electrodes 12 and 13 are formed on the n''-GaAs layer 5 to complete the field effect transistor.

As shown in Figure 1(c), there is an n”-
A GaAs layer 4 is grown, which will act as an n+32275 layer. Since this layer 4 is formed by continuous epitaxy in an As atmosphere into which As is introduced after being evacuated, the interface is of good quality and low selective resistance and source resistance are realized.

In the above embodiment, steps are formed only on the source side, and n
Although the case where the +32275 layer is formed has been described, it is also possible to form it on the drain side.

〔Effect of the invention〕

As explained above, the present invention forms a step, forms an n''-GaAs layer on the side surface of the step, and forms an n''-GaAs layer on the side surface of the step.
The gate electrode is formed on the n'' AffGaAs layer, and the source and drain electrodes are formed on the n''-GaAS layer, so that a semiconductor device with low source resistance, low noise, and high speed operation can be obtained. It has the effect that it can be manufactured.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view of an example of a conventional field effect transistor. 1... Semi-insulating GaAs substrate, 2... Undoped G
aAs layer, 3-n”-AI!GaAs layer, 4.5...
n''-GaAs layer, 11... gate electrode, 12...
Source electrode, 13... drain electrode.

Claims (1)

[Claims] forming a step on a high-resistance substrate; and irradiating a molecular beam of a second element from an oblique direction with respect to the main surface of the substrate in an atmosphere of a first element constituting a compound semiconductor to form a step on a high-resistance substrate. a step of forming a first semiconductor layer covering a surface of the substrate; and irradiating a molecular beam of the second element and a molecular beam of a dopant from an oblique direction with respect to the principal surface of the substrate; Forming a doped second semiconductor layer on the side surface of the step by irradiating a molecular beam of a third element, which is a component of a third semiconductor layer having a lower electron affinity, from a direction that does not touch the side surface of the step. and forming a third semiconductor layer on the flat main surface.