JPS62226669A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce source resistance largely, and to obtain an FET having high performance by applying a stopper layer and an ohmic metallic layer to dug-in source-drain electrode sections, conducting alloying, diffusing the ohmic metal in the transverse direction and alloying the ohmic metal. CONSTITUTION:A wafer in which semiconductor layers 5, 3 are laminated continuously on a high resistance substrata 6 is used, and a gate l in gate length of d2 is formed. A mask 2 in length d1 is shaped onto the gate, source-drain regions are etched, employing the mask as a mask, and sections up to the semiconductor layer 5 are exposed. A metal, which has no ohmic property with the layer 5 and is not alloyed, is applied and employed as a stopper layer 8, and a metal 7 having ohmic properties with the layer 5 is applied. The mask 2 is removed, and the ohmic metal is alloyed through alloying and ohmic properties with the layer 5 are given. A dopant functioning as an impurity to the layer 5 in the metal 7 is diffused in the transverse direction (the gate direction) on the alloying, and shaped, intruding transversely only by diffusion length of d3. Accordingly, an effective interval between a source and the gate is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a field effect transistor, and particularly to a method for manufacturing a high performance field effect transistor with small parasitic resistance and small dimensions.

(Prior art) As a conventional method for manufacturing field effect transistors, GaA
An example of a short electrode with the same structure using a two-dimensional electron gas at the heterointerface of S and AlGaAs will be explained.

The structure of this field effect transistor is, as shown in the cross-sectional structural diagram of FIG. A type-doped Alo, 3Gao7AS layer is used to combine GaAs in the first semiconductor and A in the second semiconductor.
A two-dimensional electron gas 4 is formed on the GaAs side due to the difference in electron affinity with lGaAs. Then, the source and drain electrodes are formed by depositing a metal containing AuGe/Ni from the surface of the second semiconductor and alloying it at a temperature of 420°C to 450°C. The layer 3 and the first semiconductor layer 5 having a low donor impurity density are directly alloyed to form a two-dimensional electron layer.

(Problems to be Solved by the Invention) In the field effect transistor manufactured as described above, an important element for obtaining high performance characteristics is to reduce the source resistance. One of them is
The distance between the source and gate and the distance between the gate and drain may be shortened, but in conventional manufacturing methods, the distance between the source and gate is reduced to 0.
．． The limit is about 5 pm, and if you try to get it closer than that, the source/drain metal and gate metal will react during alloying and come into contact. Furthermore, if the amount of ohmic metal is increased in order to lower the source resistance, the alloy layer becomes deeper and the drain conductance increases.

(Means for Solving the Problems) The present invention provides a method for manufacturing a field effect transistor, which includes:
A field effect transistor characterized in that the source and drain electrode parts are dug, a stopper layer and an ohmic metal layer are deposited on the parts, and an alloy is formed by diffusing the ohmic metal laterally to form an alloy. This is the manufacturing method.

(Function) The structure and effects of the present invention will be described below with reference to the cross-sectional groove structures shown in FIGS. 1(a) to 1(d).

First, as shown in FIG. 1(a), a wafer in which a first semiconductor layer 5 and a second semiconductor layer 3 are successively stacked on a high-resistance substrate q by, for example, the MBE method is used, and a gate with a gate length d2 is formed. form 2. Next, as shown in FIG. 1(b), a mask 1 having a length of do is formed on the gate, and using this as a mask, the source and drain regions are etched to expose the first semiconductor layer 5. . Next, as shown in FIG. 1(e), after depositing a thin layer (stopper layer) 8 of a metal that has no ohmic properties and does not form an alloy with the first semiconductor layer 5, A certain metal 7 is deposited. Next, after removing the mask 1, alloying is performed to form an alloy of ohmic metals to obtain ohmic properties with the first semiconductor layer 5. At this time, during alloying, the dopant acting as an impurity diffuses into the first semiconductor layer 5 in the ohmic metal 7 in the lateral direction (gate direction), and if this diffusion length is d3, the alloy layer is As shown in (d), it is formed by extending laterally by a thickness d3. Therefore, the effective source
The gate interval is shortened to (d, -d2)12-d3. Therefore, source resistance is reduced. Further, there is a stopper layer 8 under the ohmic metal 7 that does not act as an impurity for the first semiconductor layer 5, and does not react with the first semiconductor layer 5 even if alloying is performed. Even if the amount of is increased, the diffusion of the dopant in the depth direction is suppressed, and the drain conductance can be reduced.

(Example) Examples of the present invention will be described in detail below.

As shown in FIG. 1(a), a P--Ga layer with a carrier density of about I x 10110 l4 and a thickness of 0.8 pm was formed by MBE on a semi-insulating GaAs substrate as a first semiconductor layer.
As a second semiconductor layer, an As layer is grown and a donor density of 2X1018 cm' and a thickness of 100 n-AI is grown.
. , 3Ga, 7As layer, thickness 20OA, n-AlxGa with the molar ratio of AI and Ga changing from 0.3 to 0,
Using a wafer in which a -xAs layer and a 200-thick n-GaAs layer were sequentially grown, a gate length of 0 with a thickness of aoooA was used.
．． Form gate 2 of 5 pm AI. Next, Figure 1 (
As shown in b), a mask 1 with a length of 1.5 pm is formed above the gate, and using this as a mask, the source and drain electrode portions are etched to a depth of 700 mm. After that, 20 W as a stopper layer and 200 W as an ohmic metal layer.
0 AuGe and 600 Ni are sequentially deposited, and the mask 1 is lifted off so that the ohmic metal is present only in the openings of the source and drain electrodes. Figure 1(e)
After that, alloying is performed at 450°C for 2 minutes to alloy the ohmic metal, form source/drain electrodes, and FET.
was produced. At this time, about 0.111 m of Ge is diffused in the gate direction (lateral direction) and alloyed, so the effective distance between the source and gate is 0.511 m to 0.1 m. It is narrow as Qm. In addition, in the depth direction of the ohmic electrode, there is a stopper layer of W, which does not have ohmic properties with GaAs, so that the diffusion of Ge is suppressed. As a result, the source resistance was significantly reduced, the effective gate length was also shortened, and mutual conductance was improved. Furthermore, the stopper layer reduces the drain conductance, and even if the gate length is shortened, the short channel effect is reduced, making it possible to fabricate a high-performance field-effect transistor with fine dimensions. Here, as an example,
W as a stopper, AuGe as an ohmic metal
Although Ni is used, a metal that has Schottky properties with GaAs and does not react even when alloyed is used for the stopper, or other ohmic metals may also be used.

(Effects of the Invention) As detailed above, according to the method of the present invention, the source/drain electrode portions are dug, a stopper layer and an ohmic metal layer are deposited on the portions, and alloying is performed. By diffusing and alloying the ohmic metal in the direction, the distance between the source and gate and between the gate and drain can be shortened, so the source resistance can be significantly reduced. Further, the depth direction of the alloy layer can be controlled by the stopper layer, and a high-performance field transistor with reduced drain conductance can be realized.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are cross-sectional views of the device, showing the T, W construction and steps for explaining the manufacturing method according to the present invention. FIG. 2 is a cross-sectional structural diagram of a conventional short electrode FET with the same structure. Here 1. Mask 2. Gate 3. Second semiconductor layer 4. Two-dimensional electron gas 5. First semiconductor layer 6, high resistance substrate 7
．． One layer of ohmic metal 8 stoppers 9. Alloy layer of ohmic metal. 7〈 Agent 1

Claims (1)

[Claims] A method for manufacturing a field effect transistor, characterized in that a source/drain electrode part is dug, a stopper layer and an ohmic metal layer are deposited on the part, and alloying is performed in the lateral direction to form an alloy. Method of manufacturing effect transistors.