JPS6394688A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To decrease a source resistance and to improve electrical characteristics of an element, by performing ion implantation with a gate electrode used as a mask so that a n-type region is formed and forming a high- concentration n-type GaAs layer ranging from the part below an ohmic electrode to the vicinity of the gate electrode. CONSTITUTION:A n-type AlGaAs layer 3 is formed on a GaAs layer 2 which is formed on a semi-insulating GaAs substrate 1. Next, a gate electrode 4 comprising a high-melting-point metallic layer is formed on this n-type AlGaAs layer 3. while the gate electrode 4 is used as a mask, an element 5 acting as a donor in the GaAs layer 2 and the AlGaAs layer 3 is ion-implanted, and annealing processing is performed to form a channel region under the gate electrode 4 and to form n-type regions 6 on both sides of this channel region. Next, an insulating film 7 coating the n-type AlGaAs layer 3 and the gate electrode 4 is etched to remain on the sides of the gate electrode 4. While the gate electrode 4 and the insulating film 7 are used as masks, epitaxial growth of a high-concentration n-type GaAs layer 8 is selectively performed on the n-type AlGaAs layer 3. Thus, a field-effect transistor having a hetero junction is formed, moreover, by sticking ohmic electrodes 9 on the surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and particularly to a method for manufacturing a field effect transistor having a heterojunction.

[Conventional technology]

Conventionally, in a semi-insulating semiconductor substrate using gallium arsenide, an undoped gallium arsenide layer (hereinafter referred to as a GaAs layer) and an n-type aluminum gallium arsenide layer (hereinafter referred to as an A
Since the heterostructure formed by the eGaAs layer has extremely high electron mobility at low temperatures, field effect transistors and the like using this heterostructure are attracting attention as high-speed driving elements.

For example, a conventional method for manufacturing a field effect transistor having a heterostructure will be described with reference to FIGS. 2(a) to 2(d).

211(a) to 211(d) are cross-sectional views of the field effect transistor shown in the order of steps.

First, as shown in FIG. 2(a), an undoped GaAs layer 12 with a carrier density of 1×10 14 Cal-3 and a thickness of 1 μm is formed on a semi-insulating GaAs substrate 11. 2 silicon as a donor
X1018C1l' doped thickness 250 n
A type A & GaAs layer 13 is formed. Next, this n-type Af
On top of the GaAs layer 13 is deposited a gate electrode 14 consisting of a layer of high melting point metal with a thickness of 5,000 thick.

Next, as shown in FIG. 2(b), an insulating film 17 made of silicon oxide or the like having a thickness of 0.1 μm is coated on the n-type Ae layer 13 and the gate electrode 14, and then the reactive The insulating film 17 is etched by ion etching so that it remains only on the side surfaces of the gate electrode 14.

Next, as shown in FIG. 2(c), using the gate electrode 14 and the insulating film 17 as a mask, a film is deposited on the n-type AeGaAs layer 13 to a thickness of 100 mm and a carrier density of lXl0''C11-3.
A high concentration n-type GaAs layer 18 is selectively grown epitaxially.

Furthermore, as shown in FIG. 2(d), high concentration n-type GaAs
An ohmic electrode (e.g. AuG) is placed in place on layer 18.
e/N1) 19 is formed and completed as a field effect transistor.

[Problem that the invention seeks to solve]

In manufacturing a field effect transistor having a hetero-IR structure formed by the above-mentioned n-type Aj'GaAs layer and undoped GaAs layer, it is important to reduce the source resistance in order to improve the electrical characteristics.

According to this conventional manufacturing method, a high concentration n-type GaAs layer can be formed near the gate electrode, which has the effect of reducing the source resistance. Since no concentration n-type GaAs layer is provided, the source resistance cannot be made sufficiently small, which has the drawback of limiting the electrical characteristics of the device.

An object of the present invention is to provide a method for manufacturing a field effect transistor in which the above-mentioned source resistance is reduced and the electrical characteristics of the device are improved.

[Means for solving problems]

The method for manufacturing a field effect transistor of the present invention includes the steps of providing an undoped GaAs layer on a semi-insulating GaAs substrate, and forming an n-type Al! layer on the undoped GaAs layer. A step of providing a GaAs layer and the n-type Al! A step of forming a patterned high melting point metal layer, a high melting point metal compound layer, or a silicide layer thereof on the GaAs layer as a gate electrode, and a step of forming the metal layer or the compound layer formed as the gate electrode, or Using these silicide layers as a mask, the GaAs layer and the Aff
A step of ion-implanting an element as a donor into the GaAs layer, a step of activating the implanted ions by annealing, a step of covering an insulating film, and etching the insulating film by an anisotropic dry etching method. a step of leaving the insulating film only on the side surfaces of the gate electrode; and a step of leaving the insulating film only on the side surfaces of the gate electrode, and forming a high concentration n-type GaAs layer only on the n-type AeGaAs layer.
The method includes a step of selectively epitaxially growing a layer, and a step of forming an ohmic electrode at a predetermined position on the high concentration n-type Ga, As layer.

In particular, in the present invention, ion implantation is performed using the gate electrode of the field effect transistor as a mask to provide an n-type region, and a highly concentrated n-type GaAs layer is provided from below the ohmic electrode to near the gate electrode. This is an important point, because the channel region and the n-type region are adjacent to each other, and the ohmic electrode is formed on the GaAs layer, resulting in a field effect transistor with low source resistance and good electrical characteristics. It is formed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views of a field effect transistor shown in order of steps for explaining an embodiment of the present invention.

As shown in FIG. 1(a), an undoped GaAs layer 2 with a carrier density of lXl0"C1l' and a thickness of 1 μm is formed on a semi-insulating GaAs substrate 1, and a silicon donor is deposited 2× on this GaAs layer 2. 1018 cr-' doped 9 to form a 250 n-type A!Q a As layer 3
Then, on top of this n-type AfGaAs layer 3, a layer with a thickness of 5
The gate electrode 4 is formed of a high melting point metal layer such as tungsten.

Next, as shown in FIG. 1(b), using the gate electrode 4 as a mask, an element 5 (for example, silicon,
Salefa etc.) are ion-implanted. Next, if necessary, an annealing treatment is performed at this stage to form the n-type region 6. As a result, a channel region is formed under the gate electrode 4, and n-type regions 6 are formed on both sides of the channel region. Note that the annealing treatment at this stage is not necessarily necessary, and may be performed in a step to be described later.

Next, as shown in FIG. 1(c), the n-type AeGaAs layer 3 and the gate electrode 4 are covered with an insulating film 7 such as silicon oxide having a thickness of 0.1 μm.

Next, as shown in FIG. 1(d), this insulating film 7 is etched, for example, by a reactive ion etching method using carbon tetrafluoride gas CF4, leaving the insulating film 7 only on the side surfaces of the gate electrode 4. .

Next, as shown in FIG. 1(e), with the gate electrode 4 and the insulating film 7 as a mask, a high concentration film with a thickness of 100 nm and a carrier density of about 1×1 OI9c111-1 is deposited on the n-type AeGaAs layer 3. The n-type GaAs layer 8 is selectively epitaxially grown by low pressure MOCVD (metal organic chemical vapor deposition) or the like.

Note that the alnealing process may be performed after the step of forming the insulating film 7 shown in FIG. 1(c) or the step of forming the high concentration n-type GaAs layer 8 shown in FIG. 1(e). Before forming the high concentration n-type GaAs layer 8, hydrogen arsenide (AsH)
3) You can also do it inside.

Furthermore, as shown in FIG. 1(f), high concentration n-type Q a
An ohmic electrode 9 formed by adding Ni to an alloy layer of Au and Ge is applied to the As layer to form a field effect transistor having a heterojunction.

The field effect transistor thus formed has a source resistance as small as 0.15 ohms, a mutual conductance as high as 400 m5/dragon, and good electrical characteristics.

Further, in the above embodiment, a high melting point metal layer is used as the gate electrode, but the same effect can be obtained by using a high melting point metal compound layer, a high melting point metal silicide layer, or a high melting point metal compound silicide layer. The present invention can be implemented in the following manner.

〔Effect of the invention〕

As explained above, in the method for manufacturing a field effect I-transistor of the present invention, the channel region and the n-type region are adjacent to each other and the ohmic electrode is formed on the GaAs layer, so the source resistance is small and the mutual conductance is low. There is an advantage that a method for manufacturing a field effect transistor having good characteristics such as a large value can be obtained.

[Brief explanation of the drawing]

Figures 1 (a) to (f) are cross-sectional views of a field effect transistor shown in the order of steps to explain an embodiment of the present invention, and Figures 2 (a) to (d) illustrate a conventional manufacturing method. FIG. 3 is a cross-sectional view of a field effect transistor shown in the order of steps for manufacturing. 1... Semi-insulating GaAs substrate, 2... Undoped G
aAs layer, 3-n type AeGaAs layer, 4... Day 1~
electrode, 5... implanted ion, 6... n-type region, 7...
・Insulating film, 8... High concentration n-type GaAs layer, 9... Ohmic conduction Figure 1

Claims (1)

[Claims] providing an undoped gallium arsenide layer on a semi-insulating gallium arsenide substrate; providing an n-type aluminum gallium arsenide layer on the undoped gallium arsenide layer; and patterning the n-type aluminum gallium arsenide layer as a gate electrode. forming at least one of a high melting point metal layer, a high melting point metal compound layer, and a silicide layer of the metal layer and the compound layer, and using the layer formed as the gate electrode as a mask, the gallium arsenide implanting an element as a donor to the aluminum gallium arsenide layer and the aluminum gallium arsenide layer, activating the implanted ions by an annealing process, coating an insulating film, and anisotropically forming the insulating film. etching using a dry etching method to leave the insulating film only on the side surfaces of the gate electrode;
selectively epitaxially growing a high concentration n-type gallium arsenide layer only on the gallium arsenide layer;
forming an ohmic electrode at a predetermined position on a gallium arsenide layer.