JPS6010785A - Field effect transistor and manufacture thereof - Google Patents
Field effect transistor and manufacture thereofInfo
- Publication number
- JPS6010785A JPS6010785A JP11907483A JP11907483A JPS6010785A JP S6010785 A JPS6010785 A JP S6010785A JP 11907483 A JP11907483 A JP 11907483A JP 11907483 A JP11907483 A JP 11907483A JP S6010785 A JPS6010785 A JP S6010785A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- field effect
- effect transistor
- gate electrode
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010931 gold Substances 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract 4
- 239000007789 gas Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/432—Heterojunction gate for field effect devices
Abstract
Description
【発明の詳細な説明】
（１） 発明の技術分野
本発明は電界効果トランジスタ及びその製造方法に係り
、特に同一導電型のへテロ接合を有し２次元ガスを利用
して高速動作させる電界効果トランジスタ及びその製造
方法に関する。Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a field effect transistor and a method for manufacturing the same, and particularly to a field effect transistor having heterojunctions of the same conductivity type and operating at high speed using a two-dimensional gas. The present invention relates to a transistor and its manufacturing method.
（２） 技術の背景
■−■族化合物半導体の１つであるガリウム・ヒ素（以
下Ｇ ａ Ａ Ｓと記す）はシリコンＳｔに比べて電子
移動度が約６倍あり、高周波素子や高速論理素子の材料
として注目を集めている。(2) Technical background Gallium arsenide (hereinafter referred to as GaAS), which is one of the ■-■ group compound semiconductors, has an electron mobility approximately six times that of silicon St, and is used in high-frequency devices and high-speed logic devices. It is attracting attention as a material for
このＧａＡｓを用いた電界効果トランジスタ（以下ＦＥ
Ｔと記す）としてはショットキーバリアＦＥＴや接合Ｆ
ＥＴなどが提案されているが。Field effect transistor (hereinafter referred to as FE) using this GaAs
(denoted as T) is a Schottky barrier FET or a junction FET.
ET etc. have been proposed.
その中でも特にヘテロ接合を用いたＧ ａ Ａ ｓ Ｆ
ＥＴはノンドープＧ ａ Ａ Ｓ層の界面に形成され
る２次元電子ガスによって高速動作を達成している。Among them, especially G a A s F using heterojunction
ET achieves high-speed operation by a two-dimensional electron gas formed at the interface of the non-doped GaAs layer.
（３） 従来技術と問題点
このヘテロ接合を有したＧ ａ Ａ ｓ Ｆ Ｅ Ｔの
構成を従来例を用いて簡単に説明する。(3) Prior Art and Problems The structure of the GaAsFET having this heterojunction will be briefly explained using a conventional example.
先ず、半絶縁性のＧａＡｓ基板上にノンドープＧａＡｓ
１ｉを形成し、その上にアルミニウムＡβが３０％、ガ
リウムＧａが７０％の割合で化合したｎ形のアルミニウ
ム・ガリウムヒ素Ａｊ！ＧａＡＳ層（以下、ｎ形Ａｊ！
（０，３）Ｇａ （０，７）Ａｓ層という形式で記す
ことにする）を形成する。First, undoped GaAs was deposited on a semi-insulating GaAs substrate.
1i, and n-type aluminum-gallium-arsenide Aj! on which 30% aluminum Aβ and 70% gallium Ga are combined. GaAS layer (hereinafter referred to as n-type Aj!
(0,3)Ga(0,7)As layer) is formed.
このｎ形ＡＡ （０，３） Ｇａ （０，７） Ａｓ層
につづいてアルミニウムＡ！の割合を減少させたｎ形Ａ
ｌｘ１Ｇａ （１−ｘ）Ａｓ層を形成し、最後にアルミ
ニウムＡＡを含まないｎ形ＧａＡｓ層を形成する。そし
てアイソレーションのためにメサ形成を行なった後にソ
ース及びドレイン電極を形成し１合金化処理によってオ
ーミック接触をとる。Following this n-type AA (0,3) Ga (0,7) As layer, aluminum A! n-type A with a reduced proportion of
A lx1Ga (1-x)As layer is formed, and finally an n-type GaAs layer containing no aluminum AA is formed. After forming a mesa for isolation, source and drain electrodes are formed and ohmic contact is established by 1-alloying treatment.
そして最後にリフトオフ法によって、ゲート金属を真空
中でｎ形ＱａＡｓ層表面に被着させ、ゲート電極を形成
する。このようにしてヘテロ接合を有するＧａＡｓＦＥ
Ｔが製造される。Finally, a gate metal is deposited on the surface of the n-type QaAs layer in vacuum by a lift-off method to form a gate electrode. In this way, GaAsFE with a heterojunction
T is manufactured.
しかしながらＧａＡｓＦＥＴでは、遮断周波数向上の点
でも、利得の点でも、また雑音低減の点でもゲート長を
極力小さく （１μｍ以下）する必要がある。そのため
に高度な微細加工技術が要求され、従来では２通常の光
露光ではなく電子ビームやＸ線露光を採用しなければな
らず、さらにゲートとソース及びドレインとの位置合せ
等も非常に複雑になるという欠点を有していた。However, in GaAsFETs, it is necessary to make the gate length as small as possible (1 μm or less) in terms of improving the cutoff frequency, increasing gain, and reducing noise. This requires advanced microfabrication technology, which requires the use of electron beams or X-ray exposure instead of conventional light exposure, and the alignment of the gate, source, and drain, etc., is extremely complicated. It had the disadvantage of being
また従来では、ゲートがショットキー接触であ８′″″
５°゛１１７”１１１２〜３ （Ｖ） ｉｔ！？、ｂ
。In addition, in the past, the gate had a Schottky contact and was 8′″″
5°゛117”1112~3 (V) it!?, b
.
す、耐圧が低いという欠点があった。However, it had the disadvantage of low pressure resistance.
さらにゲートとソース及びドレインの位置合せが複雑で
あることも関連して、従来の方法ではソース、ドレイン
間の距離をゲート長より大きくとる必要があり、直列抵
抗Ｒｓが大きくなって、その結果ＦＥＴの伝達コンダク
タンスｇｍが小さく遮断周波数が低いという欠点も有し
ていた。Furthermore, due to the complicated alignment of the gate, source, and drain, conventional methods require the distance between the source and drain to be larger than the gate length, which increases the series resistance Rs. It also had the disadvantage of a small transfer conductance gm and a low cut-off frequency.
（４） 発明の目的
本発明は上記従来の欠点に鑑み、目的とするところは、
ゲート耐圧の高い電界効果トランジスタを提供すること
にある。(4) Purpose of the invention In view of the above-mentioned conventional drawbacks, the present invention aims to:
An object of the present invention is to provide a field effect transistor with high gate breakdown voltage.
さらに目的とするところは、光露光法を使用してゲート
長を１μｍ以下に小さくすると同時にソース、ドレイン
間距離を短縮して遮断周波数を向上させる電界効果トラ
ンジスタの製造方法を提供することにある。A further object of the present invention is to provide a method for manufacturing a field effect transistor in which the gate length is reduced to 1 μm or less using a light exposure method, and at the same time the distance between the source and drain is shortened to improve the cutoff frequency.
（５） 発明の構成
上記目的は本発明によれば、同一導電型のへテロ接合を
有し、２次電子ガスを利用して高速動作させる電界効果
トランジスタにおいて、ＰＮ接合５−
ゲートを設けた電界効果トランジスタを提供することに
より達成される。また、上記目的は本発明によれば、同
一導電形のへテロ接合を有し２次元電子ガスを利用して
高速動作させる電界効果トランジスタの製造方法におい
て、該電界効果トランジスタの半導体積層構造の表面に
形成された一導電形の半導体層の上に反対導電形の半導
体層を成長させる工程と、該反対導電形半導体層の上に
形成されたゲート電極をマスクにして上記反対導電形半
導体層を選択的にエツチングする工程と、上記ゲート電
極をマスクにしてソース電極とドレイン電極を被着形成
する工程とを設けたことを特徴とする電界効果トランジ
スタの製造方法を提供することによって達成される。(5) Structure of the Invention According to the present invention, the above object is to provide a field effect transistor having heterojunctions of the same conductivity type and operating at high speed using secondary electron gas, in which a PN junction 5-gate is provided. This is achieved by providing a field effect transistor. According to the present invention, the above object is a method for manufacturing a field effect transistor that has heterojunctions of the same conductivity type and operates at high speed using two-dimensional electron gas. a step of growing a semiconductor layer of an opposite conductivity type on a semiconductor layer of one conductivity type formed on a semiconductor layer of one conductivity type; and a step of growing a semiconductor layer of an opposite conductivity type using a gate electrode formed on the opposite conductivity type semiconductor layer as a mask. This is achieved by providing a method for manufacturing a field effect transistor, which comprises a selective etching step and a step of depositing and forming a source electrode and a drain electrode using the gate electrode as a mask.
（６） 発明の実施例 以下本発明の実施例を図面を用いて詳細に説明する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図（ａｌないし第１図（ｅｌは本発明による電界効
果トランジスタの一実施例の製岳工程順図である。FIGS. 1A to 1E are sequential diagrams of the manufacturing process of an embodiment of a field effect transistor according to the present invention.
先ず、第１図（ａ）において１図示されていない半６−
絶縁性基板上にノンドープＧａＡｓ層１を３０００人、
その上に約２×１０ 印 のｎ形ＡＩ！ （０，３）Ｇ
ａ （０，７）Ａｓ層２を約３００人、つづいてＡβの
比率を漸減させた約２×１０ ｃｍ のｎ形Ａ／！ （
Ｘ） Ｇａ （１−Ｘ） Ａｓ層３を約３００人、その
上に２×１０〜２×１０ ｃｍ のｎ形Ｇ ａ Ａ ｓ
ｉｉ ４を約３００人、そして最後に約２×１０ 印
のＰ形Ａｎ （０，３）Ｇａ （０，７）Ａｓ層５を
約３００人を連続的に分子線エピタキシ（ＭＢＥ）等を
用いて成長させる。つづいてアイソレーションのために
メサ形成を行なう。First, in FIG. 1(a), a non-doped GaAs layer 1 was deposited on a semi-insulating substrate (not shown) by 3,000 people.
On top of that is an n-type AI with about 2×10 marks! (0,3)G
a (0,7) As layer 2 of about 300 layers, followed by about 2×10 cm of n-type A/! with a gradually decreasing proportion of Aβ! (
X) About 300 Ga (1-
ii 4 by about 300 people, and finally about 2 × 10 marks of P-type An (0,3) Ga (0,7) As layer 5 by about 300 people using molecular beam epitaxy (MBE) etc. and grow it. Next, a mesa is formed for isolation.
そして第１図（ｂｌに示すように、レジスト６を用い、
既成の光露光法によってゲート電極部をバターニングし
、真空中にてゲート金属７及び８ （アルミニウムＡ７
！等）を被着させることによって厚さ０．５〜１μｍの
ゲート電極８が形成される。Then, as shown in FIG. 1 (bl), using resist 6,
The gate electrode portion is patterned using a conventional light exposure method, and gate metals 7 and 8 (aluminum A7
! etc.) to form a gate electrode 8 having a thickness of 0.5 to 1 μm.
第１図（Ｃ）には、リフトオフ法によってゲート電極８
以外の不要部分９を取除いた状態が示されている。In FIG. 1(C), a gate electrode 8 is formed by the lift-off method.
The state is shown with unnecessary parts 9 other than those removed.
ここでＰ形Ａｊ！ （０，３）Ｇａ （０，７）Ａｓ層
５のみを選択的にエツチングするエツチング液（塩酸Ｈ
ＣＩとりん酸Ｈ３Ｐ０ａとの混合液）によってエツチン
グを行なう。その際ゲート電極８の下までサイドエツチ
ングすることによってゲート電極８のゲート長よりも短
い、すなわち１μｍ以下のＰＮ接合ゲートを極めて容易
に得ることができる。第１図（ｄ＋はエツチングによっ
てＰ形Ａｌ２（０，３）Ｇａ （０，７）Ａｓ層５がゲ
ート電極８より短縮化された状態を示している。P-type Aj here! (0,3) Ga (0,7) As an etching solution (hydrochloric acid, H
Etching is performed using a mixed solution of CI and phosphoric acid H3P0a). At this time, by performing side etching to the bottom of the gate electrode 8, a PN junction gate having a length shorter than the gate length of the gate electrode 8, that is, 1 μm or less, can be obtained very easily. FIG. 1 (d+ shows a state in which the P-type Al2(0,3)Ga(0,7)As layer 5 is shortened from the gate electrode 8 by etching.
そして最後にゲート電極８をマスクにしてソース及びド
レイン電極を形成する。その際、先ず１２重量％の金−
ゲルマニウム合金（以下ＡｕＧｅと記す）を被着させ１
次に酸化防止のために金ＡｕをＡｕＧｅの上に被着させ
る。そしてＡｕＧｅとｎ形ＧａＡｓ層４とをオーミック
接触させるために４５０℃の窒素雰囲気中で２分間合金
化処理を行ない、第１図（ｅ）に示すようにソース電極
１２、ドレイン電極１３が形成される。同図中において
ゲート電極８上にはソース電極１２及びド 。Finally, source and drain electrodes are formed using the gate electrode 8 as a mask. At that time, first 12% by weight of gold-
Germanium alloy (hereinafter referred to as AuGe) is deposited 1
Next, gold (Au) is deposited on the AuGe to prevent oxidation. Then, in order to make ohmic contact between the AuGe and the n-type GaAs layer 4, an alloying process is performed for 2 minutes in a nitrogen atmosphere at 450° C., and a source electrode 12 and a drain electrode 13 are formed as shown in FIG. 1(e). Ru. In the figure, a source electrode 12 and a gate electrode are provided on the gate electrode 8.
レイン電極１３と同じＡｕ及びＡｕ００層１１が形成さ
れるがゲートの特性に影響を及ぼすことはない。また２
次元ガス層１４はノンドープＧａＡ３層１の界面付近に
生成するもので、このガス層１４によってＦＥＴの高速
動作が可能となる。Although the same Au and Au00 layers 11 as the rain electrode 13 are formed, they do not affect the characteristics of the gate. Also 2
The dimensional gas layer 14 is generated near the interface of the non-doped GaA 3 layer 1, and this gas layer 14 enables high-speed operation of the FET.
なおソース電極１２及びドレイン電極１３を形成する前
に、ゲート電極８をマスクとしてイオン注入を施して予
めＮ 層を形成し、熱処理によって活性化した後でソー
ス電極１２及゛びドレイン電極１３を形成してもよい。Note that before forming the source electrode 12 and drain electrode 13, an N layer is formed in advance by ion implantation using the gate electrode 8 as a mask, and after activation by heat treatment, the source electrode 12 and drain electrode 13 are formed. You may.
ただしその場合は熱処理工程を要するためにゲートの材
料をシリサイド（ＴｔＷＳｉあるいはＷＳｔ等）の耐熱
性のある高融点金属にする必要がある。However, in that case, since a heat treatment process is required, the material of the gate needs to be a heat-resistant, high-melting point metal such as silicide (TtWSi, WSt, etc.).
（７） 発明の効果
以上詳細に説明したように本発明による電界効果トラン
ジスタは、ＰＮ接合ゲートを有するために従来のショッ
トキ形ゲートに比べて高耐圧となり、１０ｖ以上の電圧
を印加することが可能となる。(7) Effects of the Invention As explained in detail above, the field effect transistor according to the present invention has a PN junction gate, so it has a higher withstand voltage than the conventional Schottky gate, and can apply a voltage of 10 V or more. becomes.
また製造方法において、Ｐ形ＡβＧａＡｓ層を９−
ゲート電極をマスクにして選択的にエツチングを行ない
、さらにサイドエツチングすることで微細なゲートを得
ることができ、遮断周波数の向上をもたらす。さらにゲ
ート電極をマスクにしてソース、ドレイン電極を形成す
るために、工程数が少なり、シかも精密制御を要する工
程が事実上ゲート電極形成工程のみであり、電界効果ト
ランジスタの均一性や安定性が向上する。またソース、
ドレイン電極間の直列抵抗が低減するので伝達コンダク
タンスが向上する。また表面の露出面はＧａＡｓ面にな
るので特性の劣化が少ない等の効果がある。In addition, in the manufacturing method, the P-type AβGaAs layer is selectively etched using the 9-gate electrode as a mask, and further side etching is performed to obtain a fine gate and improve the cutoff frequency. Furthermore, since the source and drain electrodes are formed using the gate electrode as a mask, the number of steps is reduced, and the only step that requires precise control is actually the gate electrode formation step, which improves the uniformity and stability of the field effect transistor. will improve. Also sauce,
Since the series resistance between the drain electrodes is reduced, the transfer conductance is improved. Furthermore, since the exposed surface is a GaAs surface, there is an effect that there is less deterioration of characteristics.
第１図は本発明の一実施例の製造工程順図である。
１・・・ノンドープＧａＡｓｆＷ、 ２・・・ｎ形ＡＩ
Ｖ、（０，３）Ｇａ （０，７）Ａｓ層。
３・・・ｎ形Ａ＃ （ｘ） Ｇａ （１−Ｘ） Ａｓ層
。
４−＝ｎ形ＧａＡｓ層、 ５・・−ｐ形Ａ１ （０，３
）Ｇａ （０，７）Ａｓ層、 ８・１０−
・・ゲート電極、 １２・・・ソース電極。
１３・・・ドレイン電極、 １４・・・二次元ガス
１１−
第１図FIG. 1 is a sequential diagram of a manufacturing process according to an embodiment of the present invention. 1... Non-doped GaAsfW, 2... n-type AI
V, (0,3)Ga(0,7)As layer. 3...n-type A# (x) Ga (1-X) As layer. 4-=n-type GaAs layer, 5...-p-type A1 (0,3
)Ga(0,7)As layer, 8.10-...gate electrode, 12...source electrode. 13...Drain electrode, 14...Two-dimensional gas 11- Fig. 1
Claims (6)
を利用して高速動作させる電界効果トランジスタにおい
て、ＰＮ接合ゲートを設けたことを特徴とする電界効果
トランジスタ。(1) A field effect transistor having a heterojunction of the same conductivity type and operating at high speed using two-dimensional electron gas, characterized in that it is provided with a PN junction gate.
り短いことを特徴とする特許請求の範囲第１項記載の電
界効果トランジスタ。(2) The field effect transistor according to claim 1, wherein the gate length of the PN junction gate is shorter than the gate electrode.
を利用して高速動作させる電界効果トランジスタの製造
方法において、該電界効果トランジスタの半導体積層構
造の表面に形成された一導電形の半導体層の上に反対導
電形の半導体層を成長させる工程と、該反対導電形半導
体層の上に形成されたゲート電極をマスクにして上記反
対導電形半導体層を選択的にエツチングする工程と、上
記ゲート電極をマスクにしてソース電極とドレイン電極
を被着形成する工程とを設けたことを特徴とする電界効
果トランジスタの製造方法。(3) In a method for manufacturing a field effect transistor that has a heterojunction of the same conductivity type and operates at high speed using two-dimensional electron gas, a field effect transistor of one conductivity type formed on the surface of a semiconductor stacked structure of the field effect transistor a step of growing a semiconductor layer of an opposite conductivity type on the semiconductor layer of the opposite conductivity type, and a step of selectively etching the opposite conductivity type semiconductor layer using a gate electrode formed on the opposite conductivity type semiconductor layer as a mask. A method for manufacturing a field effect transistor, comprising the step of depositing and forming a source electrode and a drain electrode using the gate electrode as a mask.
する工程はゲート電極下のサイドエツチングを含むこと
を特徴とする特許請求の範囲第３項記載の電界効果トラ
ンジスタの製造方法。(4) The method of manufacturing a field effect transistor according to claim 3, wherein the step of selectively etching the opposite conductivity type semiconductor layer includes side etching under the gate electrode.
あることを特徴とする特許請求の範囲第３項記載の電界
効果トランジスタの製造方法。(5) The method for manufacturing a field effect transistor according to claim 3, wherein the - conductivity type semiconductor is n-type gallium arsenide.
ガリウムヒ素であることを特徴とする特許請求の範囲第
３項記載の電界効果トランジスタの製造方法。(6) The above-mentioned opposite conductivity type semiconductor is P-type aluminum.
4. The method of manufacturing a field effect transistor according to claim 3, wherein the material is gallium arsenide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11907483A JPS6010785A (en) | 1983-06-30 | 1983-06-30 | Field effect transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11907483A JPS6010785A (en) | 1983-06-30 | 1983-06-30 | Field effect transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6010785A true JPS6010785A (en) | 1985-01-19 |
Family
ID=14752233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11907483A Pending JPS6010785A (en) | 1983-06-30 | 1983-06-30 | Field effect transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010785A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62117666A (en) * | 1985-11-15 | 1987-05-29 | Fuji Photo Film Co Ltd | Coating method |
| US5591266A (en) * | 1994-03-25 | 1997-01-07 | Tdk Corporation | Extrusion type coating head |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5123090A (en) * | 1974-08-20 | 1976-02-24 | Matsushita Electronics Corp | SETSUGOGEETOGATADENKAIKOKATORANJISUTA |
| JPS51115780A (en) * | 1974-10-31 | 1976-10-12 | Matsushita Electric Ind Co Ltd | Hetero junction gate form fieid effect transistor and manufacturing me thod |
| JPS5922367A (en) * | 1982-07-29 | 1984-02-04 | Nec Corp | Semiconductor device |
-
1983
- 1983-06-30 JP JP11907483A patent/JPS6010785A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5123090A (en) * | 1974-08-20 | 1976-02-24 | Matsushita Electronics Corp | SETSUGOGEETOGATADENKAIKOKATORANJISUTA |
| JPS51115780A (en) * | 1974-10-31 | 1976-10-12 | Matsushita Electric Ind Co Ltd | Hetero junction gate form fieid effect transistor and manufacturing me thod |
| JPS5922367A (en) * | 1982-07-29 | 1984-02-04 | Nec Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62117666A (en) * | 1985-11-15 | 1987-05-29 | Fuji Photo Film Co Ltd | Coating method |
| US5591266A (en) * | 1994-03-25 | 1997-01-07 | Tdk Corporation | Extrusion type coating head |
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