JPS6378575A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable an electrode to be formed very closely with excellent insulating properties by a method wherein with an organic material such as photoresist etc. formed, a convex flat part is coated with an electrode material through the intermediary of an insulating film formed on the side of convex region and then the photoresist part is removed. CONSTITUTION:A semiconductor layer 3 to form an electrode thereon is exposed by dry-etching process etc. using a photoresist 2 normally patterned in length of 1-several mum. In such a state, the sidewall parts of region 1 is coated with insulating film 4 at low temperature not to deform the photoresist 2. Next, the insulating film 4 in flat part is selectively removed using the photoresist 2 as a mask and successively coated with an electrode metal 5 to remove the electrode on the photoresist part. Through these procedures, an extremely thin insulating film with excellent downward step coverage from the patterned photoresist can be formed so that the processes may be simplified to electrically isolate the parts between source and gate or emitter and base very stably.

Description

[Detailed Description of the Invention] [Industrial Application Field] The first invention relates to a self-aligned electrode formation technique, and in particular, to a semiconductor device suitable for forming extremely close electrodes with good insulation, and a semiconductor device thereof. Regarding the manufacturing method.

The second invention relates to the formation of minute electrodes, and particularly to a method of manufacturing a semiconductor device suitable for forming submicron gate electrodes and emitter electrodes.

[Conventional technology]

Conventionally, compound semiconductors, gallium arsenide (GaAs
), 2DEC-FET (two-dimensional electron gas field effect transistor) or HBT (heterojunction bipolar transistor) using a heterojunction of aluminum gallium arsenide (A n GaAs) for the purpose of improving transistor performance. In FETs, efforts have been made to reduce the parasitic resistance R8□ by shortening the distance between the source/drain electrodes and the gate electrode (IEICE Technical Research Report, Vol. 85. No. 263.
PP, 103-110), while in HBT,
Efforts have been made to shorten the emitter and base electrodes in order to reduce the base resistance rnn'. This is discussed, for example, in International Electron Devices Meeting, 1985, p. 325.
national electron device
eMeet, ing.

1985, p. 325).

In addition, compound semiconductors, especially GaAs MESFET (Meta
lSemiconductor Field Ef
large-scale integrated circuits (intog
rated C1rcuit, (LSI))
(For example, Promedinges of the IEEI Gari Arsenic Icy Symposium, No. 4)
pp. 1-44, November, 1985 (Proceed
ingsof the I E E E GaAs I
CSy+nposium.

pp, 41-44. Nov, 1985), conventionally mainly high-temperature metals (e.g., NSi,
WAfl) was used as the gate metal, and ion implantation was used to form the n+ (high concentration layer) region using a highly heat-resistant metal as the mask ion.

Figure 5 shows a cross-sectional view of the main part of the FE'T (same side as the gate electrode).
Shown in a) and (b).

Since the n medium region 25 is formed by ion implantation using the high heat resistant metal 14' as a mask, a part of the lower part of the gate metal 14' becomes an n+ region, and the transistor threshold voltage Vt
This caused a so-called short channel effect in which h was dependent on the gate length.

On the other hand, as a solution to this problem, a structure using a sidewall insulating film 109 of gate metal in the n+ region has been realized as shown in FIG. 5(b).

[Problem that the invention seeks to solve]

In the above conventional technology, as seen in (1) 2DEG-FET formation, side etching of the gate metal is performed using a gate photoresist as a mask ion, and the source/drain metal is formed by vacuum evaporation in a self-aligned manner. In this method, the source and drain metals are deposited isotropically, so short-circuits between the source and gate often occur.

(2) On the other hand, as seen in the HBT formation example, in order to electrically isolate the emitter region and the base electrode, a method was used in which 5i02 was deposited on the sidewalls of the emitter region. However, this method of removing the photoresist and forming SiO2 after forming the emitter region has the drawback that a new lithography step is required to take out the base electrode, which complicates the process steps.

Furthermore, in the above conventional technique, the n+ region 125 is formed even below the gate gold GL14' (FIG. 5(a)), so it is extremely effective for reducing the low range of the source-gate parasitic resistance R, . , high transistor performance (for example, transconductance gm~200~3oOmS/lll11) has been achieved.

However, in the above conventional technology, (3) due to the limitations of gate metal processing technology, the gate length Lg inevitably varies from lot to lot, and as a result, the threshold voltage Vth fluctuates due to the short channel effect.
This was the main cause of the decline and variation in SI access time.

(4) After forming the gate metal 114', high temperature (800°C)
Since the n+ region is activated by annealing (before and after), the threshold voltage Vth fluctuates due to a reaction between the gate metal and the n-type active layer 110, causing a reduction in LSI access time.

The above-mentioned problems (3) and (4) are unavoidable problems in the process of using such a high heat-resistant metal as a mask material for n'' ion implantation.

In particular, submicron gate length is essential for improving the performance of LSIs, and in this case, it is essential to solve problem (3) above.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above problems.

[Means for solving problems]

The above-mentioned problems (1) and (2) can be solved by using a low-temperature insulating film forming technique that allows formation of a pattern on an organic material such as photoresist without deforming the photoresist.

The main points of the invention will be explained using FIGS. 1(a), (b), and (c).

Patterned photoresist 2, typically 1 to several μm long
Using etching as a mask material, etching such as dry etching is used to expose the semiconductor layer 3 where electrodes are to be formed. 1
is a general term for a portion of the semiconductor layer 3 that is desired to be electrically insulated from the electrode 5, and is named region 1. In this state, an insulating film (for example,
(SiN, etc.) 4 is formed by a photo-CVD method.

In this case, an insulating film formation method with good step coverage is used. That is, it is necessary to deposit the insulating film 4 on the side wall portion of the region 1 (FIG. 1(a)).

Next, using a method such as dry etching, the flat portions of the insulating film 4 are selectively removed using the photoresist 2 as a mask. Subsequently, electrode metal 5 is deposited, and the electrode in the photoresist portion is removed using a method such as lift-off (Fig. 1 (C)).
.

The above problems (3) and (4) occur after the formation of the n10 regions.

This can be avoided by taking a step to form the gate metal.

It has been known that the variation in gate length is generally small within one wafer, but tends to be large between wafers or between lofts. Therefore, it is highly desirable to have a process step that allows adjustment of the gate surface after gate processing.

This will be explained using FIGS. 4(a) to 4(g).

After forming insulating layers 121, 122 and 123 on the semiconductor layer 110, a gate photoresist 124 is formed. The insulating layers 122 and 123 are selectively removed using the gate photoresist 124 as a mask, except by dry or wet etching.

Roughly speaking, the width of the gate photoresist 124 is usually 0.8μ.
m to about 10 μm.

Next, photoresist processing is applied to the necessary areas, and step 124 is performed.
Ions 125 such as S+ using 123 and 122 as mask materials
Ions are implanted using the insulating film 121 as a through film (FIG. 4(b)). Furthermore, the photoresist 124 etc. are removed and cleaned, annealed and activated, and a photoresist 126 is applied and planarized over the entire surface, as shown in FIG. 4(c). The state shall be as follows. Insulating film 12
2, the insulating film 123 is selectively removed, and a low-temperature insulating film 113 is formed using an insulating film forming method with good step coverage without deforming the photoresist 126, such as photo-CVD. Furthermore, the insulating film 113 on the photoresist and the insulators 122 and 121 are removed using real-tropic dry etching. (Figure 4(e)).

In this case, it is preferable that side etching occurs in the insulating film 122 during etching. Further, it is desirable that side etching does not occur in the insulating film 121.

Next, an electrode metal 114 is deposited on the entire surface, and a W1 pole 114 is formed by a lift-off method (FIG. 4(f)).

Next, source/drain electrodes 130 and 131 are formed to complete the process.

[Effect]

As shown in FIG. 1, in the first invention, the region 1 under the patterned photoresist and the electrode 5 can be separated in a self-aligned manner in one lithography step, so the process is greatly simplified. In addition, photo-CVD is used as the insulating film 4 to be deposited.
If 5iN or the like is selected, the deposition rate is very slow (3 nm/min), so the film thickness can be controlled very well, and a very thin sidewall insulating film can be formed, so it is possible to create a structure with extremely low parasitic resistance Rsg in FETs. In the HBT, a structure with an extremely small base resistance rnn' can be realized.

As shown in FIG. 4, in the method for manufacturing a semiconductor device according to the second invention, dummy gate processing (FIGS. 4(b) and 4(c)) is performed.
), (d)), the dummy gate length can be actually measured.

After measuring the dummy gate length, the deposition speed was very slow (2-1
(0 nm/min) The film thickness of the photo-CVD insulating film 113 can be adjusted to a desired gate length.

Furthermore, the n medium region 125 is located approximately 0.2 μm inside the dummy gate length due to diffusion (FIG. 4(C)). However, the film thickness of the photo-CVD insulating film 113 is set to 0.1 to 0.4 μm.
By appropriately selecting the film thickness, the distance between the gate metal 114 and the n+ region 125 can be determined with excellent controllability.

By the above method, it is possible to solve one of the above-mentioned problems, that is, the short channel effect due to variations in gate length and the problem of improving gate breakdown voltage.

Furthermore, since a high temperature process is not performed after forming the gate metal, fluctuations in the threshold voltage Vth peculiar to high temperature processes are eliminated.

〔Example〕

Hereinafter, the first invention will be explained in more detail through Examples 1 and 2.

(Example 1) An example in which the present invention is applied to a 2DEC-FET is shown in FIGS. 2(a) and 2(b).

1 liter of undoped GaAs was deposited on a semi-insulating GaAs substrate lo using MBE (molecular beam epitaxy).
μm, undoped AQ) (Gal-XA5 (x~0.
3) n-type AQ xGal-xAs (x ~ 0.3
) 13 at 30 nm, St slightly (~10”ell
-3) 20 nm of doped n-GaASWJl 4 was formed.

After device isolation by mesa etching, gate electrode metal 1 (Afl, Mo/Au, etc.) is separated by 50 cm.
It was covered. Further, a photoresist 2 having a length of 0.9 μm and a thickness of 0.8 μm was patterned.

Subsequently, gate metal 1 was selectively processed by dry etching using photoresist 2 as a mask. At this time, the amount of side etching of the gate metal was 0.25 μm. Furthermore, SiN was deposited on the entire surface to a thickness of 150 nm using a photo-CVD method. Furthermore, SiN on the flat portions was removed by dry etching using CF 4 gas. Next, the source
Drain electrode metal (AuGe/Ni/Au
) was deposited to a thickness of 200 nm (FIG. 2(b)).

Next, the photoresist 2 on the gate electrode 1 and the source/drain electrode metal 15 are removed using a normal lift-off process.
was removed. The gate electrode gate length in this case is 0.4μ
m, and the noise figure at high frequency 12 GHz is 1.0.
dB, making it possible to realize an extremely low noise FET.

Furthermore, in the present invention, since the ohmic electrode 15 and the gate electrode 1 are electrically isolated very well by the photo-CVD 5iN film 4, the phenomenon of poor contact between the source and gate, which often occurred in conventional known examples, can be avoided. is gone.

In this embodiment, a case where the present invention is applied to a normal 2DEC-FET has been described.

However, the gate electrode 1 is replaced with p-type GaAs or p-type C, aAs/AQGaAs, and the thickness of the undoped GaAs 1l is kept to about 300 nm, and P+GGaA is formed between the undoped GaAs 1l and the substrate IO.
s400n was formed. The so-called 2DEC-HBT (2
It is also applicable to dimensional electron gas/Petero bibolar transistors).

(Example 2) FIGS. 3(a) and 3(b) show an example in which the present invention is applied to the formation of emitter and base electrodes of HB T.

Shown in (c) and (d).

Undoped P-G a As was deposited on a semi-insulating GaAs substrate lO using MOCVD (metal organic pyrolysis).
After forming the layer 51 with a thickness of 1 μm as a buffer layer, 5
The n" GaAS layer 52 containing X 10 "cm-"
000 people, 3000 people of n-type GaAs56 containing 5 x 1015 cm-' of Si, and furthermore I x 10 of Mg.
1000 p”GaAs54 containing 19Cal-3
Man.

2000 A Q O3 Gao 7 As55 containing 5 x 10171''3 Si, 1000 n-type GaAs56 with the same doping, 5 Si
x 1016cm-3 containing n”GaAs57
00 people formed. Subsequently, a photoresist 58 forming an emitter region was formed, and after selectively etching down to the n-GaAs 56 using a CCU 2 F 2 /He mixed gas, the n-type AQGaAs 55 was removed by chemical etching. Subsequently, 3000 layers of 5iN60 were deposited by photo-CVD, and then the SiN on the flat portions was removed by dry etching. AuZn2000 using photoresist 58 as a mask
After the lift-off, alloying was carried out at 450°C. (Figure 3(b)), then continue with the positive vcVDsi
After forming 3000 N61, using a flattening process,
After exposing the emitter part, A for every 6 emitter poles.
uGe/Nt/Au was formed.

Subsequently, collector electrodes and isolation between elements were performed using conventional methods.

In this example, the case where the present invention is applied to a normal npn-type HBT was explained, but the pnp-type HBT, which has excellent injection efficiency,
It is also applicable to BT.

Examples of the second invention will be described below.

(Example 3) In GaAs-MESFET, 0.5 ttmFE
An example of forming T is shown in the steps shown in FIG. 4, with specific materials, film thicknesses, and doping levels written down.

50 nm of 5iN121 was deposited on the n-type active layer region 110 formed by ion implantation on a semi-insulating GaAs substrate.
Formed by CVD method. Subsequently, 300 nm of Si 02122 and 400 nm of S i N 123 are formed. After processing the gate photoresist 124 with a length of 1.2 μm, using dry etching and chemical etching,
Insulating films 122 and 123 are selectively removed. Si ions 125 at a dose of 3 x 1013 am-3 and an accelerating voltage of 17
The photoresist 124 and the insulating film 122 under the condition of 0 keV
, 123 as a mask, ions are implanted. (Figure 4(b)
)) After removing the photoresist, annealing was performed at 800° C. for 10 minutes to activate the Si ions 125. Next, using a planarization process, photoresist 126 was buried up to the height of the dummy gate 123.degree. 122 (FIG. 4(C)) (FIG. 4(C)).

Next, the S i N 123 was removed, and 5iN 113 was formed to a thickness of 300 nm using a photo-CVD method.

Using anisotropic etching, the flat part of the photo-CVD 5iN113 is removed, and then isotropic etching is used to remove the Si○212
2. Furthermore, S i N 121 is removed (Fig. 4(e)
).

A gate electrode 114 is formed by vacuum-depositing Ti/Pt/Au, Au, or Mo/Au to a thickness of about 200 nm as a gate metal and lift-off (FIG. 4(f)).

Finally, the source/drain electrodes 130 are
, 131 are formed.

In this embodiment, three layers of dummy gate insulating films 121 and 12 are used.
2,123 was used, but this is not necessary.

A single insulating film or a two-layer insulating film may be used.

Furthermore, although the present invention has been shown as an example in which it is applied to the formation of a gate electrode of a GaAs MESFET, the present invention is also effective in a 2DEG-FET using an AQGaAs/GaAs heterojunction. In this FET, the gate length is 0.5 μm, and the mutual conductance gm at gate voltage O is 35
It was 0m5/mm. 50-1 compared to the conventional structure
00m5/aha large mutual conductance was obtained.

(Example 4) G a A sMESFE when source and drain electrodes are formed in a self-aligned manner with respect to a dummy gate insulating film
The main parts of an embodiment in which the present invention is applied to a T are shown in Figure 6 (
Shown in a), (b), (c), and (d).

The cross-sectional structure after n+ ion implantation (FIG. 4(b)) and annealing of Si in Example 3 is shown in FIG. 6(,).

n+ region 125 using dummy gates 122 and 123 as a mask
The upper insulating film 121 is removed. Next, AuGe/N
AuGe/Ni/A on the dummy gate 123 by vacuum evaporating 150rzn of i/Au and using a planarization process.
u is removed and a photoresist 126 is buried.

Thereafter, the steps shown in FIG. 4(d) and subsequent steps of Example 3 were performed.

By forming the ohmic electrodes in a self-aligned manner in this way, it is possible to reduce the distance between the source and gate electrodes to approximately 0.2 μm, and the source-gate resistance can be significantly reduced.

In addition, since n+ ions are implanted using the dummy gate insulating film as a mask material, n+H penetrates approximately 0.2 μm inward from both ends of the mask material, making it difficult to perform photo-CVD or SjN.
．． By depositing 3 μm, the gate length can be made extremely small, and there is an effect that the gate metal layer does not need to come into contact with the n-middle region. Therefore, the VB obtained from the source and gate can be as high as 10 to 14V.

The length of the dummy gate insulating film is determined by the dry etching conditions.
Generally, variations of about ±0.2 μm occur depending on the formation conditions of the photoresist length.

Photo-CVD has an extremely slow insulating film deposition rate (~3 nm/
m1n), it has the great advantage that after measuring the dummy gate length, the thickness of the deposited film can be adjusted so that the desired gate electrode length can be achieved.

The present invention can also be applied to 2DEG-FETs.

(Example 5) GaAs when the present invention is implemented using a single insulating film
An example of MESFET fabrication is shown in FIG.

700n of CVD SiO2122 on the active layer 110
After forming the gate photoresist 124, a gate photoresist 124 is formed. SiO2 is removed by dry processing, and St ions 125 are implanted. 200n of 5iN127 after removal on photoresist
m is deposited and annealed. As in the fourth embodiment, the source/drain electrodes 130 are connected to the dummy gate 122.
131 is deposited, a planarization process is used to embed photoresist 126, and after removing 5i02122, optical CV is applied.
D5iN' is applied (FIG. 7(d)).

Next, as the gate metal, T i / P t /
Although Au was deposited, the deposition lift-off may be performed using -A Q y M o /A u or the like.

(Embodiment 6) FIG. 8 shows an embodiment in which the present invention is applied to the formation of an emitter region and a base region of an npn-type HBT (peterojunction bipolar transistor).

Using MBE (molecular beam epitaxy), an n medium-sized Ga As 5 was deposited on a semi-insulating Ga As substrate 150.
151, n-type GaAs152 (ml director region) p
”GaAs153 (base region), n-type AQGaAs
154 (emitter region), n-type GaAs 155, and n-type GaAs 156 (cap region) were formed. The film thickness and doping level are according to known specifications.

An emitter region is formed using the dummy gate insulating film 157 of Examples 3 to 5. Using this emitter region forming insulating film 157 as a mask, the n'' GaAs cap layer 156 is removed by etching. Mg ions 158 are etched at 175 keV 7 using the emitter region forming insulating film 57 as a mask material.
Implantation (Si
O2 was deposited to a thickness of 200 nm, and lamp annealing was performed at 1000° C. for 10 seconds to activate Mg ions 158.

The method of Example 3 or 4 was used to form the base electrode and emitter electrode. However, the base electrode material contains A u Z n
, AuGe/Ni/Au was used as the emitter electrode material.

A conventional method was used to separate the collector electrode forming elements.

Although this embodiment shows a case where the present invention is applied to an npn-type HBT, it is also applicable to a pnp-type HBT. In that case, Si ion implantation is used to form the base region. The base electrode has A u G e/N i/ A u
, and A u Z n is used for the emitter electrode.

In addition, there is a pnp-type HBT (referred to as 2DEG-HBT) that uses a two-dimensional electron gas formed at the interface between n-type AΩGaAs and undoped GaAs as a base layer.
The present invention is also applicable to

In this case, a dummy insulating film for emitter region formation is used, and P
After removing GaAs or AQGaAs in the sub-region, 5i
02 to 50 nm and Si at 175 keV 5X
It was implanted at a dose of 1013 cm-2 and activated using lamp annealing. At this time, the sheet resistance of the n-type base region into which ions were implanted was 70Ω/hole.

〔Effect of the invention〕

According to the first invention, an extremely thin insulating film with good step coverage can be formed on the patterned photoresist. It is possible to electrically isolate the two regions in an extremely stable manner.

(2) When applied to field effect transistors, FE
The source gate resistance Rsg of T can be significantly reduced. When applied to a Peter junction bipolar transistor, the base resistance rnn' can be significantly reduced.

Furthermore, according to the second invention, an n-thickness or P-medium region can be formed using a dummy gate (or emitter) insulating film as a mask, and after the photoresist is buried and flattened, the dummy insulating film is removed and photo-CVD, etc. After depositing an insulating film that does not deform the photoresist on the sidewalls, gate metal or emitter metal is deposited.
Since the source/drain total bend and the gate metal can be formed very close together (up to 0.1 μm) without contacting, the parasitic resistance Rsg between the source and gate can be minimized.

In addition, the deposition speed of photo-CvD is extremely slow (~3nm
7 minutes) Since an insulating film is used, the gate length can be controlled with extremely good controllability.

(2) When applied to an HBT, it is possible to achieve a low sheet resistance of the n+ side base region or the p+ side base region, and to place the n+ (or p'') region or base electrode and emitter region very close together (~0. 1 μm), and the base resistance can be extremely reduced.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram explaining the first invention, and FIG. Figure 3 shows the first
FIG. 4 is a process diagram showing the principle of the second invention. FIG. 5 is a cross-sectional diagram of a conventional FET. FIG. 7 is a main process diagram when the second invention is applied to an FET, and FIG. 8 is a main sectional structural diagram when the second invention is applied to the formation of an emitter and base region of an npn type HBT. 1... Emitter or gate region, 4... PhotoCVD
Insulating film, 2... Photoresist, 5... Electrode full bending, 3
...Semiconductor, 13.55-n-type AAGaAS, 12-
... Undoped A Q GaAs, 11,51... Undoped Ga As, 10-... Semi-insulating Ga
As substrate, 54-p” GaAs, 53.14.
=n-GaAs, 52, 57-n"GaAs, 5
6-n GaAs. 124...Gate emitter photoresist, 121
．． 122, 123... Insulating film, 110... Semiconductor layer, 126... Buried photoresist, 113... Light C
VD insulating film, 114...gate electrode, 130.131
...Source/drain electrode, 125...Si ion, 158...Mg ion, 154...P+GaAs
, 156-n"GaAs, 155-n type GaA
s, 152-n-GaAs, 151-n ”GaAs
. 'ku, 7th TI21 J￥hat 13 Potato 20 No. 3 Figure 3 Yobee 4s 71θ Dye 4 v $5 No. 2f 12 Ri Hayabusa Z mouth graduation 7 mouth

Claims (1)

[Claims] 1. For a convex region located directly below a patterned organic material such as a photoresist, an insulating film is formed on the side surface of the convex region while the organic material such as the photoresist is formed. A method for manufacturing a semiconductor device, comprising the steps of: removing the photoresist portion after the electrode metal disposed on the convex flat portion is deposited via the sidewall insulating film. 2. Using a patterned photoresist or an organic material as a mask, use a photomask for the processed or etched convex region, or use a photomask to implant ions or deposit metal on the convex region, and then embed the photoresist to flatten the convex region. After selectively etching away the convex areas and depositing an insulating film with good step coverage at a low temperature that does not deform the photoresist, etching away the flat part of the insulating film, then depositing a metal. A method for manufacturing a semiconductor device, characterized in that metal is formed only in concave portions.