JPH0815159B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a self-aligned electrode forming technique, and more particularly, to a semiconductor device suitable for forming electrodes which are extremely close to each other with good insulating property, and a semiconductor device thereof. It relates to a manufacturing method.

The second invention relates to the formation of minute electrodes, and more particularly to a method of manufacturing a semiconductor device suitable for forming submicron gate electrodes and emitter electrodes.

[Conventional technology]

2D using a conventional heterojunction of compound semiconductor, gallium arsenide (GaAs), and aluminum gallium arsenide (AlGaAs)
In EG-FET (two-dimensional electron gas field effect transistor) or HBT (heterojunction bipolar transistor), in order to improve the transistor performance, in 2DEG-FET, the distance between the source / drain electrode and the gate electrode is shortened, and parasitic A device has been made to reduce the resistance Rsg (Technical Report of IEICE, Vol.85, No.263, pp.103-1).
Ten). On the other hand, also in HBTs, measures have been taken to shrink the emitter and base electrodes in order to reduce the base resistance r _nn ′. About this, for example, International Electron Device Meeting, 1985, No. 325.
Page (International Electron Device Meeting, 1985, p.3
25).

Further, a compound semiconductor, GaAs MESFET (M etal S with particular reference to gallium arsenide (GaAs) emiconductor F ield E ffe
ct T ransistor) large-scale integrated circuit using the (L arge S ca
le I ntograted Circuit (LSI)) ( for example, professional Me Proceedings Of The Eye E Ii-Garihi iodine Icy Symposium, 41 pp to 44, November, 1985 (Proceedings of the IEEE GaAs IC Symposium , pp.41
-44, Nov. 1985))),
High heat resistant metals (eg, NSi and WAl) have been used as gate metals, and ion implantation for forming n ⁺ (high concentration layer) regions has been used with high heat resistant metals as mask ions.

Sectional views of the main part of the FET (same side of the gate electrode) are shown in FIGS. 5 (a) and 5 (b).

Since the n ⁺ region 25 is formed by the ion implantation method using the high heat resistant metal 14 ′ as a mask, the lower part of the gate metal 14 ′ is the n ⁺ region, and the threshold voltage V _{th of the} transistor is shown in the gate table. It caused the so-called short channel effect, which is dependent. On the other hand, as a solution to this problem, a structure using a side wall insulating film 109 of gate metal for the n ⁺ region has been realized as shown in FIG.

[Problems to be solved by the invention]

In the above-mentioned prior art, as seen in (1) 2DEG-FET formation, the side-etching of the gate metal is used with the gate photoresist as the mask ion, and the source / drain metal is vacuum-deposited in a self-aligned manner. In this method, the source / drain metal is isotropically deposited, so that a source-gate short circuit often occurs.

(2) On the other hand, as seen in the HBT formation example, in order to electrically separate the emitter region and the base electrode, a method of depositing SiO ₂ on the side wall of the emitter region has been adopted. However,
In this way, the photoresist is removed after the emitter region is formed,
In the method of forming SiO ₂ , since the base electrode is taken out,
There is a drawback that a new lithography process is required and the process steps are complicated.

Further, in the above-mentioned conventional technique, the n ⁺ region 125 is the gate metal 1.
Since it is formed up to the bottom of 14 '(Fig. 5 (a)), it is extremely effective in reducing the source-gate parasitic resistance R _sg , and has high transistor performance (for example, mutual conductance gm to 200 to 300 mS / mm). ) Has been realized.

However, in the above conventional technique, (3) the gate table Lg is inevitably varied from lot to lot due to the limitation of the gate metal processing technique, and as a result, the threshold voltage V _th varies due to the short channel effect. It was the main cause of the decrease and variation in access time of LSI.

(4) After the gate metal 114 'is formed, the n ⁺ region is activated by high temperature (around 800 ° C.) annealing.
The threshold voltage V _th fluctuates due to the reaction with the active layer 110, which causes a decrease in the LSI access time.

Regarding the above problems (3) and (4), there is an unavoidable problem in the process of using the high heat-resistant metal as a mask material for n ⁺ ion implantation.

In particular, submicron gate length is indispensable for improving LSI performance, and in that case, it was essential to solve the problem (3).

An object of the present invention is to provide a method of manufacturing a semiconductor device that can solve the above problems.

[Means for solving problems]

The above problems (1) and (2) can be solved by using a low-temperature insulating film forming technique that can be applied on an organic material such as a photoresist on which a pattern is formed without deforming the photoresist.

The essential points of the invention will be described with reference to FIGS. 1 (a), (b) and (c).

The semiconductor layer 3 on which the electrode is to be formed is exposed by etching such as dry etching using the patterned photoresist 2 having a length of 1 to several μm as a mask material.
Reference numeral 1 is a general term for a portion to be electrically insulated from the electrode 5 formed on the semiconductor layer 3, and is named a region 1. In this state,
An insulating film (eg, SiN by photo CVD method) 4 is formed at a low temperature that does not deform the photoresist 2.

In this case, an insulating film forming method with good step coverage is used. That is, it is necessary to deposit the insulating film 4 on the side wall of the region 1 (FIG. 1 (a)).

Next, the insulating film 4 in the flat portion is selectively removed by a method such as dry etching using the photoresist 2 as a mask.
Then, the electrode metal 5 is deposited, and the electrode in the photoresist portion is removed by a method such as lift-off (FIG. 1 (c)).

The problems (3) and (4) can be avoided by forming the gate metal after forming the n ⁺ region.

The variation in gate length is generally small within one wafer, and it is known that the variation between wafers or lots tends to be large. Therefore, it is highly desirable to have a process step in which the gate surface can be adjusted after the gate processing.

 This will be described with reference to FIGS. 4 (a) to 4 (g).

After forming the insulating layers 121, 122 and 123 on the semiconductor layer 110, the gate photoresist 124 is formed. Except for dry or wet etching, the insulating layers 122 and 123 are selectively removed using the gate photoresist 124 as a mask.

Generally, the width of the gate photoresist 124 is usually 0.8 μm or more.
It is about 10 μm.

Next, apply photoresist processing to the necessary areas, and
Ions 125 such as Si are deposited on the insulating film 121 using 3,122 as a mask material.
Is ion-implanted as a through film (FIG. 4 (b)). Further, after removing and cleaning the photoresist 124 and the like, annealing and activation are performed, and the photoresist 126 is applied and planarized on the entire surface to obtain a state as shown in FIG. 4 (c). Insulating film 123 against insulating film 122
Is selectively removed, and the low temperature insulating film 113 is formed by a method such as photo-CVD that does not deform the photoresist 126 and has a good step coverage. Further, by using anisotropic dry etching, the insulating film 113 on the photoresist and the insulator 1 are formed.
Remove 22,121. (Fig. 4 (e)). In this case, it is desirable that the insulating film 122 undergo side etching during etching. Further, it is desirable that side etching does not occur in the insulating film 121.

Next, the electrode metal 114 is deposited on the entire surface, and the electrode 114 is formed by the lift-off method (FIG. 4 (f)).

Next, the source / drain electrodes 130 and 131 are formed, and the process is completed.

[Action]

As shown in FIG. 1, in the first aspect of the invention, the region 1 under the patterned photoresist and the electrode 5 can be separated in a self-aligned manner in one lithography process, so that the process is greatly simplified. In addition, as the insulating film 4 to be deposited, optical CVDS is used.
If iN or the like is selected, the deposition rate is very slow (3 nm / min), so the film thickness controllability is extremely good, and a very thin sidewall insulating film can be formed. Therefore, in FET, the parasitic resistance R _sg is extremely small. The structure can be realized, and in HBT, the base resistance
A structure with extremely small r _nn ′ can be realized.

As shown in FIG. 4, in the method of manufacturing a semiconductor device of the second invention, dummy gate processing (see FIG. 4 (b),
In (c) and (d), the dummy gate length can be measured.

After measuring the dummy gate length, the deposition rate is very slow (2-
(10 nm / min) The film thickness of the photo CVD insulating film 113 can be adjusted to have a desired gate length.

Further, the n ⁺ region 125 is inwardly diffused by about 0.2 μm from the dummy gate length (FIG. 4 (c)). But,
By properly selecting the film thickness of the photo CVD insulating film 113 to about 0.1 to 0.4 μm, the distance between the gate metal 114 and the n ⁺ region 125 can be determined with good controllability.

By the above method, the problems of short channel effect and improvement of gate breakdown voltage due to variations in gate length, which are one of the above problems, can be solved.

Further, since the high temperature process is not passed after the gate metal is formed, the fluctuation of the threshold voltage V _th peculiar to the high temperature process is eliminated.

〔Example〕

Hereinafter, the first invention will be described in more detail through Examples 1 and 2.

Example 1 An example in which the present invention is applied to a 2DEG-FET is shown in FIGS. 2 (a) and 2 (b).

On the semi-insulating GaAs substrate 10, 1 μm of undoped GaAs11 and 1 μm of undoped Al are formed by MBE (molecular beam epitaxy).
The _{x Ga 1-x A s (} x~0.3) 12 3nm, Si and 2 × 10 ¹⁸ cm ^-3 doped n-type _{Al x Ga 1-x A s} (x~0.3) 13 to 30 nm, a slightly Si A (-10 ¹⁵ cm ^-3 ) doped n ^- GaAs layer 14 was formed to a thickness of 20 nm. After element isolation by mesa etching, a gate electrode metal 1 (Al, Mo / Au, etc.) was deposited to a thickness of 500 nm. Further 0.
The photoresist 2 having a length of 9 μm and a thickness of 0.8 μm was patterned. Subsequently, the gate metal 1 was selectively processed by using dry etching using the photoresist 2 as a mask. At this time, the side etching amount of the gate metal is 0.25μ.
It was m. Furthermore, SiN was deposited on the entire surface of 150 nm by using the photo-CVD method. Further, SiN in the flat portion was removed by dry etching using CF ₄ system gas. Next, a source / drain electrode metal (AuGe / Ni / Au) was deposited to a thickness of 200 nm (FIG. 2 (b)).

Next, using the normal lift-off process, the photoresist 2 on the gate electrode 1 and the source / drain electrode metal 15
Was removed. In this case, the gate electrode gate length is 0.4 μm
And the noise figure at high frequency of 12 GHz is 1.0 dB,
We were able to realize an extremely low noise FET. Further, in the present invention, the ohmic electrode 15 and the gate electrode 1 are formed by the photo CVD SiN film 4
Since it is electrically separated very well, the phenomenon of poor contact between the source and the gate, which often occurs in the known examples up to now, is eliminated.

In this embodiment, the case where the present invention is applied to a normal 2DEG-FET has been described.

However, if the gate electrode 1 is p-type GaAs or p-type Ga
Replaced with As / AlGaAs, and undoped GaAs11 with a film thickness of 300
p ⁺ between undoped GaAs 11 and substrate 10
GaAs was formed to 400 nm. It is also applicable to so-called 2DEG-HBT (two-dimensional electron gas / hetero bipolar transistor).

(Embodiment 2) An embodiment in which the present invention is applied to the formation of emitter and base electrodes of HBT is shown in FIGS. 3 (a), (b), (c),
It shows in (d).

On the semi-insulating GaAs substrate 10, MOCVD (Metal Organic Thermal Decomposition) was used to form the undoped p-GaAs layer 51 as a buffer layer of 1 μm, and then n ⁺ GaAs containing 5 × 10 ¹⁸ cm ^{−3 of} Si was formed.
N ^- GaAs53 containing layer 52 of 3000Å and Si of 5 × 10 ¹⁵ cm ^-3
Is 3000 Å, and p ⁺ GaAs54 containing Mg of 1 × 10 ¹⁹ cm ^-3 is 10
00Å, Al ₀₃ Ga _{07 As} 55 containing 5 × 10 ¹⁷ cm ^{-3 of} Si is 2000
Å, n-type GaAs56 with the same doping is 1000Å, Si is 5 × 10
2000 Å of n ⁺ GaAs57 containing ¹⁸ cm ^-3 was formed. Subsequently, a photoresist 58 that forms an emitter region is formed, and CCl ₂ F ₂ / H is used.
The n-type AlGaAs 55 was removed by chemical etching after selectively etching up to n-GaAs 56 using a mixed gas of e.
Subsequently, 3000 Å of optical CVD SiN60 was deposited, and SiN in the flat portion was removed by dry etching. AuZn2000Å is deposited using photoresist 58 as a mask, and after lift-off 450 ° C
Was alloyed. (FIG. 3 (b)). Subsequently, after plasma CVD SiN61 was formed at 3000 Å, a flattening process was used to expose the emitter portion, and then AuGe / Ni / Au was formed for each emitter electrode 6.

Subsequently, the collector electrode and the element were separated from each other by a usual method.

In this embodiment, the case where the present invention is applied to a normal npn type HBT has been described, but the present invention can also be applied to a pnp type HBT having excellent injection efficiency.

 An embodiment of the second invention will be described below.

(Embodiment 3) In a GaAs MESFET, an embodiment for forming a 0.5 μm FET will be shown in the process shown in FIG. 4 by writing down the specific material, film thickness and doping level.

SiN 121 is formed by the 50 nm CVD method on the n-type active layer region 110 formed by the ion implantation method on the semi-insulating GaAs substrate. Subsequently, SiO ₂ 122 is formed to 300 nm and SiN 123 is formed to 400 nm. length
After processing the 1.2 μm gate photoresist 124, the insulating films 122 and 123 are selectively removed by dry etching and chemical etching. Si ion 125 dose 3 × 10 ¹³ c
Ion implantation is performed under the conditions of m ^-3 and accelerating voltage of 170 keV using the photoresist 124 and the insulating films 122 and 123 as a mask. (FIG. 4 (b)) After removing the photoresist, annealing was performed at 800 ° C. for 10 minutes to activate Si ions 125. Next, using a planarization process, dummy gates 123 and 122 (FIG. 4 (c))
The photoresist 126 was embedded up to the height (FIG. 4 (c)).

Next, SiN123 is removed, and SiN113 is removed to 300 by photo CVD method.
nm formed.

By anisotropic etching, the flat portion of the optical CVD SiN113 removed, SiO ₂ 122 a further isotropic etching, further SiN12
1 is removed (Fig. 4 (e)).

Ti / Pt / Au or Al or Mo / Au as gate metal
Is vacuum-deposited for about 200 nm, and the gate electrode 114 is formed by lift-off (FIG. 4 (f)).

Finally, by mask alignment, the source / drain electrodes 130,
Form 131.

In this embodiment, three layers of dummy gate insulating films 121, 122, 12 are used.
We used 3, but this is not necessary. It may be a single insulating film or a double-layer insulating film.

Moreover, although the example applied to the formation of the gate electrode of the GaAs MESFET is shown, the present invention is also effective in the 2DEG-FET using the AlGaAs / GaAs heterojunction. In this FET, the gate length is
0.5μm, transconductance g at 0V gate voltage
m was 350 mS / mm. 50-100mS compared to the conventional structure
A large transconductance of / mm is obtained.

(Embodiment 4) Self-alignment of source / source to a dummy gate insulating film
FIG. 6 (a) shows a main part of an embodiment in which the present invention is applied to a GaAs MESFET in which a drain electrode is formed.
Shown in (b), (c) and (d).

FIG. 6 (a) shows the cross-sectional structure after annealing the n ⁺ ion implantation (FIG. 4 (b)) Si in Example 3.

Insulating film on n ⁺ region 125 with dummy gates 122 and 123 as a mask
Remove 121. Subsequently, AuGe / Ni / Au was vacuum-deposited at 150 nm, and a planarization process was used to deposit AuG on the dummy gate 123.
The e / Ni / Au is removed, and the photoresist 126 is embedded.

After that, the steps shown in FIG.

By thus forming the ohmic electrodes in a self-aligning manner, the distance between the source and gate electrodes can be reduced to about 0.2 μm, and the source / gate resistance can be greatly reduced.

Also, since n ⁺ ion implantation is performed using the dummy gate insulating film as a mask material, the n ⁺ layer penetrates inward by about 0.2 μm from both ends of the mask material, and photo CVD or SiN is deposited by 0.3 μm. , The gate length can be made extremely small, and there is an effect that the gate metal does not have to come into contact with the n ⁺ region. Therefore, V _B obtained the source and the gate can be very high and 10～14V.

The length of the dummy gate insulating film usually varies by about ± 0.2 μm depending on dry etching conditions, photoresist length forming conditions and the like.

Photo-CVD is extremely slow in insulating film deposition rate (up to 3 nm / min)
Therefore, after the dummy gate length is measured, the deposited film thickness can be adjusted so that a desired gate electrode length can be realized.

 The present invention can also be applied to 2DEG-FET.

(Embodiment 5) GaAs MES when the present invention is implemented by using a single insulating film.
An example of making a FET is shown in FIG.

After forming 700 nm of CVD SiO ₂ 122 on the active layer 110, a gate photoresist 124 is formed. SiO ₂ is removed by dry processing, and Si ions 125 are implanted. After removing to photoresist S
iN127 is deposited to 200 nm and annealed. Similar to the fourth embodiment, the source / drain electrodes 130 and 131 are deposited on the dummy gate 122, the photoresist 126 is embedded by the planarization process, the SiO ₂ 122 is removed, and then the photo-CVD SiN is deposited. FIG. 7 (d)).

Subsequently, Ti / Pt / Au was vapor-deposited as the gate metal, but Al, Mo / Au or the like may be used for vapor deposition lift-off.

(Embodiment 6) FIG. 8 shows an embodiment in which the present invention is applied to formation of an emitter region and a base region of an npn type HBT (heterojunction bipolar transistor).

Semi-insulating GaA using MBE (Molecular Beam Epitaxy)
n ⁺ type GaAs151, n ⁻ type GaAs152 (collector region) p ⁺ GaAs153 (base region), n type AlGaAs154 (emitter region), n type GaAs155, n ⁺ type GaAs156 (cap region) on the s substrate 150
Were formed respectively. The film thickness and doping level are known specifications.

An emitter region is formed using the dummy gate insulating film 157 of Examples 3-5. Insulating film for forming this emitter region
The n ⁺ type GaAs cap layer 156 is removed by etching using 157 as a mask. Implanting Mg ions 158 under a condition of a dose amount of 175 keV 7 × 10 ¹⁴ cm ^-2 using the insulating film 57 for forming the emitter region as a mask material (SiO ₂ is deposited to 200 nm, and lamp annealing is performed at 1000 ° C. for 10 seconds. Activated Mg ion 158.

The method of Example 3 or 4 was used for forming the base electrode and the emitter electrode. However, AuZn was used as the base electrode material and AuGe / Ni / Au was used as the emitter electrode material.

A usual method was used for separating the collector electrode forming elements.

In the present embodiment, the case where the present invention is applied to the npn type HBT is shown, but it is also applicable to the pnp type HBT. In that case, Si ion implantation is used to form the base region. AuGe / Ni / Au is used for the base electrode and AuZn is used for the emitter electrode.

Also, a pnp-type HBT that uses a two-dimensional electron gas formed at the interface between n-type AlGaAs and undoped GaAs as a base layer.
The present invention is also applicable to (called 2DEG-HBT).

In this case, a dummy insulating film for forming the emitter region is used,
After removing GaAs or AlGaAs in the p-type region, SiO ₂ was deposited to a thickness of 50 nm, Si was injected at a dose of 175 keV 5 × 10 ¹³ cm ^-2 , and activated by lamp annealing. At this time, the sheet resistance of the ion-implanted n-type base region was 70Ω / □.

〔The invention's effect〕

According to the first aspect of the present invention, since the step coverage is excellent and the extremely thin insulating film can be formed on the patterned photoresist, (1) the process steps are simplified, and the source / gate or emitter -The bases can be electrically separated very stably.

(2) When applied to a field effect transistor, a FET
The source gate resistance Rsg of can be significantly reduced. When applied to a heterojunction bipolar transistor, the base resistance
r _nn a can be significantly reduced.

According to the second invention, the n ⁺ or p ⁺ region can be formed by using the dummy gate (or emitter) insulating film as a mask. After the photoresist is buried and planarized, the dummy insulating film is removed and a photoresist such as photo-CVD is used. Since the gate metal or the emitter metal is deposited after depositing the insulating film which is not deformed on the side wall, (1) When applied to the FET, the n ⁺ region or the source / drain metal and the gate metal are not in contact with each other. ,
Since it can be formed extremely close to (~ 0.1μm),
Gate-to-gate parasitic resistance Rsg can be minimized.

In addition, since an insulating film having a very slow deposition rate (up to 3 nm / min) such as photo-CVD is used, the gate length can be controlled with excellent controllability.

(2) When applied to the HBT, a low sheet resistance of the n ⁺ or p ⁺ side base region can be realized, and the n ⁺ (or p ⁺ ) region or the base electrode and the emitter region are extremely close (up to 0.1 μm).
m) and the base resistance can be extremely reduced.

[Brief description of drawings]

FIG. 1 is a principle diagram for explaining the first invention, FIGS. 2 and 3 are cross-sectional structural views when the first invention is applied to a 2DEG-FET and an HBT, and FIG. 4 is a second structure diagram. FIG. 5 is a process diagram showing the principle of the invention, FIG. 5 is a sectional structure diagram of a conventional FET, FIGS. 6 and 7 are main process diagrams when the second invention is applied to the FET, and FIG.
FIG. 3 is a main cross-sectional structure diagram when the second invention is applied to formation of an emitter and base region of a pn type HBT. 1 ... Emitter or gate region, 4 ... Photo CVD insulating film, 2 ... Photoresist, 5 ... Electrode metal, 3 ... Semiconductor, 13,55 ... N-type AlGaAs, 12 ... Undoped AlGaAs, 1
1,51 …… Undoped GaAs, 10 …… Semi-insulating GaAs substrate, 54
…… p ⁺ GaAs, 53,14 …… n ^- GaAs, 52,57 …… n ⁺ GaAs, 56…
… NGaAs, 124 …… Gate Emitter photoresist, 121,
122,123 ... Insulating film, 110 ... Semiconductor layer, 126 ... Buried photoresist, 113 ... Photo CVD insulating film, 114 ... Gate electrode, 130, 131 ... Source / drain electrode, 125 ... Si ion, 158 ... Mg Ion, 154 …… p ⁺ GaAs, 156 …… n ⁺ GaA
s, 155 ... n-type GaAs, 152 ... n ^- GaAs, 151 ... n ⁺ GaAs.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/417 29/73 29/778 29/812 H01L 29/72 29/205 29/50 J ( 56) References JP-A-55-82469 (JP, A) JP-A-59-12787 (JP, A) JP-A-61-6871 (JP, A)

Claims (1)

[Claims] 1. A step of forming a first area body and a patterned photoresist film on the first area body on a semiconductor substrate, and the semiconductor substrate, the first area body and the photoresist film. Is coated with an insulating film by photo-CVD, and the insulating film is dry-etched to expose the upper surface of the photoresist film and the semiconductor substrate, and the insulating film on the side wall of the first region body is left. And a step of depositing a metal film on the exposed portion of the photoresist film and the semiconductor substrate, and a step of removing the photoresist film to remove the metal film deposited on the photoresist film. And a method for manufacturing a semiconductor device.