JPH03211839A - Compound semiconductor device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: To make it possible to manufacture a compound semiconductor element of a new structure wherein cap layers are provided in such a way that they are brought into contact directly with a two-dimensional electronic layer and the source resistance of an HEMT is decreased. CONSTITUTION: Source and drain electrodes 21 and 23 are each formed on the upper part of each N<-> GaAs cap layer 19 and a control electrode, that is, a gate electrode 25, which Schottky contacts with an N<-> AlGaAs source layer 17, is formed on the exposed surface of this source layer 17. In a high electron mobility transistor (MEMT) of this structure, when a voltage is applied to the electrode 25, a donor in the layer 17 is ionized to generate two-dimensional electrons and these generated two-dimensional electrons move at high speed without scattering due to impurities through a channel, which is formed in the surface of an N<-> GaAs buffer layer 13 by a voltage difference between the electrodes 21 and 23. Thereby, a source resistance of the HEMT is decreased and the enhancement of the transfer conductance of the HEMT is contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a compound semiconductor device and a method for manufacturing the same, and particularly to a compound semiconductor device having a heterojunction structure and having high electron transfer characteristics, and a method for manufacturing the same.

In recent years, as the information and communication society has rapidly developed, the need for ultra-high speed combi coaters, ultra-high frequencies, and optical communications is increasing. However, existing devices using 81 have limitations in meeting these needs, and therefore, research into compound semiconductors with excellent material properties is being actively conducted. Among the compound semiconductors, GaA
s is high electron mobility ()light Electron M
Since it has properties such as high electron velocity, semi-insulating property, and properties, it has properties such as high-speed operation, high frequency, low noise, and low power consumption compared to Sl.

Therefore, research is actively underway to fabricate low-noise monolithic microwave ICs and ultra-high-speed, low-power digital ICs by utilizing the excellent material properties of GaAs.

Among the elements, a high electron mobility transistor (HighEl
ectron Mobility Transistor
r; F (hereinafter referred to as EMT) operates by electric field effect using modulated electrons, and has low noise, high frequency, and high speed characteristics. That is, the HEMT is N-GaA
It has a structure in which a thin film of an s layer, an MGaAs layer, and a N″AI GaAs layer are continuously grown, and the N″M
The current source electrons generated in the GaAs source layer are not present together with ionized donors or impurities, and the N-GaAs buffer layer and the Ai Ga
It is formed at a high concentration between the As spacer layer and operated by the electric field effect. Said N″AI Ga As
Si is generally used as a doping material for the source layer.

The low noise and high frequency characteristics of the HEMT improve as the transconductance g increases. However, since the front S self transconductance increases as the source resistance is reduced, it is important to reduce the source resistance.

Figure 1 is a vertical cross-sectional view showing the structure of a typical HEMT.
This structure will be explained.

An N-GaAs buffer layer 2, an A'GaAs spacer layer 3 and an N''A17 are formed on the entire surface of the semi-insulating GaAs substrate 1.
A GaAs 7-layer 4 is laminated thereon. Before and N″Ai
i! A gate electrode 8 is formed on a predetermined portion of the exposed surface of the Ga As source layer 4, and a gate electrode 8 is formed on the upper part of the Ga As source layer 4 excluding the predetermined portion.
A "GaAsGaAs cap layer 5-" and a drain electrode 6, 7 are formed.The source and drain electrodes 6, 7 are in contact with the N"GaAsGaAs cap layer to generate four N"GaAsGaAs source layers. .

Also, the above Ai? GaAS spacer layer 3 is N′″AlG
The N-GaAs buffer layer 2 serves to increase the mobility of the two-dimensional electrons generated in the aAs7-S N4, and the N-GaAs buffer layer 2 allows the two-dimensional electrons to form an interfacial potential well.
Used in active layers that are restricted to run. but,
The general HEMT shown in Figure 1 is N″A1G a
As source layer 4, AffGaAs spacer layer 3 and N
- the barrier resistance between the GaAs buffer layer 2 and the M,
G a As spacer layer 3 and N″AI G a A
There is a problem in that the source resistance consisting of the bulk resistance of the s source layer 4 deteriorates low noise and high frequency characteristics.

HEMTs in which ions are implanted to reduce the problem described above, ie, source resistance, are known.

FIG. 2 is a vertical cross-sectional view showing the structure of a HEMT using conventional ion implantation. The structure of FIG. 2 is the structure of FIG. 1 with more ion implantation regions 9 formed, and the same reference numerals indicate the same structures and parts.

The construction method of the HEMT will be briefly explained.

Molecular beam epitaxy is performed on the surface of the semi-insulating GaAs substrate 1.
; hereinafter referred to as MBE) method or metal-organic chemical vapor deposition (MBE) method;
etal Organic Chemical Vapo
r Deposition (hereinafter referred to as MOCVO) method, the N-GaAs buffer layer 2, A1. GaAs
Spacer layer 3, N'''AI Ga As source layer 4
and N'' GaAs cap layer 5 are sequentially formed.

After that, excluding the gate region, ions of impurities such as 81 are implanted to a depth of a part of the buffer layer 2, and an ion implantation region 9 is formed through an annealing process. Then, the N″
Source and drain electrodes 6.7 are formed on the surface of the GaAs cap layer 50. After the above step, the predetermined portions of N゛GaAsGaAs where the ion implantation region 9 was not formed are
After removing through the cap layer 5,
Source layer 4 is exposed and gate electrode 8 is formed.

H E M T IiN″Ga formed as above
As cap layer and N″AlG below this cap layer
The source resistance is reduced by the ion implant regions formed in the a As source layer, the AI Ga As spacer layer, and a portion of the N-GaAs layer. The annealing process brings the ionized donors of the NAI Ga As source layer into contact with the Idl Ga As spacer layer and the N-
Since electron mobility is reduced by being diffused into the two-dimensional electron layer formed at high concentration between the GaAs buffer layer and the GaAs buffer layer, there is a problem that low noise and high frequency characteristics are deteriorated.

Therefore, a first object of the present invention is to develop a new structure that can reduce the source resistance by bringing the cap layer into direct contact with the two-dimensional electronic layer, in order to solve the problems of the prior art as described above. An object of the present invention is to provide a compound semiconductor device.

Further, a second object of the present invention is to provide a method for manufacturing a compound semiconductor device as described above.

In order to achieve the above first object, the present invention provides a semi-insulating compound semiconductor substrate; a buffer layer of a first conductivity type formed of a compound semiconductor of the same type as that of the substrate; A first conduction type first and a second conduction type semiconductor layer are formed of a compound semiconductor of the same type as the buffer layer and are separated at a constant interval from each other.
a cap layer; first and second current electrodes forming ohmic contact with the cap layer on each of the first and second cap layers; a buffer layer on the buffer layer between the first and second cap layers; a spacer layer formed of a compound semiconductor different from the spacer layer; a first conductivity type source layer formed of a compound semiconductor of the same type as the spacer layer on the spacer layer; It is characterized in that it comprises a discount electrode forming a contact.

In addition, in order to achieve the above-mentioned second object, the present invention provides a method for manufacturing a compound semiconductor device in which a two-dimensional electron layer is formed in an interfacial potential well at the interface between different types of compound semiconductor layers due to the affinity difference between these materials. A step of crystal-growing a buffer layer made of the same type of compound semiconductor on a semi-insulating compound semiconductor substrate; a space layer and a first conductivity type source layer made of a compound semiconductor different from the buffer layer on the buffer layer; Sequential crystal growth; etching to form a mesa structure to a partial depth of the space layer and source layer and the buffer layer; depositing the buffer layer on the mesa structure and the exposed buffer layer; A step of crystal-growing a cap layer of a first conductivity type which is a compound semiconductor of the same type as that of the mesa structure; a step of forming first and second current electrodes on the cap layer on the left and right sides of the mesa structure; etching the cap layer to form an opening for exposing the top surface; and forming a control electrode on the source layer exposed in the opening so as to be isolated from the cap layer. It is characterized by

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a vertical cross-sectional view of a HEMT according to the present invention.

In FIG. 3, NGa is deposited on a semi-insulating GaAs substrate 11.
As buffer layer 13 is formed by crystal growth.

The N-GaAs buffer layer 13 is formed in a mesa (MeSa) structure with a predetermined portion protruding. Said NG
M G a on the surface of the protruding portion of the aAs buffer layer 13
As spacer layer 15 and N-AlGaAs source layer 1
7 is formed by crystal growth. N-GaAs cap layers 19 are formed on the buffer layers 13 on the left and right sides of the mesa structure.

Further, the N-GaAs groove layer 19 is formed of the AlG
It is brought into contact with the side surface of the a As spacer layer 15 . First and second current polarity, ie, source and drain electrodes 21.23 are formed on top of each N-GaAs cap layer 19 and are in ohmic contact with the N-GaAs cap layer 19.
A control or gate electrode 25 is formed on the exposed surface of GaAs source layer 17 and makes Schottky contact with the source layer.

In the HEMT having the above-described structure, when a voltage is applied to the gate electrode 25, the donors in the N-AlGaAs source layer 17 are ionized and two-dimensional electrons are generated, and the generated two-dimensional electrons are transferred to the AI GaAs spacer layer 15. and N-
Since a highly concentrated two-dimensional electron layer is formed at the interface of the GaAs buffer layer 13, the source electrode 21 and the drain electrode 23
N-GaAs buffer layer 130 due to the voltage difference between
Two-dimensional electrons can be moved at high speed through channels formed on the surface without being scattered by impurities. Also, N-
Since the A3GaAs source layer 17 and the MGaAs spacer layer 15 are confined only to the gate region, only the N''GaAs cap layer 19 is formed under the source and drain electrodes 21.23, and this cap layer 19 and The two-dimensional electronic layer is brought into direct contact. Therefore, the N″AI Ga A of the prior art (see FIGS. 1 and 2)
s source layer, AI Ga As spacer layer and N-G
The barrier resistance due to discontinuity in the conduction band between the N-AffGaAs layer and the Ai'GaAs layer and the
Since the resistance of the As spacer layer itself disappears, the source resistance is reduced. Therefore, the transfer conductance of the HEMT can be improved and the threshold voltage can be lowered.

48-C are cross-sectional views showing the manufacturing process of FIG. 3 described above.

Referring to FIG. 4A, an N-GaAs layer with an impurity concentration of 1Xl0I4/ctl or less and a thickness of Q, 5 to 2 μm is formed on a semi-insulating GaAs substrate 11, and an N-GaAs layer with a thickness of 30 to 1 μm is formed on a semi-insulating GaAs substrate 11.
00 MI Ga As layer and impurity concentration I
XIO" ~ 3 XIO"/cd, thickness 3QO
~500 A'N''A'GaAs layer by MBE or M
The layers are formed sequentially by OCVD. At this time, the impurity is S! Take advantage of. After that, to form a mesa pattern in a predetermined area, N''M
The GaAs layer and the AIGaAs layer are sequentially etched to form the N'' AlGaAs source layer 17 and the AlGa^S spacer layer 15. At this time, the etching is performed in parallel using a dry or wet method. The GaAs layer is also etched to a predetermined thickness to form an N-GaAs buffer layer 13.
N-GaAs/77 layer 13 is made of AI GaAs
It is formed to protrude from the bottom of the spacer layer 15 so that a source-drain current path can be easily formed.

Referring to FIG. 4B, on the exposed N-GaAs buffer layer 13 and the N''/Ij7GaAs source layer 17, a N''GaAs layer with a thickness of approximately 3 μm is formed, the surface of which may be planarized by the aforementioned MBE or MOCVD method. form a layer. Then, the N''AI! layer is deposited on the surface of the N''GaAs layer by a lift-off method. G
Source and drain electrodes 21 and 23 are formed on the remaining portions of the aAs 7-layer 17 with the upper portion removed. The source and drain electrodes 21 and 23 are ohmic.
It is made of metal, for example AuGe/Ni/^U. Continuing with the N″MGaAsMGaAs source layer N″GaA
The opening 24 is formed by removing the s cap layer 19 by a photo process.
form.

Next, a gate electrode 25 is formed on the exposed N''AI Ga As source layer 17, resulting in a structure as shown in FIG. 4C. At this time, the gate electrode 25 is made of Schottky metal, for example, Ti/Pt. /Au.

As described above, the N'''/Ij7GaAs source layer and AlGaAs spacer layer are formed only in the gate region, and the N''GaAsGaAs spacer layer is formed in the source and drain regions.
By forming the cap layer on the aAs buffer layer so that the cap layer is in direct contact with the two-dimensional electronic layer formed on the surface of the buffer layer, the source resistance can be reduced, thereby improving low noise and high frequency characteristics. There are advantages.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional general gallium arsenide high electron mobility transistor, Figure 2 is a cross-sectional view of a conventional gallium arsenide high electron mobility transistor by ion implantation, and Figure 3 is a gallium arsenide high electron mobility transistor according to the present invention. A cross-sectional view of the transistor, FIGS. 4A-4C, is a process sequence diagram showing the manufacturing process of the gallium arsenide high electron mobility transistor of FIG. 3. 11; Semi-insulating GaAs substrate 13: N-GaAs bar''/77 layer 15: AlGaAs spacer H 17: N''#GaAs 7-layer 19: N'' GaAs cap layer 21. 23: Source and drain electrodes 24: Opening 25: Gate electrode

Claims (1)

[Claims] 1. A semi-insulating compound semiconductor substrate; A buffer layer of a first conductivity type formed of the same type of compound semiconductor as the substrate on the substrate; first and second cap layers of a first conductivity type formed of the same type of compound semiconductor as the buffer layer; a first cap layer forming ohmic contact with the cap layer in each of the first and second cap layers; first and second current electrodes; a spacer layer formed of a compound semiconductor different from the buffer layer on the buffer layer between the first and second cap layers; a spacer layer formed of a compound semiconductor of the same type as this spacer layer on the spacer layer; A compound semiconductor device comprising: a first conductivity type source layer made of a compound semiconductor; and a control electrode formed on the source layer to form a Schottky contact with the source layer. 2. The compound semiconductor device according to claim 1, wherein the substrate is a GaAs compound semiconductor, and the spacer layer is an AlGaAs compound semiconductor. 3. The compound semiconductor device according to claim 2, wherein the first conductivity type is an N type. 4. The compound semiconductor device according to claim 1, wherein the spacer layer and the source layer are formed in a mesa structure on the buffer layer. 5. The first and second cap layers are formed to cover the inclined side surfaces of the mesa structure.
The compound semiconductor device described in . 6. In a method for manufacturing a compound semiconductor device in which a two-dimensional electron layer is formed in an interfacial potential well due to the difference in the affinity of these substances at the interface between compound semiconductor layers of different types, A step of crystal-growing a buffer layer made of a compound semiconductor; A step of sequentially growing a space layer and a source layer of a first conductivity type on the buffer layer, which are made of a compound semiconductor different from the buffer layer; The space layer and the source layer,
and etching to form a mesa structure to a partial depth of the buffer layer; forming a cap layer of a first conductivity type, which is a compound semiconductor of the same type as the buffer layer, on the mesa structure and the exposed buffer layer; growing a crystal; forming first and second current electrodes on the cap layer on the left and right sides of the mesa structure; forming an opening on the cap layer to expose the top surface of the mesa structure; and forming a control electrode on the source layer exposed in the opening so as to be isolated from the cap layer. 7. The method of manufacturing a compound semiconductor device according to claim 6, wherein the substrate is a GaAs compound semiconductor, and the space layer is an AlGaAs compound semiconductor. 8. The method for manufacturing a compound semiconductor device according to claim 7, wherein the first conductivity type is N type. 9. The method of manufacturing a compound semiconductor device according to claim 6, wherein the etching process for forming the mesa structure is a dry etching process or a wet etching process.