JPH05198601A - Field-effect transistor and its production - Google Patents

Abstract

PURPOSE:To improve the reproducibility of drain resistance (Rd) and improve the inverse voltage resistance of a high concentration activating layer (n<+> layer) by using a field-effect transistor which has an inclined gate electrode. CONSTITUTION:A source electrode 26a, a drain electrode 26b and an insulating film 18 are accumulated on an (n)-type activating layer 12 and an (n)-type activating layer 14. The layers 12 and 14 are formed on a semiconductor substrate 10 so as to run on the insulating film 18a. The GaAs FET structure semiconductor element with the inclined gate electrode is used. The source electrode 26a, the drain electrode 26b and the insulating film 18 are masked by using a negative resist pattern 52. The (n)-type activating layer 12 and the (n<+>)-type layer 14 of the element is etched by using etching liquid. At that time, the recess length L11 of the activating layer on the source side is not changed, whereas the recess length L12 on the drain side is changed and the thickness is reduced. Therefore, drain resistance (Rd) is increased, the recess is formed in the prescribed shape and high inverse voltage resistance and the highly accurate shape are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and its manufacturing method.

[0002]

2. Description of the Related Art A method has been proposed in which a recess is provided in a substrate and an inclined gate electrode is formed in the recess by using an oblique evaporation method. GaAsF as a typical example
A method of manufacturing ET will be described. 3 to 5 are manufacturing process diagrams of a GaAs FET using a SiN insulating film. First, an n ⁺ -type active layer 14 having a donor concentration one order higher than that of the n layer is formed on the GaAs substrate 10 by using the epitaxy technique.
000 A ° (A ° is a symbol representing angstrom), and then the n-type active layer 12 is formed to a film thickness of 1000 A ° ((A) of FIG. 3). Normally, AlGaAs is used as the material for these active layers.

Next, an insulating film 18 made of SiN is formed to a thickness of 1000 A ° on the n ⁺ type active layer by using the CVD method (FIG. 3B). The active layer 16 having a two-layer structure is obtained by the both active layers.

Next, a negative resist pattern having an opening 22 in a region portion of the insulating film 18 for forming two ohmic electrodes as a source electrode and a drain electrode is formed by using a photographic technique (FIG. 3). (C)).

Next, a negative resist 20 having an opening 22 at a position where an electrode is to be formed by using a dry etching method.
Is used as a mask to etch the SiN film 18 (FIG. 4A).

Subsequently, after depositing a metal film by a vacuum evaporation method, the Au electrode systems 26a and 26b are formed at positions separated from each other on the n ⁺ active layer 14 by using a lift-off method. Subsequently, heat treatment is performed at about 300 ° C. to 400 ° C. to remove the Au-based electrodes 26 a and 26 b and the n-type active layer 14.
The alloying reaction with and changes to a state in which ohmic electrical characteristics are obtained ((B) of FIG. 4). Therefore, the Au-based electrodes 26a and 26b become ohmic electrodes.

Next, the SiN film 18 is etched by using the dry etching method similarly to the formation of the ohmic electrodes, so that the two ohmic electrodes 26a and 26a are formed.
The gate opening 30 is formed in the gate electrode formation portion between b (FIG. 5A).

Therefore, the ohmic electrodes 26a, 26b
After the negative resist is once provided on the entire surface of the side, the gate opening 28 is formed by the photolithography technique. This negative resist pattern is shown at 29.

Next, dry etching is performed using the resist pattern 29 having the gate opening 28 formed therein as a mask to form the gate opening 30 (FIG. 5A).

Next, using the SiN film 18 in which the gate opening 30 is formed and the resist pattern 29 as a mask, the n ⁺ type layer 14 and the active layer 16 of the two-layer structure are formed by a wet etching method or a dry etching method. n
The mold layer 12 is sequentially etched. Since the recess 32 is formed in the active layer 16 by this etching, it is called recess etching. When this recess portion is formed, the etching depth of the n-type layer 12 is determined by the etching time so that the FET characteristics of the completed element will be the characteristics as designed.

Next, as in the case of the ohmic electrode, the gate opening 3 is formed by using the vacuum evaporation method and the lift-off method.
The Al-based gate electrode 34 is formed using the SiN film 18 having 0 as a mask ((C) of FIG. 5).

At this time, the vapor deposition is tilted by about 10 ° C. to 20 ° C. from the direction perpendicular to the substrate surface to set the vapor deposition incident angle so that it is offset to one side, that is, the source electrode 26a side and the gate electrode 34 is inclined. It is formed ((C) of FIG. 5).

This gate electrode 34 is called an offset gate. Further, the offset gate 34 has the gate opening 3
It has a shape of riding on the portion 18a of the SiN film 18 on the source electrode side of 0. The portion of the SiN film 18 on the drain electrode side is indicated by 18b.

[0014]

However, in the conventional GaAsFET manufacturing process, the active layer 1 is formed by the epitaxy method.
6 is formed, it is difficult to obtain an active layer that gives stable FET characteristics. It is stable because the source resistance (the series resistance located on the source side that is not changed by the gate bias) that causes the fluctuation of the FET characteristics is determined in a self-aligned manner, but the drain resistance (the series located on the drain side is This is because the resistance component) varies depending on the Schottky length and the recess length. It was difficult to form this drain resistance with good reproducibility by the conventional method.

The shorter the recess length, the shorter the distance between the drain and gate, and the resistance of the n-type layer active layer is reduced by the shorter recess length. Therefore, the reverse breakdown voltage in the FET characteristics is reduced. was there.

The object of the present invention is (1) drain resistance (R
to improve the reproducibility of (d) (2) high-concentration active layer (n ⁺
It is to improve the reduction of reverse breakdown voltage in the mold layer).

[0017]

To achieve this object, according to the FET of the present invention, an active layer having a multilayer structure is provided on a semiconductor substrate, and an insulating film, a source electrode and a drain electrode are provided on the active layer. In a field effect transistor in which a recess is provided in the active layer between the source electrode and the drain electrode, a recessed gate electrode is provided, the recess is formed as continuous shallow and deep recesses having different depths. The recess is formed on the source side, the deep recess is formed on the drain electrode side described above, and the gate electrode described above is formed on the shallow recess described above and a part of the gate electrode is formed on the insulating film part described above on the source electrode side. It is characterized in that it is formed as an inclined gate electrode so as to ride up.

Further, according to the method of manufacturing a semiconductor element of the present invention, a step of forming a gate electrode on the side of the recess closer to the source electrode by using an oblique evaporation technique, and the gate electrode and the insulating film are resistant to etching. And a step of etching a portion of the recess, which is not covered by the gate electrode, as a mask.

[0019]

According to the method of manufacturing a semiconductor device of the present invention and the semiconductor device manufactured by this method, the recess length is determined in a self-aligned manner because the gate electrode is mounted on the insulating film. Therefore, the source resistance (Rs) is reduced,
The conventional advantage of obtaining high conductance can be retained.

The recess portion is formed by selectively etching a source electrode side, a shallow recess where the gate electrode is formed, and a deep recess where the gate electrode on the drain electrode side is not formed. .. Therefore, of the active layer, the film thickness is reduced and the recess-side active layer on the drain side is reduced. Therefore, the surface resistance in the mesa direction, that is, the drain resistance (Rd) is Rd = ρ / d (where d: thickness,
ρ: specific resistance of the n layer), the high reverse withstand voltage can be obtained.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor device and the method of manufacturing the same according to the present invention will be described below with reference to FIGS. 1 and 2A to 2B and FIG. In the examples described below, the active layer follows the conventional example,
A GaAsaFET formed by the epitaxial method will be described as an example. It should be understood that the embodiment described here is merely a preferred example, and the present invention is not limited to this embodiment.

Further, the drawings referred to below only schematically show the shapes, sizes, and arrangement relationships of the respective constituents to the extent that the present invention can be understood.

In the following description, the process is the same as the conventional process until the recessed portion is formed by the etching method and the gate offset electrode is formed. Therefore, the description thereof will be omitted and the constituent components already described will be omitted. Similar components are designated by the same reference numerals.

FIG. 6 shows an essential part of a structure corresponding to the structure shown in FIG. 5C, which is formed through the conventional process.
In this structure, the source-gate distance is indicated by L ₁₁ , and the drain-gate distance is indicated by L ₁₂ . The film thickness of the recess 32 of the active layer 16 is t ₂₀ .
The FET characteristics of the semiconductor element shown in FIG. 6 are measured by a normal method using a DC prober, a curve tracer, etc.
s) and drain resistance (Rd) are measured.

At this time, when the drain resistance (Rd) is smaller than the set value or when the reverse breakdown voltage is low, the gate electrode 34 and the insulating films 18a and 18b are used as etching resistant masks to expose the active layer 12. The etched part is etched. Therefore, first, a negative resist pattern 52 having an opening 50 is formed on the uppermost source electrode 26a, drain electrode 26b, and insulating films (SiN films) 18a and 18b on the GaAs substrate 10 by using the photolithography technique. .. This opening 50 is formed by the gate electrode 34,
So as to be located between the source electrode 26a and the drain electrode 26b so that at least the recess portion 32 is exposed,
It is provided. In other words, the negative resist pattern 52 may be provided so as to cover the source electrode 26a and the drain electrode 26b. A state in which the resist pattern 52 is provided is shown in FIG.

Next, only the exposed portion of the recess 32 is selectively wet-etched. This etching is
The recess depth is set so that the difference between the initial set value and the characteristic value measured by the structure of FIG. 6 can be supplemented. The recessed portion having a two-stage structure formed in this way is indicated by 60, the recessed portion which remains without being etched is referred to as a shallow recessed portion, and the recessed portion formed by etching is referred to as a deep recessed portion. It is represented by 64 ((B) of FIG. 2). Note that these shallow and deep recesses 62 and 6
The etching solution used in the process of forming 4 is an acid type. By immersing in the etching solution, the active layer 16 between the gate and the source is not exposed because the gate electrode 34 rides on the insulating film (SiN film) 18a. Since the portion of the active layer 16 between them does not penetrate, this active layer portion is not etched and remains as a shallow recess, and thus the active layer 16 also remains as the thickness t ₂₀ .

On the other hand, since the portion of the active layer 16 between the gate and the drain is exposed as described above, the etching solution permeates into this active layer portion and the n-type layer 12
And the n ⁺ type layer 14 is etched. Therefore, a new gate-drain distance L ₁₃ is formed. Then, it shows the thickness of the active layer that remained after the formation of the deep recess 64 in the t _21.

By repeating the above process, the drain resistance value (Rd) of the initial set value can be obtained. In the present invention, the selective etching is performed by the wet etching method, but it goes without saying that the dry etching method can be performed by the same process.

Further, even if the shape of the recess portion is not an inverted trapezoid, for example, even if it is rectangular or circular, the drain resistance Rd initially set can be easily obtained.

When the initially set drain resistance (Rd) is obtained, the negative resist 52 is removed with an organic solvent (eg, acetone) or the like, and the process is completed. The finally obtained FET structure is shown in FIG.

According to the structure shown in FIG. 1, the active layer 16 having a two-layer structure is provided on the GaAs substrate 10. The active layer 16 is provided with insulating films 18a and 18b, a source electrode 26a and a drain electrode 26b. Further, a recess 60 having a two-step structure is provided in the active layer 16 between the source electrode 26a and the drain electrode 26b. This recess 60 has a shallow recess 62 and a deep recess 64.
And are formed in a continuous form. The shallow recess 62 is provided on the source electrode 26a side, and the inclined gate electrode 34 is formed on the upper side thereof. A part of the gate electrode 34 is formed on the insulating film 18a on the source electrode side. Further, in this embodiment, the shallow recess 62 and the deep recess 64 are both formed up to the n-type layer 12 on the side of the active layer 16 where the impurity concentration is low.

The invention is not limited to the embodiments described above, but many variants or modifications can be made. For example, although the SiN film is used as the etching mask used for the recess in this embodiment, not only the SiN film but also an insulating material such as SiO ₂ having etching resistance, a resist having good adhesion to a semiconductor, or a polyimide may be used. Good.

Further, in the above-mentioned embodiment, GaAs FET
However, if the gate electrode is provided in the recess, other III-V group, II-VI group compound semiconductors and Si
The present invention can be applied to FETs made of elemental semiconductors such as.

[0034]

As is apparent from the above description, according to the field effect transistor and the method of manufacturing the same of the present invention, the following effects can be obtained.

By selectively etching the active layer after forming the FET, the active layer becomes asymmetric with respect to the gate electrode, and the source resistance (Rs) is small, so that the mutual inductance is high and the drain resistance (Rd) is large. Therefore, a high reverse voltage can be obtained.

Further, since the drain resistance (Rd) can be adjusted after the gate electrode is formed, a drain resistance that matches the design value can be obtained, the degree of freedom in designing the FET is increased, and the FET can be formed with good reproducibility, so that the yield is improved. It can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the structure of a field effect transistor of the present invention.

2 (A) and 2 (B) are process drawings for explaining a method for manufacturing a field effect transistor of the present invention.

3 (A) to (C) are process diagrams of the first half for explaining a conventional method for manufacturing a GaAs FET.

FIG. 4A to FIG. 4C are process diagrams of the latter half of FIG. 2, following FIG.

5A to 5C are process diagrams of the latter half of FIG. 3 following FIG.

FIG. 6 is a sectional view schematically showing the structure of a conventional GaAs FET.

[Explanation of symbols]

10: semiconductor substrate (GaAs) 12: n-type layer 14: n ⁺ type layer 16: two-layer active layer 18a, 18b: insulating film (SiN film) 26a: source electrode 26b: drain electrode 34: gate electrode 50: Opening 52: Negative resist pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/12 8728-4M 29/46 H 7738-4M

Claims (2)

[Claims] 1. A semiconductor substrate comprising an active layer having a multi-layer structure, an insulating film, a source electrode and a drain electrode provided on the active layer, and a recess formed in the active layer between the source electrode and the drain electrode. In the field effect transistor having a structure in which the gate electrode is provided, the recess is formed by a continuous shallow recess and a deep recess, and the shallow recess is provided on the source electrode side and the deep recess is provided on the drain side. A field effect transistor, wherein the gate electrode is provided on the shallow recess as a tilted gate electrode, a portion of which extends over the insulating film portion on the source electrode side. 2. The method for manufacturing a field effect transistor according to claim 1, wherein: (a) a step of forming the gate electrode on the side of the recess, which is closer to the source electrode, using an oblique evaporation technique; b) a step of using the gate electrode and the insulating film as an etching resistant mask to etch a portion of the recess which is not covered with the gate electrode, and manufacturing the field effect transistor.