JPH02113539A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02113539A JPH02113539A JP26651388A JP26651388A JPH02113539A JP H02113539 A JPH02113539 A JP H02113539A JP 26651388 A JP26651388 A JP 26651388A JP 26651388 A JP26651388 A JP 26651388A JP H02113539 A JPH02113539 A JP H02113539A
- Authority
- JP
- Japan
- Prior art keywords
- high concentration
- gate electrode
- layer
- concentration layer
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000013459 approach Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 230000005669 field effect Effects 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- -1 silicon ions Chemical class 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に電界効果
型トランジスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a field effect transistor.
従来の電界効果型トランジスタの製造方法を第３図によ
って説明する。半導体基板１にイオン注入により能動層
１２を第３図（ａ）のように形成した後、第３図（ｂ）
のようにショットキー特性を有するゲート電極１３を形
成する。その後、ゲート電極１３をマスクとして自己整
合的にイオン注入によりコンタクト層１４を第３図（Ｃ
）のように形成し、能動層１２．コンタクト層１４の活
性化を行なう。さらに自己整合的にゲート電極１３の側
壁に絶縁膜１５を形成した後、ゲート電極１３及び絶縁
膜１５以外のコンタクト層１４上にＭＯＣＶＤ法により
選択的に高濃度層１６を第３図（ｄ）のように成長させ
、高能動層１６にオーミック電極１７を形成し、第３図
（ｅ）のように電界効果型トランジスタを作製していた
。このような製造方法により、オーミック電極１７−能
動層１２−ゲート電極１３間の直列的な抵抗が下がり、
相互コンダクタンスの向上を図ることができ、高周波特
性及び高速動作性に優れた電界効果型トランジスタが得
られる。A conventional method for manufacturing a field effect transistor will be explained with reference to FIG. After forming the active layer 12 on the semiconductor substrate 1 by ion implantation as shown in FIG. 3(a), the active layer 12 is formed as shown in FIG. 3(b).
A gate electrode 13 having Schottky characteristics is formed as shown in FIG. Thereafter, the contact layer 14 is formed by ion implantation in a self-aligned manner using the gate electrode 13 as a mask as shown in FIG.
), and the active layer 12. The contact layer 14 is activated. Furthermore, after forming an insulating film 15 on the sidewalls of the gate electrode 13 in a self-aligned manner, a high concentration layer 16 is selectively formed on the contact layer 14 other than the gate electrode 13 and the insulating film 15 by MOCVD as shown in FIG. 3(d). An ohmic electrode 17 was formed on the highly active layer 16, and a field effect transistor was manufactured as shown in FIG. 3(e). With this manufacturing method, the series resistance between the ohmic electrode 17, the active layer 12, and the gate electrode 13 is reduced.
A field-effect transistor with improved mutual conductance and excellent high-frequency characteristics and high-speed operation can be obtained.
上述した従来の電界効果型トランジスタの製造方法は、
高濃度層がゲート近傍に設けられるので、能動層のうち
ソース１２″側ではソース抵抗を低減できる効果がある
が、このトランジスタを高周波回路等に用いた場合、高
周波の振幅に耐え得るゲート１３．ドレイン１２′間耐
圧を得られないという欠点がある。The conventional method of manufacturing the field-effect transistor described above is as follows:
Since the high concentration layer is provided near the gate, it has the effect of reducing the source resistance on the source 12'' side of the active layer, but when this transistor is used in a high frequency circuit etc., the gate 13. There is a drawback that a breakdown voltage between the drain 12' cannot be obtained.
本発明の電界効果型トランジスタの製造方法は、能動層
を有する半導体基板上にゲート電極を形成する工程と、
ゲート電極をマスクとしてコンタクト層を形成する工程
と、ゲート電極と自己整合的に隔てられたコンタクト層
上に高濃度層を形成する工程と、ドレイン側のゲート電
極近傍の高濃度層を薄くする工程と、高濃度層にオーミ
ック電極を形成する工程とを含むものである。このよう
な製造方法によりドレイン側の高濃度層をゲート電極近
傍のみ薄く形成し、ゲート・ドレイン間耐圧を向上させ
ることができる。A method for manufacturing a field effect transistor according to the present invention includes a step of forming a gate electrode on a semiconductor substrate having an active layer;
A process of forming a contact layer using the gate electrode as a mask, a process of forming a high concentration layer on the contact layer separated from the gate electrode in a self-aligned manner, and a process of thinning the high concentration layer near the gate electrode on the drain side. and a step of forming an ohmic electrode on the high concentration layer. By such a manufacturing method, the high concentration layer on the drain side can be formed thin only in the vicinity of the gate electrode, and the breakdown voltage between the gate and drain can be improved.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of a first embodiment of the invention.
第１図（ａ）に示すように、ガリウム砒素（ＧａＡｓ）
半導体基板１にシリコンイオンを注入し、能動層を形成
した後、能動層２上にゲート電極３を形成し、ゲート電
極３をマスクとして、シリコンイオンを注入して能動層
２に一部重なるように深くコンタクト層４を形成する。As shown in Figure 1(a), gallium arsenide (GaAs)
After silicon ions are implanted into the semiconductor substrate 1 to form an active layer, a gate electrode 3 is formed on the active layer 2, and using the gate electrode 3 as a mask, silicon ions are implanted so as to partially overlap the active layer 2. A contact layer 4 is formed deeply.
次に能動層２及びコンタクト層４の活性化を行なった後
、シリコン酸化膜５を基板１表面に１０００人程度堆積
し、ゲート電極３の側壁以外のコンタクト層４上のシリ
コン酸化膜５をエツチング除去し、第１図（ｂ）に示す
ようにゲート電極３及びシリコン酸化膜５をマスクとし
て、たとえば、１〜５×１０１６ＣＩ１１″″３程度の
キャリア濃度の高濃度層６をＭＯＣＶＤ法により３００
０人〜４０００人選択成長する。その後、第１図（ｃ）
に示すように、ゲート電極３上からドレイン側の高濃度
層６が一部露出するようにフォトレジストアを形成する
。そして、フォトレジスト７、ゲート電極３及びシリコ
ン酸化膜５をマスクとして高濃度層６を１００人〜５０
０人となるように等方性エツチングを行ない、第１図（
ｄ）に示すように高濃度層６上にオーミック電極を形成
する。このようにして本発明では、ソース２″側で高濃
度層がゲート電極に接近し、ドレイン２′側でゲート電
極近傍の高濃度層が薄く形成された電界効果型トランジ
スタを提供できる。Next, after activating the active layer 2 and the contact layer 4, a silicon oxide film 5 of about 1000 layers is deposited on the surface of the substrate 1, and the silicon oxide film 5 on the contact layer 4 other than the side walls of the gate electrode 3 is etched. As shown in FIG. 1(b), using the gate electrode 3 and silicon oxide film 5 as a mask, a highly concentrated layer 6 with a carrier concentration of, for example, 1 to 5×10 16 CI 11″″3 is formed by MOCVD at 300 nm.
Select and grow from 0 to 4000 people. After that, Fig. 1(c)
As shown in FIG. 3, a photoresist is formed so that a portion of the high concentration layer 6 on the drain side is exposed from above the gate electrode 3. Then, using the photoresist 7, the gate electrode 3, and the silicon oxide film 5 as a mask, the high concentration layer 6 is formed by 100 to 50 layers.
Isotropic etching was performed so that there were 0 people, and as shown in Figure 1 (
As shown in d), an ohmic electrode is formed on the high concentration layer 6. In this manner, the present invention can provide a field effect transistor in which the highly doped layer approaches the gate electrode on the source 2'' side, and the highly doped layer near the gate electrode is thinly formed on the drain 2' side.
第２図は本発明の第２の実施例の縦断面図である。実施
例１と同様に高濃度層６をゲート電極３とシリコン酸化
膜５をマスクとして、成長させた際、ゲート電極３の側
壁のシリコン酸化膜５と高濃度層６の間に、第２図（ａ
）のように隙間がある場合の実施例を示す。これは、高
濃度層６は、ＧａＡｓ半導体基板１の成長面と軸を同じ
くして成長するため、高濃度層６が必ずしもシリコン酸
化膜５に隣接して成長しないために起こるものである。FIG. 2 is a longitudinal sectional view of a second embodiment of the invention. When the high concentration layer 6 was grown using the gate electrode 3 and the silicon oxide film 5 as masks in the same manner as in Example 1, a layer 6 was formed between the silicon oxide film 5 on the side wall of the gate electrode 3 and the high concentration layer 6 as shown in FIG. (a
) shows an example in which there is a gap. This occurs because the high concentration layer 6 grows coaxially with the growth surface of the GaAs semiconductor substrate 1, so the high concentration layer 6 does not necessarily grow adjacent to the silicon oxide film 5.
この場合、高濃度層６成長後、第２のシリコン酸化膜を
堆積させ、ドライエツチングで第２図（ｂ）のようにエ
ッチバックし、隙間を第２のシリコン酸化膜９で埋込ん
だ後、第１の実施例と同様にドレイン側の高濃度層６を
薄くした後、第２図（Ｃ）のようにオーミック電極８を
形成する。この実施例では、隙間が第２のシリコン酸化
膜９で埋込まれているので高濃度層６をエツチングする
際、能動層及びコンタクト層がエツチングされないとい
う利点がある。In this case, after the high concentration layer 6 is grown, a second silicon oxide film is deposited, etched back by dry etching as shown in FIG. 2(b), and the gap is filled with a second silicon oxide film 9. After thinning the high concentration layer 6 on the drain side as in the first embodiment, an ohmic electrode 8 is formed as shown in FIG. 2(C). In this embodiment, since the gap is filled with the second silicon oxide film 9, there is an advantage that the active layer and the contact layer are not etched when the high concentration layer 6 is etched.
以上説明したように本発明は、ソース側はゲートと高濃
度層を近づける事により、ソース抵抗の低減を図る一方
、ドレイン側は高濃度層を薄くすることにより、ゲート
・ドレイン耐圧を向上できる効果がある。As explained above, the present invention has the effect of reducing the source resistance by bringing the gate and high concentration layer closer to each other on the source side, and improving the gate-drain breakdown voltage by making the high concentration layer thinner on the drain side. There is.
第１図は本発明の第１の実施例の縦断面図、第２図は本
発明の第２の実施例の縦断面図、第３図は従来の技術を
示す縦断面図である。
１．１１・・・・・・半導体基板、２，１２・・・・・
・能動層、３．１３・・・・・・ゲート電極、４．】４
・・・・・・コンタクト層、５・・・・・・シリコン酸
化膜、６，１６・・・・・・高濃度層、７・・・・・・
フォトレジス）、８．１７・・・・・・オーミック電極
、９・・・・・・第２のシリコン酸化膜、１２’ ・・
・・・・ドレイン領域、１２″・・・・・・ソース領域
、１５・・・・・・絶縁膜。
代理人 弁理士 内 原 晋
（ｂ＞
、３
第
図
（５Ｌ〕
第１FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, FIG. 2 is a longitudinal sectional view of a second embodiment of the invention, and FIG. 3 is a longitudinal sectional view of a conventional technique. 1.11... Semiconductor substrate, 2,12...
- Active layer, 3.13...gate electrode, 4. ]4
...Contact layer, 5...Silicon oxide film, 6, 16...High concentration layer, 7...
photoresist), 8.17...ohmic electrode, 9...second silicon oxide film, 12'...
...Drain region, 12''...Source region, 15...Insulating film. Agent: Susumu Uchihara, patent attorney (b>, 3 Figure (5L)) 1st
Claims (1)
る工程と、該ゲート電極をマスクとし、前記能動層に重
ねてコンタクト層を形成する工程と、該ゲート電極と自
己整合的に隔てられたコンタクト層上に高濃度層を形成
する工程と、前記能動層のうちドレイン側のゲート電極
近傍の該高濃度層を薄くする工程と、該高濃度層にオー
ミック電極を形成する工程とを含むことを特徴とする半
導体装置の製造方法。forming a gate electrode on the semiconductor substrate on which the active layer is formed; using the gate electrode as a mask, forming a contact layer over the active layer; and forming a contact layer separated from the gate electrode in a self-aligned manner. The method includes the steps of forming a high concentration layer on the contact layer, thinning the high concentration layer near the gate electrode on the drain side of the active layer, and forming an ohmic electrode on the high concentration layer. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26651388A JPH02113539A (en) | 1988-10-21 | 1988-10-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26651388A JPH02113539A (en) | 1988-10-21 | 1988-10-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02113539A true JPH02113539A (en) | 1990-04-25 |
Family
ID=17431949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26651388A Pending JPH02113539A (en) | 1988-10-21 | 1988-10-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02113539A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5298445A (en) * | 1992-05-22 | 1994-03-29 | Nec Corporation | Method for fabricating a field effect transistor |
-
1988
- 1988-10-21 JP JP26651388A patent/JPH02113539A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5298445A (en) * | 1992-05-22 | 1994-03-29 | Nec Corporation | Method for fabricating a field effect transistor |
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