JPS6376380A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPS6376380A
JPS6376380A JP22038486A JP22038486A JPS6376380A JP S6376380 A JPS6376380 A JP S6376380A JP 22038486 A JP22038486 A JP 22038486A JP 22038486 A JP22038486 A JP 22038486A JP S6376380 A JPS6376380 A JP S6376380A
Authority
JP
Japan
Prior art keywords
type
layer
mobility
gaas layer
stripes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22038486A
Other languages
Japanese (ja)
Other versions
JPH07105490B2 (en
Inventor
Kenichi Imamura
健一 今村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61220384A priority Critical patent/JPH07105490B2/en
Publication of JPS6376380A publication Critical patent/JPS6376380A/en
Publication of JPH07105490B2 publication Critical patent/JPH07105490B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To achieve speeding up of mobility of electrons by forming hetero junction interfaces of a channel region so that they may have a plurality of parallel and stripe forms each other and producing electron gases in the same manner as one dimensional quantization that are separated one another among stripes. CONSTITUTION:This device permits an n-type AlxGa1-xAs layer 2 and a non- doping i-type GaAs layer 3 to make an epitaxial growth on a semi-insulated GaAs substrate 1. A flat plane where a stripe-like pattern of the i-type GaAs layer 3 is visible between SiO2 films 5 is formed to make the GaAs layer 3 visible, in which a source and drain contact region is formed by an etching treatment. Si is ion-implanted into this region to form an n-type source and drain contact region 4 after carrying out an activated heat-treatment, thereby arranging a source and drain electrodes 6 composed of, for instance, AuGe/Au as well as a gate electrode 7 composed of, for instance, Al. As a result, electron gases 3e are formed in the vicinity of respective hetero junction interfaces that are patternized in the form of stripes by electrons moved from the n-type AlGaAs layer 2 to the i-type GaAs layer 3. Thus, this approach helps increase mobility of the electrons and improve speeding up of mobility.

Description

【発明の詳細な説明】 〔概要〕 この発明は、空間分離ドーピングと界面量子化による電
子ガスをチャネルとする電界効果トランジスタにかかり
、 チャネル領域のヘテロ接合界面を複数の相互に平行なス
トライプ状に成形して、ストライプ相互間で分離された
1次元量子化に準する電子ガスを生成することにより、 電子の移動度を高めて、半導体装置の高速化を進めるも
のである。
[Detailed Description of the Invention] [Summary] The present invention relates to a field effect transistor that uses an electron gas as a channel by spatially separated doping and interface quantization, and in which the heterojunction interface in the channel region is formed into a plurality of mutually parallel stripes. By molding and producing an electron gas that corresponds to one-dimensional quantization separated between stripes, the mobility of electrons is increased and the speed of semiconductor devices is increased.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置、特に空間分離ドーピングと界面量
子化による1次元に準する高移動度の電子ガスをチャネ
ルとする半導体装置に関する。
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a channel is a high-mobility electron gas based on one-dimensional doping and interface quantization.

従来知られている高電子移動度電界効果トランジスタ(
HEMT)は2次元量子化された電子ガスをチャネルと
しているが、この2次元量子化状態を1次元量子化状態
に近づけた更に高電子移動度の半導体装置の実現が要望
されている。
The conventionally known high electron mobility field effect transistor (
HEMT) uses a two-dimensional quantized electron gas as a channel, but there is a desire to realize a semiconductor device with even higher electron mobility in which the two-dimensional quantized state approaches the one-dimensional quantized state.

〔従来の技術〕[Conventional technology]

従来のHEMTの一例の模式側断面図を第3図に示す。 A schematic side sectional view of an example of a conventional HEMT is shown in FIG.

本従来例では半絶縁性砒化ガリウム(GaAs)基板2
1上に、ノンドープのi形GaAs層22と、これより
電子親和力が小さく例えば濃度2×10111CI+1
弓程度にドナー不純物がドープされたn型砒化アルミニ
ウムガリウム(AIXGal−XMS)層23と、これ
と同程度以上にドナー不純物がドープされたn型GaA
s層24とが設けられ、n型AlGaAs1J23から
i形GaAs層22へ遷移した電子によってヘテロ接合
界面近傍に2次元電子ガス22eが形成される。
In this conventional example, a semi-insulating gallium arsenide (GaAs) substrate 2
1, there is a non-doped i-type GaAs layer 22 on top of the undoped i-type GaAs layer 22, and a layer 22 having a smaller electron affinity than that, for example, a concentration of 2×10111CI+1.
An n-type aluminum gallium arsenide (AIXGal-XMS) layer 23 doped with donor impurities to the extent of an arch, and an n-type GaA layer 23 doped with donor impurities to the same extent or more.
A two-dimensional electron gas 22e is formed near the heterojunction interface by electrons transferred from the n-type AlGaAs1J23 to the i-type GaAs layer 22.

この半導体基体のn型GaAs層24上に例えば金ゲル
マニウム/金(AuGe/Au)を用いてソース、ドレ
イン電極26を設け、n型AlGaAs電子供給層23
上に例えばチタン/白金/金(Ti/Pt/Au)又は
アルミニウム(AI)等を用いてゲート電極27を設け
る。なお26Aはソース、ドレイン電極26と半導体基
体との間に形成された合金化領域である。
Source and drain electrodes 26 are provided on the n-type GaAs layer 24 of this semiconductor substrate using, for example, gold germanium/gold (AuGe/Au), and the n-type AlGaAs electron supply layer 23
A gate electrode 27 is provided thereon using, for example, titanium/platinum/gold (Ti/Pt/Au) or aluminum (AI). Note that 26A is an alloyed region formed between the source/drain electrode 26 and the semiconductor substrate.

ゲート電極27によるショットキ空乏層で2次元電子ガ
ス22eの面密度を制御してトランジスタ動作が行われ
るが、この2次元電子ガス22eは不純物散乱による移
動度低下が殆どなく、格子散乱が低下する例えば77に
程度以下の低温において最も高い移動度が得られる。こ
の場合の電子移動度は通常1〜10X10’cm”/V
、s、例えば6 X 10’cm”/V、s程度であり
、不純物をドープしたGaAs単結晶内の電子移動度が
I X 10’cm”/V、s以下であるのに比較すれ
ば遥かに高い値が得られている。
Transistor operation is performed by controlling the areal density of the two-dimensional electron gas 22e in the Schottky depletion layer formed by the gate electrode 27, but this two-dimensional electron gas 22e has almost no reduction in mobility due to impurity scattering and, for example, when lattice scattering is reduced. The highest mobility is obtained at low temperatures below 77°C. In this case, the electron mobility is usually 1 to 10×10'cm"/V
, s, for example, about 6 x 10'cm"/V, s, which is much lower than the electron mobility in a GaAs single crystal doped with impurities, which is less than I x 10'cm"/V, s. A high value has been obtained.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の様に、2次元電子ガスをチャネルとするHEMT
は従来の電界効果トランジスタ中でキャリアの移動度が
最も高く、ゲート長の短縮と相俟って、半導体装置の高
速化の代表的な例となっている。
As mentioned above, HEMT uses two-dimensional electron gas as a channel.
has the highest carrier mobility among conventional field effect transistors, and together with shortening the gate length, it has become a typical example of increasing the speed of semiconductor devices.

しかしながらパターンの微細化、ゲート長の短縮にも限
界があり、電子の1次元量子化或いはこれに準する状態
によってキャリア移動度を更に高めた電界効果トランジ
スタを具体的に実現することが要望されている。
However, there are limits to miniaturization of patterns and shortening of gate length, and there is a need to concretely realize field-effect transistors that further increase carrier mobility through one-dimensional quantization of electrons or a similar state. There is.

〔問題点を解決するための手段〕[Means for solving problems]

前記問題点は、ノンドープの第1の半導体層と、該第1
の半導体層より電子親和力が小さくドナー不純物を含む
第2の半導体層とのヘテロ接合を備え、 チャネル領域の該ヘテロ接合界面が複数の相互に平行な
ストライプ状に成形されて、該ストライプ相互間で分離
され、かつ少なくとも該界面に垂直方向について量子化
された電子ガスが該界面近傍に生成され、 該ストライプに交差して配設されたゲート電極により該
電子ガスを制御する本発明による半導体装置により解決
される。
The problem is that the non-doped first semiconductor layer and the first
The channel region has a heterojunction with a second semiconductor layer that has a smaller electron affinity than the second semiconductor layer and contains donor impurities, and the heterojunction interface of the channel region is formed into a plurality of mutually parallel stripes, and there are gaps between the stripes. By the semiconductor device according to the present invention, an electron gas that is separated and quantized at least in a direction perpendicular to the interface is generated near the interface, and the electron gas is controlled by a gate electrode disposed intersecting the stripe. resolved.

〔作 用〕[For production]

本発明によれば、空間分離ドーピングされたヘテロ接合
界面のチャネル領域を、複数の相互に平行で幅が狭いス
トライプ状に成形し、該界面に垂直方向については従来
の2次元電子ガスと同様に量子化され、ストライプ幅方
向についてはストライプ相互間で分離され、量子化され
ないまでも1次元量子化に準する散乱作用が少ない電子
ガスを生成させて、その電子移動度を従来の2次元電子
ガスより高くする。
According to the present invention, the channel region of the spatially separated doped heterojunction interface is formed into a plurality of mutually parallel narrow stripes, and the direction perpendicular to the interface is similar to the conventional two-dimensional electron gas. The electron gas is quantized and separated between stripes in the stripe width direction, and although it is not quantized, it generates an electron gas with a low scattering effect similar to one-dimensional quantization, and its electron mobility is compared to that of a conventional two-dimensional electron gas. make it higher.

1次元量子化に到達するためにはストライプの幅方向を
電子のドウ・ブロイ−波長(GaAsでは約30nm)
以下にすることが必要であり、リソグラフィーエツチン
グ法等によるパターン形成でこれを実現することは困難
であるが、その10倍程度以下として2次元電子ガスよ
り散乱作用を減少させ、移動度を増大することは可能で
ある。
In order to achieve one-dimensional quantization, the width direction of the stripe must be aligned with the Doe-Brog wavelength of electrons (approximately 30 nm in GaAs).
Although it is difficult to achieve this by pattern formation using lithography etching methods, etc., it is necessary to reduce the scattering effect by about 10 times or less than the two-dimensional electron gas and increase the mobility. It is possible.

なおこの寸法にばらつきを生じてもゲート長短縮の場合
の様に特性が大幅に変動することはない。
Note that even if variations occur in this dimension, the characteristics will not vary significantly as in the case of shortening the gate length.

更に複数のストライプが並列接続されるために、単に電
流を増大するのみでなく、ばらつきが平均化される効果
が得られている。
Furthermore, since a plurality of stripes are connected in parallel, it is possible not only to simply increase the current but also to average out variations.

〔実施例〕〔Example〕

以下本発明を実施例により具体的に説明する。 The present invention will be specifically explained below using examples.

第1図は本発明の実施例の模式図であり、図(alはそ
の平面図、図(b)はX−X’断面図、図(C)はY−
Y’断面図を示し、第2図(11乃至(3)は本実施例
の製造工程中のY−Y”断面図である。
FIG. 1 is a schematic diagram of an embodiment of the present invention.
A Y' cross-sectional view is shown, and FIG. 2 (11 to (3)) is a Y-Y'' cross-sectional view during the manufacturing process of this embodiment.

図において、1は半絶縁性GaAs基板、2は例えばシ
リコン(St)を濃度2 X 1011+ am−3程
度にドープしたn型A1xGat−、As(x=0.3
)層、3はノンドープのi型GaAs層、4は例えばS
tを注入したn型ソース・ドレインコンタクト領域、5
は例えばSingからなる保護絶縁膜、6は例えばAu
Ge/Auからなるソース、ドレイン電極、6Aはソー
ス、ドレイン電極6と半導体基体との間に形成された合
金化領域、7は例えばA1からなるゲート電極であり、
n型AtGaAs層2からi形GaAs層3へ遷移した
電子によって、電子ガス3eがストライプ状にパターン
化された各ヘテロ接合界面近傍に形成されている。
In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type A1x Gat-, As (x=0.3
) layer, 3 is a non-doped i-type GaAs layer, 4 is, for example, S
n-type source/drain contact region implanted with T, 5
6 is a protective insulating film made of, for example, Sing, and 6 is made of, for example, Au.
Source and drain electrodes made of Ge/Au; 6A is an alloyed region formed between the source and drain electrode 6 and the semiconductor substrate; 7 is a gate electrode made of, for example, A1;
Electrons transferred from the n-type AtGaAs layer 2 to the i-type GaAs layer 3 form an electron gas 3e in the vicinity of each heterojunction interface patterned into stripes.

本実施例は例えば下記の様に製造される。This example is manufactured, for example, as follows.

第2図(1)参照二 半絶縁性GaAs基板1上に、例
えば分子線エピタキシャル成長方法により、前記n型A
lxGa、−、As層2とノンドープのi型GaAs層
3とを、例えば厚さそれぞれ1100nにエピタキシャ
ル成長する。
Refer to FIG. 2 (1) 2. The n-type A
The lxGa, -, As layer 2 and the non-doped i-type GaAs layer 3 are epitaxially grown to a thickness of, for example, 1100 nm.

i型GaAs層3上に例えば5iOz膜を設け、そのチ
ャネル領域上の部分に例えばマスク幅wI=Q、4gm
、開口幅wz=Q、4Innのストライプ状パターンを
形成して、マスク11とする。
For example, a 5iOz film is provided on the i-type GaAs layer 3, and a mask width wI=Q, 4gm is formed on the portion above the channel region.
, an opening width wz=Q, and a striped pattern of 4 Inn is formed to form a mask 11.

第2図(2)参照: このマスク11を用いて、例えば
2塩化2弗化炭素(CChFt)によるリアクティブイ
オンエツチング法により、i型GaAs層3をエツチン
グする。このエツチング法ではGaAs層3がAlGa
As層2に対して選択的にエツチングされ、サイドエツ
チング効果によりi型GaAs層3をマスク幅W+より
狭いストライプ幅W=0.1〜0.2pm程度とする。
Refer to FIG. 2(2): Using this mask 11, the i-type GaAs layer 3 is etched by, for example, a reactive ion etching method using carbon dichloride difluoride (CChFt). In this etching method, the GaAs layer 3 is made of AlGa
The As layer 2 is selectively etched, and the i-type GaAs layer 3 is made to have a stripe width W=0.1 to 0.2 pm, which is narrower than the mask width W+, due to the side etching effect.

第2図(3)参照: マスク11を除去してSing膜
5を堆積し、更にレジスト等の膜12を被着してその上
表面を平坦にし、例えば4弗化炭素(CF4.)に酸素
(02)を加えたドライエツチングにより、5iOz膜
5間にi型GaAs層3のストライプ状パターンが表出
する平坦面を形成する。
Refer to FIG. 2 (3): The mask 11 is removed, the Sing film 5 is deposited, and a film 12 such as a resist is further applied to make the upper surface flat. By dry etching with (02) added, a flat surface is formed between the 5iOz films 5 on which the striped pattern of the i-type GaAs layer 3 is exposed.

第1図(al、(b)参照: このエツチング処理によ
リソース・ドレインコンタクト領域4とするGaAs層
3も表出する。この領域のGaAs層3に、例えばSi
をエネルギー100keV程度でドーズ量1×1013
CIl−2程度イオン注入し、活性化熱処理を行ってn
型ソース・ドレインコンタクト領域4を形成して、例え
ばAuGe/Auからなるソース、ドレイン電極6を配
設し、合金化熱処理を行う。
Refer to FIGS. 1(al) and (b): Through this etching process, the GaAs layer 3 which will become the resource/drain contact region 4 is also exposed.
with an energy of about 100 keV and a dose of 1×1013
After implanting ions of CIl-2 and performing activation heat treatment,
Type source/drain contact regions 4 are formed, source and drain electrodes 6 made of, for example, AuGe/Au are provided, and alloying heat treatment is performed.

第1図(a)、(C)参照: 例えばA1からなるゲー
ト電極7を配設する。
See FIGS. 1(a) and 1(C): A gate electrode 7 made of, for example, A1 is provided.

本実施例では例えば温度77Kにおいて、電子移動度が
約I X 106cn+”/V、sであり、従来の2次
元量子化HEMTの電子移動度が1〜10 X 10’
cm”/V、s、例えば6 X 10’cm”/V;s
程度であるのに比較して、明らかな増大が実証されてい
る。
In this embodiment, for example, at a temperature of 77 K, the electron mobility is about I x 106cn+"/V,s, and the electron mobility of a conventional two-dimensional quantized HEMT is 1 to 10 x 10'
cm"/V,s, e.g. 6 X 10'cm"/V;s
A clear increase has been demonstrated compared to the extent of

前記実施例ではn型AlGaAs層を基板側としている
が、例えばノンドープのi型GaAs層を基板側としn
型AlGaAs層をその上に成長して、電子供給層をス
トライプ状にパターニングしても同様の効果を得ること
ができる。また本発明はGaAs/AlGaAs系に限
られず、例えばInGaAs / InAlAs等を用
いた半導体装置に適用し得ることは明らかである。
In the above embodiment, the n-type AlGaAs layer is on the substrate side, but for example, the non-doped i-type GaAs layer is on the substrate side.
A similar effect can be obtained by growing an AlGaAs layer thereon and patterning the electron supply layer into stripes. Furthermore, it is clear that the present invention is not limited to GaAs/AlGaAs semiconductor devices, but can be applied to semiconductor devices using, for example, InGaAs/InAlAs.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明によれば、空間分離ドーピング
と1次元に準する界面量子化により、電子移動度が従来
のHEMTより更に増大されて半導体装置の高速化が一
層推進され、例えば次世代の電子計算システム等に大き
い効果を与える。
As explained above, according to the present invention, the electron mobility is further increased than that of conventional HEMTs by spatially separated doping and interface quantization that approximates one-dimensionality, and the speeding up of semiconductor devices is further promoted. It has a great effect on electronic computing systems, etc.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の模式図、 第2図はその製造工程中のY−Y”断面図、第3図は従
来例の模式側断面図である。 図において、 1は半絶縁性GaAs基板、 2はn型AlzGaI−xAs層、 3はノンドープのi型GaAs層、 3eは電子ガス、 4はn型ソース・ドレインコンタクト領域、5は保護絶
縁膜、 6はソース、ドレイン電極、 6Aは合金化領域、 7はゲート電極、 11はマスク、 12はレジスト等の膜を示す。 手1 凶 票2 図 従来fノ”1の漠式便層眉狛囚 $3 g
Fig. 1 is a schematic diagram of an embodiment of the present invention, Fig. 2 is a cross-sectional view taken along the Y-Y” line during the manufacturing process, and Fig. 3 is a schematic side sectional view of a conventional example. 2 is an n-type AlzGaI-xAs layer, 3 is a non-doped i-type GaAs layer, 3e is an electron gas, 4 is an n-type source/drain contact region, 5 is a protective insulating film, 6 is a source and drain electrode, 6A is an alloyed region, 7 is a gate electrode, 11 is a mask, and 12 is a film such as a resist.

Claims (1)

【特許請求の範囲】 ノンドープの第1の半導体層と、該第1の半導体層より
電子親和力が小さくドナー不純物を含む第2の半導体層
とのヘテロ接合を備え、 チャネル領域の該ヘテロ接合界面が複数の相互に平行な
ストライプ状に成形されて、該ストライプ相互間で分離
され、かつ少なくとも該界面に垂直方向について量子化
された電子ガスが該界面近傍に生成され、 該ストライプに交差して配設されたゲート電極により該
電子ガスを制御することを特徴とする半導体装置。
[Claims] A heterojunction is provided between a non-doped first semiconductor layer and a second semiconductor layer that has a smaller electron affinity than the first semiconductor layer and contains donor impurities, and the heterojunction interface in the channel region is Formed into a plurality of mutually parallel stripes, an electron gas separated between the stripes and quantized at least in a direction perpendicular to the interface is generated near the interface and distributed across the stripes. A semiconductor device characterized in that the electron gas is controlled by a gate electrode provided.
JP61220384A 1986-09-18 1986-09-18 Semiconductor device Expired - Lifetime JPH07105490B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61220384A JPH07105490B2 (en) 1986-09-18 1986-09-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61220384A JPH07105490B2 (en) 1986-09-18 1986-09-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6376380A true JPS6376380A (en) 1988-04-06
JPH07105490B2 JPH07105490B2 (en) 1995-11-13

Family

ID=16750277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61220384A Expired - Lifetime JPH07105490B2 (en) 1986-09-18 1986-09-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH07105490B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02134830A (en) * 1988-11-15 1990-05-23 Nec Corp Field effect transistor
US6242765B1 (en) * 1991-05-21 2001-06-05 Nec Corporation Field effect transistor and its manufacturing method
CN103383959A (en) * 2013-07-04 2013-11-06 西安电子科技大学 Crosswise overgrowth one-dimensional electron gas GaN-base high electron mobility transistor (HEMT) device and manufacturing method thereof
CN103400856A (en) * 2013-07-04 2013-11-20 西安电子科技大学 One-dimensional electronic gas GaN-based HEMT (High Electron Mobility Transistor) device adopting selective area epitaxy and preparation method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61170070A (en) * 1985-01-23 1986-07-31 Sony Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61170070A (en) * 1985-01-23 1986-07-31 Sony Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02134830A (en) * 1988-11-15 1990-05-23 Nec Corp Field effect transistor
US6242765B1 (en) * 1991-05-21 2001-06-05 Nec Corporation Field effect transistor and its manufacturing method
CN103383959A (en) * 2013-07-04 2013-11-06 西安电子科技大学 Crosswise overgrowth one-dimensional electron gas GaN-base high electron mobility transistor (HEMT) device and manufacturing method thereof
CN103400856A (en) * 2013-07-04 2013-11-20 西安电子科技大学 One-dimensional electronic gas GaN-based HEMT (High Electron Mobility Transistor) device adopting selective area epitaxy and preparation method thereof

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