JPS61188966A - Manufacture of high speed semiconductor device - Google Patents
Manufacture of high speed semiconductor deviceInfo
- Publication number
- JPS61188966A JPS61188966A JP2755885A JP2755885A JPS61188966A JP S61188966 A JPS61188966 A JP S61188966A JP 2755885 A JP2755885 A JP 2755885A JP 2755885 A JP2755885 A JP 2755885A JP S61188966 A JPS61188966 A JP S61188966A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- collector
- base
- emitter
- type gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 28
- 238000005530 etching Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 9
- 239000010931 gold Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910001423 beryllium ion Inorganic materials 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- -1 oxygen ions Chemical class 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- JLVVSXFLKOJNIY-UHFFFAOYSA-N Magnesium ion Chemical compound [Mg+2] JLVVSXFLKOJNIY-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910001425 magnesium ion Inorganic materials 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
本発明は、コレクタ、ベース、エミッタなどを半導体層
を積層して構成する縦型の高速半導体装置を製造する方
法において、それ等の各半導体層を形成してから、エミ
ッタ電極をマスクとしてイオン注入を行い、コレクタ層
をエミッタ電極の形状に対応するパターンに限定する絶
縁膜及びその絶縁膜上にベース・コンタクト９１１ｋＡ
を形成するようにして、コレクタ層の面積をエミッタ電
極と同程度に小さくし、コレクタ容量の低減を図ってス
イッチング・スピードを向上するようにしたものである
。[Detailed Description of the Invention] [Summary] The present invention provides a method for manufacturing a vertical high-speed semiconductor device in which a collector, a base, an emitter, etc. are formed by stacking semiconductor layers. After that, ion implantation is performed using the emitter electrode as a mask, and an insulating film is formed to limit the collector layer to a pattern corresponding to the shape of the emitter electrode, and a base contact 911 kA is formed on the insulating film.
The area of the collector layer is made as small as that of the emitter electrode, thereby reducing the collector capacitance and improving the switching speed.
本発明は、ヘテロ接合バイポーラ・トランジスタ（ｈｅ
ｔｅｒｏｊｕｎｃｔｉｏｎ ｂｉｐｏｌａｒ ｔｒ
ａｎｓｉｓｔｏｒ：ＨＢＴ）と呼ばれる縦型の高速半導
体装置を製造する方法の改良に関する。The present invention provides a heterojunction bipolar transistor (he
terojunction bipolar tr
The present invention relates to an improvement in a method for manufacturing a vertical high-speed semiconductor device called an ansistor (HBT).
近年、例えば、高電子移動度トランジスタ（ｈｉｇｈ
ｅｌｅｃｔｒｏｎ ｍｏｂｉｌｉｔｙ −ｔｒ
ａｎｓｉｓｔｏｒ：ＨＥＭＴ）などへテロ接合を有する
高性能の半導体装置に関する研究・開発が盛んであるが
、ＨＢＴ或いはＨＥＴなど、薄層の半導体層を積層して
縦方向に電流を流すバイポーラ系の高速半導体装置では
、電流駆動能力が大、即ち、伝達コンダクタンス９ｍが
大きい為、負荷容量を充放電する時間が短く、非常に高
速である。In recent years, for example, high electron mobility transistors (high
electron mobility-tr
There is active research and development into high-performance semiconductor devices with heterojunctions such as HBTs and HETs; Since the device has a large current drive capability, that is, a large transfer conductance of 9 m, the time for charging and discharging the load capacity is short and the device is very fast.
第２図は本発明者が最近試作したＡｊ２ＧａＡｓ／ Ｇ
ａ Ａ ｓ系へテロ接合ＨＢＴを説明する為の要部切
断側面図を表している。Figure 2 shows Aj2GaAs/G, which was recently prototyped by the present inventor.
FIG. 3 is a cross-sectional side view of essential parts for explaining the a As-based heterojunction HBT.
図に於いて、１は半絶縁性ＧａＡｓ基板、２はｎ＋型Ｇ
ａＡｓコレクタ・コンタクト層、３はｎ型ＧａＡｓコレ
クタ層、４はｐ＋型ＧａＡｓベース層、４Ａはｐ＋型ベ
ース・コンタクト領域、５はｎ型ＡｌＧａＡｓエミッタ
層、６はｎ＋型ＧａＡｓエミッタ・コンタクト層、７は
エミッタ電極、８はベース電極、９はコレクタ電極、１
０は絶縁分離用溝をそれぞれ示している。In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n+ type G
aAs collector contact layer, 3 an n-type GaAs collector layer, 4 a p+-type GaAs base layer, 4A a p+-type base contact region, 5 an n-type AlGaAs emitter layer, 6 an n+-type GaAs emitter contact layer, 7 is an emitter electrode, 8 is a base electrode, 9 is a collector electrode, 1
0 indicates an insulating isolation groove.
図示されたＨＢＴに於ける各部分の諸データを例示する
と次の通りである。Examples of various data of each part in the illustrated HBT are as follows.
■ ｎ”型ＧａＡｓコレクタ・コンタクト層２厚み：
３００〜５００ （ｎｍ）
不純物濃度： ２Ｘ Ｉ Ｑ１０（ａｍ−”）■ ｎ型
ＧａＡｓコレクタ層３
厚み： ３００〜５００ （ｎｍ）
不純物濃度： ３ Ｘ １０１６ （ｃｍ−’） （
最適化状態、通常は、ｌＸ１０１７（口″町程度）
■ ｐ＋型ＧａＡｓベースＮ４
厚み： ５０＝１００ （ｎｍ）
不純物濃度： ｌ Ｘ Ｉ Ｑ１０（ａｍ−’）■ ｐ
＋型ベース・コンタクト領域４Ａ深さ： １００〜３０
０ ［ｎｍ）
不純物濃度： Ｉ Ｘ １０１９ （ａｍ−３）■ ｎ
型ＡｌＧａＡｓエミッタ層５
厚み： １００〜２００ （ｎｍ）
不純物濃度：１〜５ Ｘ １０” （ｃｍ−’）■
ｎ”型ＧａＡｓエミッタ・コンタクト層６厚み＝ ２０
０〜３００ （ｎｍ）
不純物濃度： ”ｌ Ｘ Ｉ Ｑ ｌ８（ｃ＋ａ−’）
■ エミッタ電極７
材料二金（Ａｕ）・ゲルマニウム（Ｇｅ）／Ａｕ／タン
グステン・シリサイド（ＷＳｉ）厚み：２００（人）／
１０００ （人）／３０００〔人〕
■ ベース電極８
材料： Ａｕ／亜鉛（Ｚｎ）／Ａｕ
厚み：１００（人）／１００（人） ／３０００〔人〕
■ コレクタ電極９
材料：Ａｕ−Ｇｅ／Ａｕ
厚み：２００（人）／２８００（人）
このようなＨＢＴに於いては、ホモ接合の場合と異なり
、エミッタ・ベース間にエネルギ・バンド・ギャップ差
がある為、有能指数βを大きくできることが特徴となっ
ている。■ Thickness of n” type GaAs collector contact layer 2:
300 to 500 (nm) Impurity concentration: 2X I Q10 (am-'') ■ N-type GaAs collector layer 3 Thickness: 300 to 500 (nm) Impurity concentration: 3 X 1016 (cm-') (
Optimized state, usually lX1017 (about 100mm) ■ p+ type GaAs base N4 thickness: 50 = 100 (nm) Impurity concentration: l X I Q10 (am-') ■ p
+ type base contact area 4A depth: 100~30
0 [nm] Impurity concentration: I X 1019 (am-3) ■ n
Type AlGaAs emitter layer 5 Thickness: 100 to 200 (nm) Impurity concentration: 1 to 5 x 10"(cm-')■
n” type GaAs emitter contact layer 6 thickness = 20
0 to 300 (nm) Impurity concentration: "lXIQl8(c+a-')
■ Emitter electrode 7 Materials Two gold (Au)/germanium (Ge)/Au/tungsten silicide (WSi) Thickness: 200 (people)/
1000 (people) / 3000 [people] ■ Base electrode 8 Material: Au / Zinc (Zn) / Au Thickness: 100 (people) / 100 (people) / 3000 [people] ■ Collector electrode 9 Material: Au-Ge / Au Thickness: 200 (people) / 2800 (people) In such HBTs, unlike the case of homozygous, there is an energy band gap difference between the emitter and the base, so it is possible to increase the efficiency index β. It is a feature.
通常、バイポーラ・トランジスタを高速化するには、ベ
ース幅を狭くすることが有効であるが、そのままでは、
ベース抵抗が高くなってしまうか、 ら、ベースの不純
物濃度を高くして回避する必要がある。Normally, narrowing the base width is effective in increasing the speed of bipolar transistors, but
To prevent this from increasing the base resistance, it is necessary to increase the impurity concentration in the base.
然しなから、そのようにすると、ベースからエミッタに
流れ込むホールの数が増大し、有能指数βは低下してし
まう。However, if this is done, the number of holes flowing from the base to the emitter increases, and the efficiency index β decreases.
ＨＢＴに於いては、エミッタのエネルギ・バンド・ギャ
ップを大にすることでホール電流を抑止することができ
るから、ベースの不純物濃度を所望通りに高くして、高
速動作させることが可能となるものである。In HBTs, hole current can be suppressed by increasing the energy band gap of the emitter, making it possible to increase the impurity concentration in the base as desired and achieve high-speed operation. It is.
さて、前記したようなＨＢＴに於いては、ｎ＋型ＧａＡ
ｓコレクタ・コンタクト層２とｎ 型Ａ’ＧａＡｓエミ
ッタ層５との間に在るｎ型ＧａＡｓコレクタ層３の面積
が非常に大きいので、その容量、即ち、コレクタ容量が
大である為、スイッチング時間を短くすることができな
かった。Now, in the above-mentioned HBT, n+ type GaA
Since the area of the n-type GaAs collector layer 3 located between the s-collector contact layer 2 and the n-type A'GaAs emitter layer 5 is very large, its capacitance, that is, the collector capacitance is large, so that the switching time is could not be made shorter.
本発明は、前記したような縦型の高速半導体装置に於い
て、コレクタ容量を低減し、スイッチング・スピードを
向上できるようにする。The present invention enables the collector capacitance to be reduced and the switching speed to be improved in the vertical high-speed semiconductor device as described above.
本発明一実施例を解説する為の図である第１図を借りて
説明すると、本発明に於ける手段では、半絶縁性ＧａＡ
ｓ基板１１上に少なくともコレクタ層１３及びベース層
１４及びエミッタ層１５を形成し、次いで、表面が高融
点金属からなるエミッタ電極１７を形成し、次いで、該
エミッタ電極１７をマスクにイオンを注入して前記コレ
クタ層１３を該エミッタ電極１７の形状に対応するパタ
ーンに限定する絶縁１１１１８及びその上のベース・コ
ンタクト領域１９を形成し、前記ベース・コンタクト領
域１９及びコレクタ・コンタクト層１２からベース電極
及びコレクタ電極をそれぞれ対応させて導出するように
している。To explain with reference to FIG. 1, which is a diagram for explaining one embodiment of the present invention, the means in the present invention uses semi-insulating GaA
At least a collector layer 13, a base layer 14, and an emitter layer 15 are formed on the s-substrate 11, and then an emitter electrode 17 whose surface is made of a high-melting point metal is formed, and then, ions are implanted using the emitter electrode 17 as a mask. forming an insulator 11118 that defines the collector layer 13 in a pattern corresponding to the shape of the emitter electrode 17 and a base contact region 19 thereon; The collector electrodes are derived in correspondence with each other.
Ｃ作用〕
前記説明した手段に依ると、コレクタ層１４がエミッタ
電極１７をマスクするイオン注入で形成された絶縁膜１
８でエミッタ電極１７と同程度に小面積化される為、そ
のコレクタ容量を極めて小さい値にすることができる。C action] According to the means described above, the collector layer 14 is formed by the insulating film 1 formed by ion implantation that masks the emitter electrode 17.
8, the area is reduced to the same extent as the emitter electrode 17, so its collector capacitance can be made extremely small.
従って、本発明の高速半導体装置に於けるスイッチング
・スピードは一段と向上する。Therefore, the switching speed in the high-speed semiconductor device of the present invention is further improved.
第１図（Ａ）乃至（Ｄ）は本発明一実施例を説明する為
の工程要所に於ける半導体装置の要部切断側面図であり
、以下、これ等の図を参照しつつ説明する。1A to 1D are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures. .
第１図（Ａ）参照
（ａｌ 分子線エピタキシャル成長（ｍｏｌｅｃｕｌ
ａｒ ｂｅａｍ ｅｐｉｔａｘｙ：ＭＢＥ）法を適
用することに依り、半絶縁性ＧａＡｓ基板１１の表面に
対し、ｎ４型ＧａＡＳコレクタ・コンタクト層１２、ｎ
１ＧａＡｓコレクタ層１３、ｐ＋型ＧａＡｓベース層１
４、ｎ型ＡＪ！ＧａＡｓエミッタ層１５、ｎ＋型ＧａＡ
ｓエミフタ・コンタクト層１６を成長させる。尚、前記
ＭＢＥ法に代えて有機金属熱分解気相成長（ｍｅｔａｌ
ｏｒｇａｎｉｃｓ ｃｈｅｍｉｃａｌｖａｐｏｕｒ
ｄｅｐｏｓｉｔｉｏｎ：ＭＯＣＶＤ）法或いは気相成
長（ｖａｐｏｒ ｐｈａｓｅ ｅｐｔｔａｘｙ：Ｖ
ＰＥ）法を適用すること・もてきる。See Figure 1 (A) (al Molecular beam epitaxial growth (molecular beam epitaxial growth)
By applying the ar beam epitaxy (MBE) method, an n4 type GaAs collector contact layer 12, an n4 type GaAs collector contact layer 12, an n
1 GaAs collector layer 13, p+ type GaAs base layer 1
4. n-type AJ! GaAs emitter layer 15, n+ type GaA
s-emifter contact layer 16 is grown. Note that instead of the MBE method, metal organic pyrolysis vapor phase epitaxy (metal
organics chemical vapor
deposition:MOCVD) method or vapor phase epitaxy:V
PE) Applying the law.
ここで成長させた各半導体層の厚みや不純物濃度などは
、第２図に関して説明した従来例と同様である。The thickness, impurity concentration, etc. of each semiconductor layer grown here are the same as those of the conventional example explained with reference to FIG.
ｆｂｌ 通常のフォト・リソグラフィ技術に於けるレ
ジスト・プロセスを適用することに依り、エミッタ電極
形成用開口を有するフォト・レジスト膜を形成してから
、蒸着法を適用することに依り、厚み約５０（ｎｍ）程
度のＧｅ膜及び厚み約２００（ｎｍ）程度のモリブデン
（Ｍ ｏ ）膜を形成する。fbl By applying a resist process in ordinary photolithography technology, a photoresist film having an opening for forming an emitter electrode is formed, and then by applying a vapor deposition method, a photoresist film with a thickness of about 50mm ( A Ge film with a thickness of about 200 (nm) and a molybdenum (M o ) film with a thickness of about 200 (nm) are formed.
（Ｃ） 全体を、例えばアセトン中に浸漬して前記フ
ォト・レジスト膜を溶解除去することに依り、Ｇｅ膜及
びＭｏ膜のバターニングを行い、エミッタ電極１７を形
成する。(C) The entire structure is immersed in, for example, acetone to dissolve and remove the photoresist film, thereby patterning the Ge film and the Mo film to form the emitter electrode 17.
第１図（Ｂ）
（ｄ） エミッタ電極１７をマスクとしてｎ＋型Ｇａ
Ａｓコレクタ・コンタクト層１６のウェット・エツチン
グを行う。尚、この場合のエツチング液にはフッ酸系の
ものを用いることができ、また、図示されているように
、およそ０．１ 〔μｍ〕、サイド・エツチングが行わ
れるようにする。Figure 1 (B) (d) n+ type Ga using the emitter electrode 17 as a mask
Wet etching of the As collector contact layer 16 is performed. In this case, a hydrofluoric acid-based etching solution can be used, and as shown in the figure, side etching is performed by approximately 0.1 [μm].
第１図（Ｃ）参照
＋８） イオン注入法を適用することに依り、酸素イ
オンの注入を行い、引き続きベリリウム・イオンの注入
を行う。Refer to FIG. 1(C)+8) By applying an ion implantation method, oxygen ions are implanted, followed by beryllium ions.
この場合に於けるイオン注入条件は次の通りである。The ion implantation conditions in this case are as follows.
■ 酸素イオンの場合
注入エネルギ： １５０ （ＫｅＶ）
ドーズ量：２Ｘ１０１３ （ロー２〕
■ ベリリウム・イオンの場合
注入エネルギ：４０（ＫｅＶ）
ドーズ量：１ｘｌ□＋ｓ む「２〕
尚、ベリリウム・イオンに代えてマグネシウム・イオン
を用いることもできるが、その場合は、注入エネルギを
１２０（ＫｅＶ）にする必要がある。■ For oxygen ions, implantation energy: 150 (KeV) Dose: 2x1013 (Rho 2) ■ For beryllium ions, implantation energy: 40 (KeV) Dose: 1xl + s 2) In addition, instead of beryllium ions, Magnesium ions can also be used, but in that case the implantation energy needs to be 120 (KeV).
（ｆｌ 温度９００〔℃〕、時間５〔秒〕の熱処理、
例えばフラッシュ・アニールを行う。(fl Heat treatment at a temperature of 900 [℃] and a time of 5 [seconds],
For example, flash annealing is performed.
これに依り、絶縁膜１８及びｐ＋型ベース・コンタクト
領域１９が得られる。As a result, an insulating film 18 and a p+ type base contact region 19 are obtained.
第１図（Ｄ）参照
（ｇｌ 通常の技法を適用することに依り、階段状の
メサ・エツチングを行い、ｎ ４ｐ型ＧａＡｓコレクタ
・コンタクト層１２の一部表面を露出させる。See FIG. 1(D) (gl) By applying conventional techniques, a stepped mesa etching is performed to expose a portion of the surface of the n4p type GaAs collector contact layer 12.
ｆｈｌ 通常の技法、例えば、蒸着法及びリフト・オ
フ法を適用することに依り、ベース電極２０、コレクタ
電極２１などを形成する。fhl The base electrode 20, collector electrode 21, etc. are formed by applying conventional techniques, such as vapor deposition and lift-off methods.
尚、前記各電極の材料及び厚み等は第５図に関して説明
した従来例と同様である。The material, thickness, etc. of each of the electrodes are the same as in the conventional example explained with reference to FIG.
前記実施例のようにして製造された高速半導体装置では
、ｎ型ＧａＡｓコレクタ層１３は絶縁膜１８に依り、そ
の面積が限定され、エミッタ電極１７と同程度しかない
。In the high-speed semiconductor device manufactured as in the embodiment described above, the area of the n-type GaAs collector layer 13 is limited by the insulating film 18, and is only about the same size as the emitter electrode 17.
本発明による高速半導体装置の製造方法では、半絶縁性
結晶基板上に少なくともコレクタ層及びベース層及びエ
ミッタ層を形成し、次いで、表面が高融点金属からなる
エミッタ電極を形成し、次いで、該エミッタ電極をマス
クにイオンを注入して前記コレクタ層を該エミッタ電極
の形状に対応するパターンに限定する絶縁膜及びその上
のベース・コレクタ領域を形成し、次いで、前記ベース
・コンタクト領域及びコレクタ・コンタクト層からベー
ス電極及びコンタクト電橋をそれぞれ対応して導出する
ようにしている。In the method for manufacturing a high-speed semiconductor device according to the present invention, at least a collector layer, a base layer, and an emitter layer are formed on a semi-insulating crystal substrate, an emitter electrode whose surface is made of a high melting point metal is formed, and then the emitter electrode is formed on a semi-insulating crystal substrate. Using the electrode as a mask, ions are implanted to form an insulating film that defines the collector layer in a pattern corresponding to the shape of the emitter electrode, and a base collector region thereon, and then the base contact region and the collector contact are formed. A base electrode and a contact bridge are respectively led out of the layer.
従って、前記コレクタ層は、前記絶縁膜の存在に依って
エミッタ電極と略同じパターンになっているので、従来
のこの種の高速半導体装置に比較すると著しく小面積化
され、その結果、コレクタ容量が大幅に低減されてスイ
ッチング・スピードが向上する。Therefore, since the collector layer has approximately the same pattern as the emitter electrode due to the presence of the insulating film, the area is significantly reduced compared to conventional high-speed semiconductor devices of this type, and as a result, the collector capacitance is reduced. Significantly reduced switching speeds are achieved.
第１図（Ａ）乃至（Ｄ）は本発明一実施例を説明する為
の工程要所に於ける半導体装置の要部切断側面図、第２
図は従来の高速半導体装置を説明する為の要部切断側面
図をそれぞれ表している。
図に於いて、１１は半絶縁性ＧａＡｓ基板（半絶縁性結
晶基板）、１２はｎ＋型ＧａＡｓコレクタ・コンタクト
層、１３はｎ型ＧａＡｓコレクタ層、１４はｐ＋型Ｇａ
Ａｓベース層、１５はｎ型Ａｊ！ＧａＡｓエミッタ層、
１６はｎ１型ＧａＡｓエミッタ・コンタクト層、１７は
エミッタ電極、１８は絶縁膜、１９はｐ＋型ベース・コ
ンタクト領域、２０はベース電極、２１はコレクタ電極
をそれぞれ示している。
特許出願人 富士通株式会社
代理人弁理士 相 谷 昭 司
代理人弁理士 渡 邊 弘 −
（Ａ）
第１図
（Ｂ）
（Ｃ）
（Ｄ）
第１図
従来技術に依る高速半導体装置の
要部切断側面図
第２図1A to 1D are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention;
Each figure shows a cutaway side view of a main part for explaining a conventional high-speed semiconductor device. In the figure, 11 is a semi-insulating GaAs substrate (semi-insulating crystal substrate), 12 is an n+ type GaAs collector contact layer, 13 is an n-type GaAs collector layer, and 14 is a p+ type GaAs substrate.
As base layer, 15 is n-type Aj! GaAs emitter layer,
16 is an n1 type GaAs emitter contact layer, 17 is an emitter electrode, 18 is an insulating film, 19 is a p+ type base contact region, 20 is a base electrode, and 21 is a collector electrode. Patent applicant: Fujitsu Ltd. Representative Patent Attorney: Shoji Aitani Representative Patent Attorney: Hiroshi Watanabe - (A) Figure 1 (B) (C) (D) Figure 1 Main parts of a high-speed semiconductor device based on conventional technology Cutaway side view Figure 2
Claims (1)
層及びエミッタ層を形成し、 次いで、表面が高融点金属からなるエミッタ電極を形成
し、 次いで、該エミッタ電極をマスクにイオンを注入して前
記コレクタ層を該エミッタ電極の形状に対応するパター
ンに限定する絶縁膜及びその上のベース・コンタクト領
域を形成し、 次いで、前記ベース・コンタクト領域及びコレクタ・コ
ンタクト層からベース電極及びコレクタ電極をそれぞれ
対応させて導出する工程 が含まれてなることを特徴とする高速半導体装置の製造
方法。[Claims] At least a collector layer, a base layer, and an emitter layer are formed on a semi-insulating crystal substrate, and then an emitter electrode whose surface is made of a high-melting point metal is formed, and then, ions are generated using the emitter electrode as a mask. forming an insulating film that defines the collector layer in a pattern corresponding to the shape of the emitter electrode, and a base contact region thereon; then, from the base contact region and collector contact layer, the base electrode and A method for manufacturing a high-speed semiconductor device, comprising the step of deriving collector electrodes in correspondence with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2755885A JPS61188966A (en) | 1985-02-16 | 1985-02-16 | Manufacture of high speed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2755885A JPS61188966A (en) | 1985-02-16 | 1985-02-16 | Manufacture of high speed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61188966A true JPS61188966A (en) | 1986-08-22 |
Family
ID=12224378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2755885A Pending JPS61188966A (en) | 1985-02-16 | 1985-02-16 | Manufacture of high speed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61188966A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63138774A (en) * | 1986-12-01 | 1988-06-10 | Matsushita Electric Ind Co Ltd | Manufacture of hetero junction bipolar transistor |
| JPS63263761A (en) * | 1987-04-22 | 1988-10-31 | Matsushita Electric Ind Co Ltd | Manufacture of bipolar transistor |
| JPS63263762A (en) * | 1987-04-22 | 1988-10-31 | Matsushita Electric Ind Co Ltd | Manufacture of bipolar transistor |
| JPS6447071A (en) * | 1987-08-18 | 1989-02-21 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH01175256A (en) * | 1987-12-29 | 1989-07-11 | Nec Corp | Heterostructure bipolar transistor and its manufacture |
| JPH01241166A (en) * | 1988-03-23 | 1989-09-26 | Hitachi Ltd | Bipolar transistor and manufacture thereof |
| JPH01284181A (en) * | 1988-05-11 | 1989-11-15 | Sanyo Electric Co Ltd | Automatic focusing video camera |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58111345A (en) * | 1981-12-25 | 1983-07-02 | Hitachi Ltd | Semiconductor device |
| JPS6010776A (en) * | 1983-06-30 | 1985-01-19 | Fujitsu Ltd | Manufacture of bipolar semiconductor device |
-
1985
- 1985-02-16 JP JP2755885A patent/JPS61188966A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58111345A (en) * | 1981-12-25 | 1983-07-02 | Hitachi Ltd | Semiconductor device |
| JPS6010776A (en) * | 1983-06-30 | 1985-01-19 | Fujitsu Ltd | Manufacture of bipolar semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63138774A (en) * | 1986-12-01 | 1988-06-10 | Matsushita Electric Ind Co Ltd | Manufacture of hetero junction bipolar transistor |
| JPS63263761A (en) * | 1987-04-22 | 1988-10-31 | Matsushita Electric Ind Co Ltd | Manufacture of bipolar transistor |
| JPS63263762A (en) * | 1987-04-22 | 1988-10-31 | Matsushita Electric Ind Co Ltd | Manufacture of bipolar transistor |
| JPS6447071A (en) * | 1987-08-18 | 1989-02-21 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH0620072B2 (en) * | 1987-08-18 | 1994-03-16 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JPH01175256A (en) * | 1987-12-29 | 1989-07-11 | Nec Corp | Heterostructure bipolar transistor and its manufacture |
| JPH01241166A (en) * | 1988-03-23 | 1989-09-26 | Hitachi Ltd | Bipolar transistor and manufacture thereof |
| JPH01284181A (en) * | 1988-05-11 | 1989-11-15 | Sanyo Electric Co Ltd | Automatic focusing video camera |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61121369A (en) | Semiconductor device | |
| JPH0797589B2 (en) | Method for manufacturing heterojunction bipolar transistor | |
| US5294566A (en) | Method of producing a semiconductor integrated circuit device composed of a negative differential resistance element and a FET transistor | |
| JP4182376B2 (en) | Semiconductor device | |
| JP2606581B2 (en) | Field effect transistor and method of manufacturing the same | |
| JPH11186280A (en) | Bipolar transistor and manufacture thereof | |
| JPS61188966A (en) | Manufacture of high speed semiconductor device | |
| JP2645993B2 (en) | Field effect type semiconductor device and method of manufacturing the same | |
| JP2548801B2 (en) | Field effect transistor and method of manufacturing the same | |
| JP2808145B2 (en) | Semiconductor device | |
| JP3653652B2 (en) | Semiconductor device | |
| KR910006751B1 (en) | Semiconductor integrated circuit device and its manufacturing method | |
| JPH0523497B2 (en) | ||
| JPS6252957B2 (en) | ||
| JP2503594B2 (en) | Semiconductor integrated device and manufacturing method thereof | |
| JP2616032B2 (en) | Method for manufacturing field effect transistor | |
| JPH055180B2 (en) | ||
| JPS59195874A (en) | Manufacture of field-effect transistor | |
| JPS6143443A (en) | Manufacture of semiconductor device | |
| JPS59197176A (en) | Manufacture of junction gate field-effect transistor | |
| JPS6010785A (en) | Field effect transistor and manufacture thereof | |
| JPH0666420B2 (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
| JPS62224073A (en) | Manufacture of hetero-junction bipolar transistor | |
| JPS635564A (en) | Hetero junction bipolar transistor | |
| JPH0697430A (en) | Insulated gate type field effect transistor |