JPH01241166A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To perform operation at great speed, by reducing or extinguishing an electrostatic capacity and a current which are caused by non active parts of a transistor. CONSTITUTION:Non-active parts are removed at emitter and collector layers 6 and 3 but they are left at a base layer 5. A base electrode 8 is formed at the above non active parts and etching stop layers 4 and 2 are provided at upper and lower parts of the collector layer 3. Leakage current components are distinguished by removing the non active parts and electrostatic capacity components decrease in proportion to reciprocals of relative dielectric constant. This makes it possible to operate at great speed. Further, the collector layer 3 is etched selectively with high accuracy by providing etching stop layers 4 and 2 and elements having desired characteristics are manufactured in such a manner that they are excellently reproducible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar transistor suitable for high frequency and high speed operation and a method for manufacturing the same.

[Conventional technology]

Conventionally, as a means to reduce the capacitance caused by the non-active portion of a bipolar transistor, there is a method described by IE, Electron Device Letters EDL 5.8 (1984), pp. 310 to 312' (TRHR, Electron Device). Lef
fars, EDL-5, 8 (1984) pp310-
312).

[Problem to be solved by the invention]

In the above conventional technology, since the semiconductor is depleted by ion implantation to reduce the capacitance, a large number of defects are introduced at the same time, which causes the electrical characteristics to deteriorate and the reliability to decrease. there were.

An object of the present invention is to solve the above-mentioned problem (a) and to reduce capacitance and leakage current caused by inactive parts of the emitter, base, and collector layers without deteriorating electrical characteristics.

[Means to solve the problem]

The above objective can be achieved by erasing the non-active parts of the emitter and collector layers. - an example is shown in Figure 1;
Emitter layer 6 and collector layer 3 have non-functional parts removed. A non-active portion remains in the base layer 5, and a base electrode 8 is formed in this portion.

Further, by using a manufacturing method in which the etching stop layers 4 and 2 are provided above and below the collector layer 3, the above object can be achieved.

[Effect]

By removing the inactive portion, the leakage current component disappears. Further, the capacitance component decreases in proportion to the reciprocal of the dielectric constant of the semiconductor. Therefore, high-speed operation is possible.

Further, by providing an etching stop layer, the collector layer can be selectively etched with high precision, and elements with desired characteristics can be manufactured with high reproducibility.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 Cross-sectional views of the manufacturing process of a bipolar transistor according to Example 1 of the present invention are shown in FIGS. 2(a) to 2(6).

As shown in FIG. 2(a), an n-type A Q
xG a 1-3IA 8 Lower etch stop layer 2
(x≧0, 1, n = 5 x 10"/'a
js thickness d=10 nm), n-type G a A m :I director layer 3 (n=5XIQ1B/ad, d=400 nm
), n-type AQxGat-xAs upper etch stop layer 4 (x≧O,i, n=5X1016/
cd, d = 10 nm), p-type GaAs base layer 5 (p = 4 x 10”/cd, d = 60
n m), n-type AQzGaz-mAs emitter layer 6 (n=IX1017/d, d=100
nm) are sequentially grown as crystals. Although St was used as the n-type impurity and Be was used as the p-type impurity, Sn*S#Ss was used as the n-type impurity.

Similar effects can be obtained by using Mg, Mn, Zn, C, etc. for p. It is shaped as shown in FIG. 2(b). Next, the areas other than the base region 5 which is wider by 2 μm outward than the emitter region 6 are processed in the same manner, and the etching is stopped by etching the upper etching stop layer 4 to be deeper than the lower etching stop layer 2 and shallower than the lower etching stop layer 2. (c
) into the shape shown. Next, CCQ 2 F x gas and H
Using a mixed gas of e gas, the reaction chamber pressure is 0.06 Torr.
, Ga A s for 3 minutes with bias RF power 100W
Only n 3 , 5 is selectively etched.

At this time, etching in the downward direction is blocked by the lower etching stop layer 2, and etching also progresses in the lateral direction for layers 3 and 5, which stop there, but M5 is thinner and becomes more reactive as it progresses without being etched. Due to the reduced gas supply, under the above conditions for etching layer 3 by 2 μm in the lateral direction, layer 5 is only etched by about 300 nm;
The shape shown in FIG. 2(d) is obtained. Further, after removing the photoresist 10, the emitter region and the base region are removed.

Metal or metal that can make ohmic contact with the back side of the board.
For example, AuGe alloy for n-type.

AuSn alloy, etc., and AuZn alloy for P type.

A u B e alloy etc. is deposited. This is selectively removed using a normal lift-off technique to obtain a transistor having the shape shown in FIG. 2(a). In this transistor, the part directly below the emitter region is an active part, and the other part is an inactive part. The base-collector capacitance Ctsa due to the non-active part is about 2XIO"""F/j, which is about 4% of that when the non-active part is not removed, and when the collector is depleted by ion implantation. This decreases to approximately 7.5%.

As a result, for a transistor with emitter dimensions of 2 μm x 5 μm, the CaC of the transistor of the present invention is 6.7.
X 10'''1fiF, whereas when depleted by ion implantation, it is 18.6 X i O''''ll5
F, or 31.3X1 if no special processing is performed.
0″″1! It becomes ip. The maximum cutoff frequency JT of these transistors is 45 GHz, and the maximum resistance r5 is 20 Ω. The maximum oscillation frequency f waax is expressed as a function of fT, r'b, and Cac as shown in the following equation.

f-ax=(fT/(8π rbcac))” If f max is calculated for each transistor from this, it becomes 115 GHz, 69 GHz, and 53 GHz.

The actual measurements were 108 GHz, 63 GHz, and 48 GHz, respectively, which were in good agreement with the calculations, and a significant improvement was seen by the present invention.

Embodiment 2 A bipolar transistor according to Embodiment 2 of the present invention will be explained with reference to FIG.

In Example 1, a semi-insulating GaAs substrate 1 was used instead of the n-type GaAs substrate 1, and an n-type GaAs layer 11 (n=5×10
"/cd, d=500 nm), and the same steps as in Example 1 are carried out. However, the collector electrode 9 is attached to the first surface of the substrate instead of the back surface, and a transistor having the structure shown in FIG. 3 is fabricated. Note that in the case of a zero-layer structure in which the lower etching stop layer of the collector electrode portion 9 does not necessarily need to be removed, the performance of the device is exactly the same as in Example 1, but since a semi-insulating substrate is used, a large number of devices are required. Suitable for integrating.

Embodiment 3 A bipolar transistor according to Embodiment 3 of the present invention will be explained with reference to FIG.

In Example 1 or Example 2, after the step shown in FIG. 2(a), the step shown in FIG. 2(0) was performed without going through the step shown in FIG. 2(b). The base electrode 8 was taken out by introducing an acceptor impurity into the non-active portion of the emitter layer 6 to establish electrical continuity with the base layer 5 and forming an electrode portion on one surface. Similar effects can be obtained by using any of Mg, Zn, Be, etc. as the acceptor impurity. In addition, there are two methods of introducing impurity ions: one is thermal diffusion from the surface, and the other is heat treatment at a high temperature of 600° C. or higher after impurity ions are implanted, and the same effect can be obtained by either method. Finally, a transistor having the shape shown in FIG. 4 is obtained. In this transistor, the strength of the base portion increases because the surface layer becomes thicker.

Therefore, the lateral etching depth of the collector layer 3 under the base electrode can be increased. For example, if the total thickness of the base portion is 300 nm, it is possible to etch about 3 μm in the lateral direction without impairing reliability.

Example 4 In Examples 1 to 3, the p-type GaAs base layer 5
an n-type GaAs layer 1 between the upper etching stop layer 4 and the upper etching stop layer 4;
3, or undoped GaAs layer 13' (n≦
5 x 10 work 8/al, d = 200 nm)
will be introduced. Proceed with the other steps in the same way. Then, since the depletion region from the surface of the layer 13 or 13' under the base electrode expands, no capacitance is generated there.

On the other hand, the strength of the base portion increases with increasing thickness.

Example 5 In Examples 1 to 4, pnp transistors were fabricated by changing n-type to p-type and p-type to n-type. The fr of this transistor was 30 GHz and the % f wax was 97 GHz. This is about 2
This is a two-fold improvement.

Example 6 A bipolar transistor according to Example 6 of the present invention is shown in FIG.
This will be explained with reference to a) to FIG. 5(Q).

In Examples 1 to 5, the steps shown in FIGS. 5(a) to 5(c) are performed instead of the steps shown in FIG. 2(c). That is, before the step of etching through the upper etch stop layer 4, the first protective film 14, for example, 5iOi
is deposited, and then lithography and etching are performed to form the shape shown in FIG. 5(a). Next, the protective film 15 of the rear cylinder 2 from which the photoresist has been removed is deposited, for example by Sing, to obtain the shape shown in FIG. 5(b). If this protective film 14, 15 is further etched from above by anisotropic etching, the shape shown in FIG. 5(c) can be obtained.

Subsequently, a transistor is manufactured through the selective etching and subsequent steps of Examples 1 to 5. In this case, since the side surfaces of the base layer 5 are covered with the side walls 16 formed by the second protective film 15, there is an advantage that the base layer 5 is not etched.

Both of the above embodiments use GaAs and AQGaAs.
Although the combination of materials has been described above, it is of course possible to fabricate a similar structure using the same process using other combinations of materials as long as etching with a high selectivity is possible. For example, for a combination of InP and InGaAs, a mixture of sulfuric acid, hydrogen peroxide, and water selectively etches InGaAs.

Also, hydrochloric acid, hydrogen peroxide.

The water mixture selectively etches InP.

In addition, in a combination of InGaAs and InAfiAs, InAQAs is selectively etched with hydrofluoric acid or a mixture of hydrochloric acid and water. Therefore, if these selectively etched layers are used as collector layers and blocking layers that are not etched are provided on both sides of the collector layer, a similar structure 1. Effects can be obtained.

〔Effect of the invention〕

According to the present invention, the capacitance and current caused by the non-active portion of the transistor can be reduced or eliminated, thereby enabling high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a bipolar transistor for explaining the present invention, FIG. 2 is a cross-sectional view of the manufacturing process of a bipolar transistor according to Embodiment 1 of the present invention, and FIGS. 3 and 4 are examples of the present invention. 5(a) to 5(c) are cross-sectional views of the bipolar transistors of Example 6 of the present invention. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Lower etching stop layer, 3
. . . collector layer, 4 . . . upper etching stop layer, 5 . . . base layer, 6. ...Emitter layer, 7...
Emitter electrode, 8... Base electrode, 9... Collector electrode, 10... Photoresist, 11... Collector layer, 12... Acceptor impurity doped region, 14... First protective film, 15...・・Second Part 11￥1 Part 2 (Ill”) (b) (C) 10 Netregijikutoshutoz (21 (revised) Part 3 Cause 40

Claims (1)

[Scope of Claims] 1. A base layer having an active part and a non-active part, and an emitter layer and a collector layer consisting of approximately the active part, and an overlapping area of the base layer and the non-active part of the emitter layer and the above-mentioned A bipolar transistor with a reduced overlapping area between the base layer and the non-active portion of the collector layer. 2. The bipolar transistor according to claim 1, wherein the inactive portion of the emitter layer is converted into a layer of the same conductivity type as the base layer, and a base electrode is formed on the layer. 3. A bipolar transistor manufacturing method according to claim 1, characterized in that an etching stop layer is provided sandwiching the collector layer so that other layers are not etched when the collector layer is etched. manufacturing method.