JPH01241166A - Bipolar transistor and manufacture thereof - Google Patents
Bipolar transistor and manufacture thereofInfo
- Publication number
- JPH01241166A JPH01241166A JP6736988A JP6736988A JPH01241166A JP H01241166 A JPH01241166 A JP H01241166A JP 6736988 A JP6736988 A JP 6736988A JP 6736988 A JP6736988 A JP 6736988A JP H01241166 A JPH01241166 A JP H01241166A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- collector
- base
- bipolar transistor
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000005530 etching Methods 0.000 claims abstract description 25
- 230000007423 decrease Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 46
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 8
- 239000012535 impurity Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 101000798110 Homo sapiens Thyrotropin-releasing hormone receptor Proteins 0.000 description 1
- 102100032240 Thyrotropin-releasing hormone receptor Human genes 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高周波・高速動作に好適なバイポーラトラン
ジスタとその製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar transistor suitable for high frequency and high speed operation and a method for manufacturing the same.
従来、バイポーラトランジスタの非能動部分によって生
じる静電容量を減少させる手段としてはアイ・イー・イ
ー・イー、エレクトロン デバイス レターズ イーデ
ーエル5.8(1984年)第310頁から第312頁
’(TRHR,ElectronDevice Lef
fars、 EDL−5,8(1984)pp310−
312)において論じられている。Conventionally, as a means to reduce the capacitance caused by the non-active portion of a bipolar transistor, there is a method described by IE, Electron Device Letters EDL 5.8 (1984), pp. 310 to 312' (TRHR, Electron Device). Lef
fars, EDL-5, 8 (1984) pp310-
312).
上記従来技術はイオン打ち込みにより半導体を空乏化さ
せて静電容量を減少させているために、同時に多数の欠
陥が導入され、電気的特性が劣化すると同時に信頼性が
低下するという解決すべき課題があった。In the above conventional technology, since the semiconductor is depleted by ion implantation to reduce the capacitance, a large number of defects are introduced at the same time, which causes the electrical characteristics to deteriorate and the reliability to decrease. there were.
本発明の目的は上記a題を解決し、電気的特性を劣化さ
せずにエミッタ、ベース、コレクタ層の非能動部分に起
因する静電容量、もれ電流を減少させることにある。An object of the present invention is to solve the above-mentioned problem (a) and to reduce capacitance and leakage current caused by inactive parts of the emitter, base, and collector layers without deteriorating electrical characteristics.
上記目的はエミッタおよびコレクタ層の非能動部分を消
去することによって達成できる。−例を第1図に示す、
エミッタ層6およびコレクタ層3は非能部分を除去して
いる。べ゛−ス層5には非能動部分が残っており、その
部分にベース電極8が形成されている。The above objective can be achieved by erasing the non-active parts of the emitter and collector layers. - an example is shown in Figure 1;
Emitter layer 6 and collector layer 3 have non-functional parts removed. A non-active portion remains in the base layer 5, and a base electrode 8 is formed in this portion.
また、コレクタ層3の上下にエツチングストップ層4お
よび2を設ける製造方法とすることにより、上記目的を
達成できる。Further, by using a manufacturing method in which the etching stop layers 4 and 2 are provided above and below the collector layer 3, the above object can be achieved.
非能動部分を除去することによってもれ電流成分は消滅
する。又、静電容量成分は、半導体の比誘電率の逆数に
比例して減少する。従って高速動作が可能になる。By removing the inactive portion, the leakage current component disappears. Further, the capacitance component decreases in proportion to the reciprocal of the dielectric constant of the semiconductor. Therefore, high-speed operation is possible.
また、エツチングストップ層を設けることにより、コレ
クタ層を選択的に精度良くエツチングでき、所望の特性
の素子を再現性良く製造できる。Further, by providing an etching stop layer, the collector layer can be selectively etched with high precision, and elements with desired characteristics can be manufactured with high reproducibility.
以下本発明の実施例を図を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
実施例1
、本発明の実施例1のバイポーラトランジスタの製造工
程断面図を第2図(a)〜第2図(6)に示す。Example 1 Cross-sectional views of the manufacturing process of a bipolar transistor according to Example 1 of the present invention are shown in FIGS. 2(a) to 2(6).
第2図(a)に示す様に、n型GaAs基板1(不純物
密度n == 1 x 10”/i)の上にn型A Q
xG a 1−3IA 8下部エッチストップ層2
(x≧0、1 、 n = 5 X 10”/’a
js厚さd=10nm)、n型G a A m :Iレ
クタ層3 (n=5XIQ1B/ad、d=400nm
) 、n型A Q xG a t−xA s上部エッチ
ストップ層4 (x≧O,i 、n=5X1016/
cd、 d = 10 n m) 、p型GaAsベー
ス層5 (p =4 X 10”/cd、 d =60
n m)、n型A Q zG a z−mA sエミ
ッタ層6 (n=IX1017/d、 d = 100
n m)を順次結晶成長させる。尚、n型不純物とし
てはSt、p型不純物としてはBeを用いたが、n型に
Sn* S# Ss。As shown in FIG. 2(a), an n-type A Q
xG a 1-3IA 8 Lower etch stop layer 2
(x≧0, 1, n = 5 x 10"/'a
js thickness d=10 nm), n-type G a A m :I director layer 3 (n=5XIQ1B/ad, d=400 nm
), n-type AQxGat-xAs upper etch stop layer 4 (x≧O,i, n=5X1016/
cd, d = 10 nm), p-type GaAs base layer 5 (p = 4 x 10”/cd, d = 60
n m), n-type AQzGaz-mAs emitter layer 6 (n=IX1017/d, d=100
nm) are sequentially grown as crystals. Although St was used as the n-type impurity and Be was used as the p-type impurity, Sn*S#Ss was used as the n-type impurity.
Go等、pにはMg、Mn、Zn、C等を用いても同様
の効果が得られる0次に、成長した結晶上エミッタ領域
6となる部分以外を通常のリソグラフィー及びエツチン
グを用いて加工し第2図(b)に示す形状にする。続い
てエミッタ領域6よりも2μmずつ外側に広いベース領
域5となる部分以外も同様に加工し、上部エツチングス
トップ層4より深く下部エツチングストップ層2より浅
くエツチングした特恵でエツチングを止めて第2図(c
)に示す形状にする。次にCCQ 2 F xガスとH
eガスの混合ガスを用い、反応室圧力0.06Torr
、バイアスRFパワー100Wで3分間G a A s
n 3 、5 のみを選択的にエツチングする。Similar effects can be obtained by using Mg, Mn, Zn, C, etc. for p. It is shaped as shown in FIG. 2(b). Next, the areas other than the base region 5 which is wider by 2 μm outward than the emitter region 6 are processed in the same manner, and the etching is stopped by etching the upper etching stop layer 4 to be deeper than the lower etching stop layer 2 and shallower than the lower etching stop layer 2. (c
) into the shape shown. Next, CCQ 2 F x gas and H
Using a mixed gas of e gas, the reaction chamber pressure is 0.06 Torr.
, Ga A s for 3 minutes with bias RF power 100W
Only n 3 , 5 is selectively etched.
この際下方向へのエツチングは下部エツチングストップ
層2で阻止されそこで停止する0層3及び層5に対して
は横方向にもエツチングが進むが、M5の方が薄く、エ
ツチングず進むにつれ反応性ガスの供給が少なくなるた
め、層3を横方向に2μmエツチングする上記の条件で
は層5は300nmの程度エツチングされるにすぎず、
第2図(d)に示す形状が得られる。更に、ホトレジス
ト10を除去した後、エミッタ領域、ベース領域。At this time, etching in the downward direction is blocked by the lower etching stop layer 2, and etching also progresses in the lateral direction for layers 3 and 5, which stop there, but M5 is thinner and becomes more reactive as it progresses without being etched. Due to the reduced gas supply, under the above conditions for etching layer 3 by 2 μm in the lateral direction, layer 5 is only etched by about 300 nm;
The shape shown in FIG. 2(d) is obtained. Further, after removing the photoresist 10, the emitter region and the base region are removed.
基板裏面にそれぞれオーミック接触がとれる様な金属・
例えばn型に対してはA u G e合金。Metal or metal that can make ohmic contact with the back side of the board.
For example, AuGe alloy for n-type.
AuSn合金等、P型に対してはA u Z n合金。AuSn alloy, etc., and AuZn alloy for P type.
A u B e合金等を被着させる。これを通常のりフ
トオフ技法を用いて選択的に除去し、第2図(a)に示
す形状のトランジスタを得る。このトランジスタにおい
て、エミッタ領域直下は能動部分、それ以外の部分は非
能動部分である。非能動部分に起因するベース・コレク
タ間静電容量Ctsaは約2XIO″″”F/jとなり
、非能動部分を除去しなった場合の約4%、イオン打込
みによりコレクタを空乏化させ球場合の約7.5 %に
まで小さくなる。A u B e alloy etc. is deposited. This is selectively removed using a normal lift-off technique to obtain a transistor having the shape shown in FIG. 2(a). In this transistor, the part directly below the emitter region is an active part, and the other part is an inactive part. The base-collector capacitance Ctsa due to the non-active part is about 2XIO"""F/j, which is about 4% of that when the non-active part is not removed, and when the collector is depleted by ion implantation. This decreases to approximately 7.5%.
この結果、エミッタ寸法2μm X 5μmのトランジ
スタについて本発明のトランジスタのCaCは6.7
X 10″’1fiF、これに対し、イオン打ち込みで
空乏化させた場合には18.6 X i O″″ll5
F、また、特に処理を行なわない場合には31.3X1
0″″1!ip となる。これらのトランジスタの最
大遮断周波数JTはいずれも45GHzであり、べ−大
抵抗r5はいずれも20Ωである。最大発振可能周波数
f waaxはfT、r’b 、Cacの関数として次
の式の様に表わされる。As a result, for a transistor with emitter dimensions of 2 μm x 5 μm, the CaC of the transistor of the present invention is 6.7.
X 10'''1fiF, whereas when depleted by ion implantation, it is 18.6 X i O''''ll5
F, or 31.3X1 if no special processing is performed.
0″″1! It becomes ip. The maximum cutoff frequency JT of these transistors is 45 GHz, and the maximum resistance r5 is 20 Ω. The maximum oscillation frequency f waax is expressed as a function of fT, r'b, and Cac as shown in the following equation.
f−ax= (fT/(8π rbcac))”これ
からf maXを各々のトランジスタについて計算する
と、115GHz、69GHz、53G Hzとなる。f-ax=(fT/(8π rbcac))” If f max is calculated for each transistor from this, it becomes 115 GHz, 69 GHz, and 53 GHz.
実測では各々108GHz、63GHz、48GHzと
なり計算と良く一致し1本発明により著しい向上が見ら
れた。The actual measurements were 108 GHz, 63 GHz, and 48 GHz, respectively, which were in good agreement with the calculations, and a significant improvement was seen by the present invention.
実施例2
本発明の実施例2のバイポーラトランジスタを第3図に
より説明する。Embodiment 2 A bipolar transistor according to Embodiment 2 of the present invention will be explained with reference to FIG.
実施例1においてn型GaAs基板1に替わり半絶縁性
GaAs基板1を用い、基板1と下部エツチングストッ
プ層2の間にn型G a A s層11(n=5X10
”/cd、d=500nm)を挿入し、以下実施例1と
同様の工程を経る。但し、コレクタ電極9は基板裏面で
なく1表面側に付着せしめ、第3図に示す構造のトラン
ジスタを作製する。尚、コレクタ電極部分9の下部エツ
チングストップ層は必ずしも除去しなくともよい0本構
造では素子の性能は実施例1と全く同様であるが半絶縁
性基板を用いているため、多数の素子を集積化するのに
適している。In Example 1, a semi-insulating GaAs substrate 1 was used instead of the n-type GaAs substrate 1, and an n-type GaAs layer 11 (n=5×10
"/cd, d=500 nm), and the same steps as in Example 1 are carried out. However, the collector electrode 9 is attached to the first surface of the substrate instead of the back surface, and a transistor having the structure shown in FIG. 3 is fabricated. Note that in the case of a zero-layer structure in which the lower etching stop layer of the collector electrode portion 9 does not necessarily need to be removed, the performance of the device is exactly the same as in Example 1, but since a semi-insulating substrate is used, a large number of devices are required. Suitable for integrating.
実施例3
本発明の実施例3のバイポーラトランジスタを第4図に
より説明する。Embodiment 3 A bipolar transistor according to Embodiment 3 of the present invention will be explained with reference to FIG.
実施例1あるいは実施例2において、第2図(a)の工
程の後第2図(b)の工程を経ずして第2図(0)の工
程を行なった。ベース電極8の取り出しは、エミッタ層
6の非能動部分にアクセプタ不純物を導入してベース層
5と電気的導通を取り1表面に電極部して行なった。ア
クセプタ不純物としてはMg、Zn、Be等いずれを用
いても同様の効果が得られる。又、導入方法としては表
面から熱拡散による方法と、不純物イオンを打ち込んだ
後に600℃以上の高温で熱処理する方法とがあり、い
ずれの方法によっても同様の効果が得られる。最終的に
第4図に示す形状のトランジスタが得られる。このトラ
ンジスタでは表面層が厚くなるためにベース部分の強度
が増加する。In Example 1 or Example 2, after the step shown in FIG. 2(a), the step shown in FIG. 2(0) was performed without going through the step shown in FIG. 2(b). The base electrode 8 was taken out by introducing an acceptor impurity into the non-active portion of the emitter layer 6 to establish electrical continuity with the base layer 5 and forming an electrode portion on one surface. Similar effects can be obtained by using any of Mg, Zn, Be, etc. as the acceptor impurity. In addition, there are two methods of introducing impurity ions: one is thermal diffusion from the surface, and the other is heat treatment at a high temperature of 600° C. or higher after impurity ions are implanted, and the same effect can be obtained by either method. Finally, a transistor having the shape shown in FIG. 4 is obtained. In this transistor, the strength of the base portion increases because the surface layer becomes thicker.
従ってベース電極部下コレクタ層3の横方向エツチング
深さを大きくすることができる。例えばベース部分全膜
厚を300nmとすると横方向に3μm程度は信頼性を
そこなうことなくエツチングすることが可能である。Therefore, the lateral etching depth of the collector layer 3 under the base electrode can be increased. For example, if the total thickness of the base portion is 300 nm, it is possible to etch about 3 μm in the lateral direction without impairing reliability.
実施例4
実施例1〜実施例3において、p型GaAsベース層5
と上部エツチングストップ層4の間にn型GaAs層1
3、あるいはアンドープG a A s層13’(n≦
5 X 10工8/al、 d = 200 n m)
を導入する。他は同様に工程を進める。すると層13あ
るいは13′のベース電極下の部分は表面からの空乏領
域が広がるために静電容量をここに生じることが無い。Example 4 In Examples 1 to 3, the p-type GaAs base layer 5
an n-type GaAs layer 1 between the upper etching stop layer 4 and the upper etching stop layer 4;
3, or undoped GaAs layer 13' (n≦
5 x 10 work 8/al, d = 200 nm)
will be introduced. Proceed with the other steps in the same way. Then, since the depletion region from the surface of the layer 13 or 13' under the base electrode expands, no capacitance is generated there.
一方ベース部分の強度は厚みの増大と共に増加する。On the other hand, the strength of the base portion increases with increasing thickness.
実施例5
実施例1〜実施例4でn型とあるところをp型に、p型
とあるところをn型に変えて、pnp型トランジスタを
作製した。このトランジスタのfrは30GHzであり
% f waxは97 G Hzとなった。これは約2
倍の改善である。Example 5 In Examples 1 to 4, pnp transistors were fabricated by changing n-type to p-type and p-type to n-type. The fr of this transistor was 30 GHz and the % f wax was 97 GHz. This is about 2
This is a two-fold improvement.
実施例6
本発明の実施例6のバイポーラトランジスタを第5図(
a)〜第5図(Q)により説明する。Example 6 A bipolar transistor according to Example 6 of the present invention is shown in FIG.
This will be explained with reference to a) to FIG. 5(Q).
実施例1〜実施例5において、第2図(c)の工程に代
えて第5図(a)〜第5図(c)の工程を行なう。すな
わち、上部エッチストップ層4を突き抜けてエツチング
を行なう工程の前に第1の保護膜14、例えば5iOi
を付着せしめ、その後リソグラフィー及びエツチングを
行なって第5図(a)の形状に加工する。次にホトレジ
ストを除去した後筒2の保護膜15を例えはSing付
着せしめ、第5図(b)に示す形状を得る。この保護膜
14.15を更に上方より異方性エツチングによりエツ
チングすると第5図(c)の形状を得ることができる。In Examples 1 to 5, the steps shown in FIGS. 5(a) to 5(c) are performed instead of the steps shown in FIG. 2(c). That is, before the step of etching through the upper etch stop layer 4, the first protective film 14, for example, 5iOi
is deposited, and then lithography and etching are performed to form the shape shown in FIG. 5(a). Next, the protective film 15 of the rear cylinder 2 from which the photoresist has been removed is deposited, for example by Sing, to obtain the shape shown in FIG. 5(b). If this protective film 14, 15 is further etched from above by anisotropic etching, the shape shown in FIG. 5(c) can be obtained.
続いて、実施例1〜5の選択性エツチング以降の工程を
経てトランジスタを作製する。この場合ベース層5の側
面が第2の保護膜15によって形成された側壁16で覆
われている為、ベース層5に対してエツチングが行なわ
れない利点がある。Subsequently, a transistor is manufactured through the selective etching and subsequent steps of Examples 1 to 5. In this case, since the side surfaces of the base layer 5 are covered with the side walls 16 formed by the second protective film 15, there is an advantage that the base layer 5 is not etched.
上記の実施例はいずれもG a A sとAQGaAs
の材料の組み合わせについて述べたが、これ以外の材料
の組み合わせについても選択比の大きいエツチングが可
能であれば全く同様の工程で同様の構造を作製し得るの
は勿論のことである。例えば、InPとInGaAsの
組み合わせについては、硫酸、過酸化水素、水の混合液
はI n G a A sを選択的にエツチングする。Both of the above embodiments use GaAs and AQGaAs.
Although the combination of materials has been described above, it is of course possible to fabricate a similar structure using the same process using other combinations of materials as long as etching with a high selectivity is possible. For example, for a combination of InP and InGaAs, a mixture of sulfuric acid, hydrogen peroxide, and water selectively etches InGaAs.
又、塩酸、過酸化水素。Also, hydrochloric acid, hydrogen peroxide.
水の混合液はInPを選択的にエツチングする。The water mixture selectively etches InP.
他にもI n G a A sとI nAfiAsの組
み合わせではI nAQAsがフッ酸、あるいは塩酸と
水の混合物で選択的にエツチングされる。そこで、これ
らの選択的にエツチングされる層をコレクタ層とし、そ
の両側にエツチングされない阻止層を設ければ、同様の
構造1.効果が得られる。In addition, in a combination of InGaAs and InAfiAs, InAQAs is selectively etched with hydrofluoric acid or a mixture of hydrochloric acid and water. Therefore, if these selectively etched layers are used as collector layers and blocking layers that are not etched are provided on both sides of the collector layer, a similar structure 1. Effects can be obtained.
本発明によれば、トランジスタの非能動部分に起因する
静電容量及び電流を減少あるいは消滅させ得るので高速
動作が可能になる。According to the present invention, the capacitance and current caused by the non-active portion of the transistor can be reduced or eliminated, thereby enabling high-speed operation.
第1図は本発明を説明するためのバイポーラトランジス
タの断面図、第2図は本発明の実施例1のバイポーラト
ランジスタの製造工程断面図、第3図および第4図は各
々本発明の実施例2および実施例3のバイポーラトラン
ジスタの断面図、第5図(a )〜第5図(c)は本発
明の実施例6のバイポーラトランジスタの製造工程断面
図である。
1・・・基板、2・・・下部エツチングストップ層、3
・・・コレクタ層、4・・・上部エツチングストップ層
、5・・・ベース層、6.・・・エミッタ層、7・・・
エミッタ電極、8・・・ベース電極、9・・・コレクタ
電極、10・・・ホトレジスト、11・・・コレクタ層
、12・・・アクセプタ不純物導入領域、14・・・第
1保護膜、15・・・第2第 11¥1
第 2 の
(Ill”)
(b)
(C)
10 ネトレジ゛久ト
早z(21
(改)
第 3因
茅40FIG. 1 is a cross-sectional view of a bipolar transistor for explaining the present invention, FIG. 2 is a cross-sectional view of the manufacturing process of a bipolar transistor according to Embodiment 1 of the present invention, and FIGS. 3 and 4 are examples of the present invention. 5(a) to 5(c) are cross-sectional views of the bipolar transistors of Example 6 of the present invention. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Lower etching stop layer, 3
. . . collector layer, 4 . . . upper etching stop layer, 5 . . . base layer, 6. ...Emitter layer, 7...
Emitter electrode, 8... Base electrode, 9... Collector electrode, 10... Photoresist, 11... Collector layer, 12... Acceptor impurity doped region, 14... First protective film, 15...・・Second Part 11¥1 Part 2 (Ill”) (b) (C) 10 Netregijikutoshutoz (21 (revised) Part 3 Cause 40
Claims (1)
略能動部分から成るエミッタ層およびコレクタ層を有し
、上記ベース層と上記エミッタ層の非能動部分の重なり
面積および上記ベース層と上記コレクタ層の非能動部分
の重なり面積を小さくしたバイポーラトランジスタ。 2、上記エミッタ層の非能動部分は上記ベース層と同一
導電型の層に変換されており、該層上にベース電極が形
成されている特許請求の範囲第1項記載のバイポーラト
ランジスタ。 3、特許請求の範囲第1項記載のバイポーラトランジス
タの製造方法において、コレクタ層を挾んでエッチング
ストップ層を設けておき、該コレクタ層のエッチング時
に他の層がエッチングされないことを特徴とするバイポ
ーラトランジスタの製造方法。[Scope of Claims] 1. A base layer having an active part and a non-active part, and an emitter layer and a collector layer consisting of approximately the active part, and an overlapping area of the base layer and the non-active part of the emitter layer and the above-mentioned A bipolar transistor with a reduced overlapping area between the base layer and the non-active portion of the collector layer. 2. The bipolar transistor according to claim 1, wherein the inactive portion of the emitter layer is converted into a layer of the same conductivity type as the base layer, and a base electrode is formed on the layer. 3. A bipolar transistor manufacturing method according to claim 1, characterized in that an etching stop layer is provided sandwiching the collector layer so that other layers are not etched when the collector layer is etched. manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63067369A JP2667863B2 (en) | 1988-03-23 | 1988-03-23 | Manufacturing method of bipolar transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63067369A JP2667863B2 (en) | 1988-03-23 | 1988-03-23 | Manufacturing method of bipolar transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01241166A true JPH01241166A (en) | 1989-09-26 |
JP2667863B2 JP2667863B2 (en) | 1997-10-27 |
Family
ID=13343030
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63067369A Expired - Fee Related JP2667863B2 (en) | 1988-03-23 | 1988-03-23 | Manufacturing method of bipolar transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2667863B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5485025A (en) * | 1994-12-02 | 1996-01-16 | Texas Instruments Incorporated | Depleted extrinsic emitter of collector-up heterojunction bipolar transistor |
US6147371A (en) * | 1997-12-22 | 2000-11-14 | Nec Corporation | Bipolar transistor and manufacturing method for same |
JP2009253022A (en) * | 2008-04-07 | 2009-10-29 | Sony Corp | Method of manufacturing semiconductor device |
JP2019135766A (en) * | 2012-06-14 | 2019-08-15 | スカイワークス ソリューションズ, インコーポレイテッドSkyworks Solutions, Inc. | Power amplifier modules including tantalum nitride terminated through-wafer via and related systems, devices and methods |
US11984423B2 (en) | 2011-09-02 | 2024-05-14 | Skyworks Solutions, Inc. | Radio frequency transmission line with finish plating on conductive layer |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61188966A (en) * | 1985-02-16 | 1986-08-22 | Fujitsu Ltd | Manufacture of high speed semiconductor device |
JPS625660A (en) * | 1985-07-02 | 1987-01-12 | Matsushita Electric Ind Co Ltd | Hetero junction bipolar transistor and manufacture thereof |
JPS6218761A (en) * | 1985-07-18 | 1987-01-27 | Matsushita Electric Ind Co Ltd | Hetero junction transistor and manufacture thereof |
-
1988
- 1988-03-23 JP JP63067369A patent/JP2667863B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61188966A (en) * | 1985-02-16 | 1986-08-22 | Fujitsu Ltd | Manufacture of high speed semiconductor device |
JPS625660A (en) * | 1985-07-02 | 1987-01-12 | Matsushita Electric Ind Co Ltd | Hetero junction bipolar transistor and manufacture thereof |
JPS6218761A (en) * | 1985-07-18 | 1987-01-27 | Matsushita Electric Ind Co Ltd | Hetero junction transistor and manufacture thereof |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5485025A (en) * | 1994-12-02 | 1996-01-16 | Texas Instruments Incorporated | Depleted extrinsic emitter of collector-up heterojunction bipolar transistor |
US6147371A (en) * | 1997-12-22 | 2000-11-14 | Nec Corporation | Bipolar transistor and manufacturing method for same |
US6426266B1 (en) | 1997-12-22 | 2002-07-30 | Nec Corporation | Manufacturing method for an inverted-structure bipolar transistor with improved high-frequency characteristics |
JP2009253022A (en) * | 2008-04-07 | 2009-10-29 | Sony Corp | Method of manufacturing semiconductor device |
JP4721017B2 (en) * | 2008-04-07 | 2011-07-13 | ソニー株式会社 | Manufacturing method of semiconductor device |
US8148238B2 (en) | 2008-04-07 | 2012-04-03 | Sony Corporation | Method of manufacturing semiconductor device |
US8288247B2 (en) | 2008-04-07 | 2012-10-16 | Sony Corporation | Method of manufacturing semiconductor device |
US11984423B2 (en) | 2011-09-02 | 2024-05-14 | Skyworks Solutions, Inc. | Radio frequency transmission line with finish plating on conductive layer |
JP2019135766A (en) * | 2012-06-14 | 2019-08-15 | スカイワークス ソリューションズ, インコーポレイテッドSkyworks Solutions, Inc. | Power amplifier modules including tantalum nitride terminated through-wafer via and related systems, devices and methods |
Also Published As
Publication number | Publication date |
---|---|
JP2667863B2 (en) | 1997-10-27 |
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