JPS58111345A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce parasitic capacitance through reduction of PN junction area and increase degree of freedom of structure by electrically isolating semiconduictor elements with an SiO2 film obtained by the implantation of oxygen ion. CONSTITUTION:An example of insulatingly isolating a substrate and buried layer is explained. A mask 9 is provided on the surface of P type Si substrate 1 and the surface is annealed by implanting the oxygen ion 10. At this time, an implanting accelerating voltage is 150KV and a depth from the substrate surface is about 400nm. An SiO2 8 is formed in the substrate by this process. Next, a donor impurity such as Sb is introduced into a thin Si film 11 on the oxide film 8. Thereafter, the mask 9 is removed and an N type Si layer 3 is epitaxially grown on the entire part thereof. In this process, an N<+> buried layer 2 is formed simultaneously. Succeedingly, each element region is formed by the ordinary process. Since the substrate 1 is isolated by the SiO2 film 8 from the buried layer 2, a parasitic capacitance is reduced as much. In addition to the above example, this method can be adopted to various processes.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device using a semiconductor oxide film forming technique by implanting A12 elementary ions.

The current most common bipolar NPN) transistor structure, as shown in the cross-sectional view in FIG.
A type 8i layer 3 is formed, and this N type 5iJi3t' isolation is separated into several regions by the P type layer 4, and a part of one separated N type 8i layer 3 is used as a collector. @8i layer 30 layer surface 0 surface KP type region is diffused to use a part of it as a base, N+ type region 6 is diffused to the other surface of the P region to serve as an emitter, and a part of the N type 8i layer 30 surface is used as an emitter. The part KN+ type region 7 is diffused to form a collector extraction part.

In the bibolar NPN) transistor, the parasitic capacitance 0□ generated at the emitter-base junction, the parasitic capacitance OTC' generated at the pace-collector junction, and the junction capacitance between the N''m buried layer and the P-type substrate 07. are small in total. First, there are problems with the high-frequency characteristics and high-speed performance of transistors.The only way to reduce these parasitic capacitances by reducing the junction area is to reduce the dimensions of the transistor elements. Difficult in processing.

When a large number of bipolar elements are assembled on one semiconductor chip to form an integrated circuit (10), the wiring between the elements becomes complicated and multilayer wiring is unavoidable. When attempting to provide this, internal wiring is difficult due to the presence of multiple PN junctions in the semiconductor layer as described above.

When used for the I/CM selective oxide film oxide film 1 layer, the P substrate and N
The ++-containing layer has a reverse bias junction separation structure, which is undesirable in terms of high speed, leakage current to the substrate, and noise.

The present invention attempts to solve the various problems in the prior art described above by utilizing oxygen ion implantation technology.

Therefore, one object of the present invention is to reduce the capacitance of a bipolar element, and another object of the present invention is to increase the speed and reduce the noise associated with the bipolar element.
This results in an increase in the degree of freedom in wiring.

The present invention will be described in detail below with reference to some examples.

Embodiment 1 FIG. 2 is a sectional view of a bipolar semiconductor device showing the basic structure of the present invention. As shown in the figure, k, P type substrate 1 and N
A semiconductor oxide film (8i0.) 8 is formed by implanting oxygen ions into a P-type substrate on the bonding surface with the ++-filled layer 2, and an epitaxial N layer 3 is formed on this via the N++-filled layer 2.
5. A PfIi region serving as a base on the surface of the 8 layer 30. A bipolar NPN transistor is constructed by forming an N+ type region 67 serving as an emitter and collector.

FIG. 3 shows an example of the manufacturing process of the bipolar NPN transistor (at to el), each step (a) to (e) VC.

(al High resistivity P-type 81 substrate 1 (crystal plane (10
0).

A mask 9 made of a surface Kili film or the like having a specific resistance of 1.800 Ω·cm) is provided, and oxygen ions 10 are implanted and annealed. Implant acceleration voltage is 150KV or higher,
Dose amount is 1.2X10"Ca1-", implantation depth is 8
It is approximately 400 nm Q degrees from the i surface. Annealing temperature is 9
00 to 1150°C for 2 hours or more.

(bl) In the above step, an oxide film 8 is formed by annealing, and a thin St (single crystal) film 11 remains on this oxide film. Donor impurities such as Ksb are deposited on the surface of this thin 8i film.

(cl 8b deposit) Remove the mask such as the oxide film used in K and epitaxially grow 81 on the 8i base substrate surface including the thin 8i film 11 to a thickness of 10 μm or more KN type doped St layer 34 'Form. Due to this N-type 81 layer growth, the oxide film 8 of the PfJ substrate 1 and the NWWB 2
During this period, a KN+ trench embedment is formed.

(d) By the usual isolation process, 8
An isolene 1 layer 2 layer 4 is formed between the layer 3 and the P substrate 1, and B (boron) is selectively diffused into a part of the surface of the N layer to form a P region 5 serving as a base.

(e) Perform selective diffusion of As (arsenic) or P (IJ) to form the N that becomes the entrance and collector extraction part.
+ regions 6 and 7 are formed, contact photoetching is performed on the surface oxide film 12 used as a diffusion mask, and kl
Electrodes B, E, which contact each area by vapor deposition.
Form O.

Example 2 FIG. 4 (at (bl) is a process sectional view showing a modification of Example 1.

(1) After step (b) of Example 1, 3 m of N11B1 layer was grown by epitaxial growth to a thickness of <(5 to 1 m) thinner than usual.
0 μm), and then an oxide film 13 is formed near the surface of the Nilai layer 3m by oxygen ion implantation and annealing.

(bl) Next, a second NfflSi layer 3b is layered on the entire surface by second epitaxial growth, the P type base 5 is diffused, the N+ type 2 vines 6 and the N+ type collector extraction part 7 are formed.
is formed by diffusion. Oxygen ions are implanted near the surface of the two-i ivy junction and annealing is performed to form an oxide film 14. Thereafter, although not shown, contact photoetching is performed on the surface rMtIt film, and electrodes contacting each region are formed by Aj vapor deposition photoetching.

According to the present invention described in Example 1.2 above, since an enhanced film is formed by oxygen ion implantation on the junction surface between the N+ buried layer and the P type substrate, the parasitic capacitance 07 at least on this junction surface is
．． can be reduced without changing the planar dimensions of current bipolar transistors. Also, Figure 4 (a) (
b) Oxide film 8. 13. By forming 14, the effect of preventing thyristors can be obtained.

According to the present invention described in Embodiment 2, the wII element is formed between the P substrate 10 of the N+ trench embedding 2, between the kP base and the 8th layer, and in a part of the bonding surface between the Njyukuki vine and the base. Since the oxide films 8, 13 and 14 are formed by ion implantation, the parasitic capacitance at these junction surfaces is 0. c, 0□ can be reduced without changing the plane dimensions of the transistor, high frequency characteristics and high speed can be obtained, and high performance circuits can be obtained by applying it to IIL technology, for example. This provides excellent noise characteristics and low noise characteristics.

Embodiment 3 FIGS. 5 (at to (bl) show the case where the present invention is applied to an isoplanar transistor according to its process.

tat Oxygen ions are implanted into the entire surface of the high resistivity substrate 1 and annealed. The implantation acceleration voltage, dose amount, implantation depth, and annealing temperature are the same as or close to those in Example 1.

(b) In the above process, an oxide film 8 is formed near the surface of the Si jiI plate 10, and a thin 81 film 1 is formed on this oxide film.
1 remains. The surface (part or all) of this thin 81 film 11
A donor impurity for forming the N+ trench 2 is deposited, and then a low resistivity Nff18 is formed by epitaxial growth.
One layer 3 is formed to a thickness of 5 to 10 μm 8i degrees.

(Cl N11 layer 30 surface part K 8 i, N
An oxidation-resistant film 15 such as No. 4 is formed, and using this as a mask, parts where the oxidation-resistant film is not formed are selectively oxidized in an oxidizing atmosphere to form an isolation oxide film 16 that reaches oxidation j[8 on the substrate surface. .

(di) After this, selective diffusion is performed by a process similar to the conventional bipolar element manufacturing process.
Mold base 5. After forming an N+ type machining tip 6 and an N1 type collector extraction portion 7, and contact photoetching of the surface oxide film, an isoplanar type bipolar NPN transistor is obtained through a non-deposition layer.

According to the present invention described in the above embodiments, the following effects can be obtained.

Conventional high-speed isoplanar bipolar devices have an insulation isolation structure using a selective oxide film between the devices, but reverse bias junction isolation is used between the substrate and the N+ buried layer that becomes the collector, which improves high-speed performance. This is undesirable in terms of leakage current to the circuit board and noise. However, when an oxide film 8 is formed between the substrate 1 and the N+ trench 2 using oxygen ion implantation technology, a completely isolated structure is created. is almost gone,
It is possible to achieve higher speed ratio and lower noise of the element.

Embodiment 4 Figures 6(al) to (e) show an example of forming a multilayer diffusion wiring by insulating and separating the upper layer and the lower layer using the cumulative ion implantation technique in accordance with the process. be.

(a) Oxide film 1 on the surface of high resistivity PII81 substrate 1
N+ diffusion wiring 18 is formed by selective diffusion using 7 as a mask.

(bl St) By implanting oxygen ions into the surface of the substrate 1 and then performing an annealing treatment, an oxide film 8 is formed at a slightly deeper portion from the substrate surface.

(cl) A low resistivity N-type 81 layer 3 is formed by epitaxial growth on the thin Si layer 11 remaining on the oxide film 8.

(dlN 118 Selective oxidation is performed on the surface of the i layer 3 using the oxide film 19 as a mask, and the PIN diffusion layers 20m, 2
0b and a part (20a) thereof as the lower layer wiring a (or resistance), in addition to the P type diffusion layer, the W (20b) surface kN+ diffusion layer 21 is formed and this is used as another wiring (or resistance). shall be.

tel Contact photoetch is performed on the oxide film on the surface, and the P diffusion layer or N
+ Upper layer all (or resistance) arrangement using a diffusion layer @Aj
At the same time as forming the terminals 22, the Aj arrangement 123 on the surface is formed.

FIG. 7 shows the arrangement and extraction structure from the lower layer diffusion wiring shown in FIG. 6(e). That is, lower layer N+diffused distribution I! 118, an epitaxial N layer 3 is formed on the P substrate 1, and an N+ diffusion arrangement 118kl! is formed from the surface of the N layer 30. Continuing N+ collector diffusion (ON) layer 24
is formed to serve as an N+ diffusion wiring extraction layer to the surface. N+
The epitaxial N layer 3 surrounding the diffusion wiring extraction layer 24 is provided with an isolation P layer 25 that reaches from the surface to the P substrate to provide insulation isolation between the eyebrows of each wiring extraction.

According to the present invention #4 described in the above embodiment, the following effects can be obtained.

In the conventional bipolar structure, the interior of the P substrate and epitaxial N layer is structurally restricted to the extent that bias separation is performed at PH1, making it difficult to realize multilayer wiring inside the semiconductor.

However, according to the present invention, the semiconductor layer is completely insulated and separated into an upper layer and a lower layer using an 8i0° film formed inside the semiconductor by implanting oxygen ions as an insulating film. An activity club can be formed. Therefore, according to the present invention, the degree of freedom in wiring is greatly increased, and complex wiring becomes possible within a narrow chip.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an example of the structure of a bipolar transistor. FIG. 2 is a sectional view showing the principle structure of a polar transistor according to the present invention.
(@) and FIGS. 4(a) and 4(b) are cross-sectional views of a part of the process corresponding to Example 1 and Example 2 of the present invention, and FIGS. 5(a) to (d) are Example 3 of the invention
A process cross-sectional diagram showing part of the process corresponding to Fig. 6 (
1) to (e) and FIG. 7 are process sectional views showing a part of the process corresponding to Example 4 of the present invention. 1...Pal semiconductor substrate, 2...N+ trench embedding, 3.
...NtIist layer, 4...Einlasi training P71
．． 5...Pace P area, 6...Ivy N+ area,
7... Collector N+ region, 8... Oxide film by oxygen ion implantation K, 9... Oxide film mask, 10... Oxygen implantation, 11... Thin 81 film, 12... Surface oxide film , 13.14...Oxide film by oxygen ion implantation, 1
5... Oxidation resistant film, 16... Isolation carbon oxide film, 17... Oxide film mask, 18... Diffusion wiring, 1
9... Oxide film, 2one20b... P-type diffusion layer, 2
1... NW diffusion wiring, 22... Aj terminal, 23...
・A! Wiring, 24... Collector diffusion layer, 25... Eitzley Sheen P layer. Agent Patent Attorney Susuki 1) Toshiyuki... −・. 1 Nonojiku 1 Figure 2 Figure 3 Figure 3 Figure 3 , 4f'21 Figure 6 Figure 6 Figure 7

Claims (1)

[Claims] 1. A second conductivity type semiconductor layer is formed on a first conductivity type semiconductor substrate, a part of which is used as a collector, and a first conductivity type semiconductor layer is formed on the other surface of the second conductivity type conductor layer. In a semiconductor device in which a transistor is configured by forming a region and using a part of the region as a base, and forming a second conductive leakage region on the S surface in addition to the armpit second conductivity type region to serve as an emitter, the first conductivity type semiconductor substrate and A semiconductor device characterized in that a semiconductor oxide film is formed on a bonding surface with a second conductivity type semiconductor layer by implanting oxygen ions into the semiconductor substrate. 2. Forming a second conductivity type semiconductor layer on the first conductivity type semiconductor substrate, using a part of the second conductivity type semiconductor layer as a collector, and forming a first conductivity type region on the other surface of the second conductivity type semiconductor layer. A semiconductor device constitutes a transistor in which a second conductive type region is formed as a base and a second conductive type region is formed on the other surface of the second conductive type region to serve as an emitter. The bonding surface with the semiconductor layer, part of the bonding surface between the second conductive type semiconductor layer and the first conductive region serving as the base, and the bonding surface between the first conductive type region and the second conductive type region serving as the emitter. -ISK
To semiconductor substrates and semiconductor layers! 1. A semiconductor device characterized in that a semiconductor oxide film is formed by implanting l-ion atoms. 3. Forming a second conductive type semiconductor layer on the first conductive type semiconductor substrate, forming a first conductive temperature region on a part of the surface of the second conductive type semiconductor layer and using the part as a wiring, and In a semiconductor device in which a second conductive clear region is formed on the other surface of the second conductive type region to form a wiring, a ridge is formed on the bonding surface between the first conductive type semiconductor substrate and the second conductive type semiconductor layer. A semiconductor device characterized in that a semiconductor oxide film is formed by implanting oxygen ions, and a wiring made of a highly concentrated buried layer of a second conductivity type is formed on a part of the surface of a semiconductor substrate under the oxide layer.