JPH02165679A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a one-dimensional channel having excellent characteristics by alternately piling first semiconductor layers and second semiconductor layers having a smaller electron affinity by a vapor growth method on a region having a specified crystal face orientation in a protruding shape so that the area of the upper layer becomes smaller than the lower layers. CONSTITUTION:First semiconductor layers 3 and a second semiconductor layer 4 having a smaller electron affinity than the first layer are alternately piled on a region 1a having a specified crystal face orientation that is formed on a semiconductor GaAs substrate 1 by a vapor growth method in a protruding shape so that the area of the upper layers becomes small than the lower layers. When a third semiconductor layer 5 incorporating impurities whose electron affinity is smaller than that in the first semiconductor layer 3 is formed on the first and second semiconductor layers 3 and 4, electrons are supplied from the third semiconductor layer 5 into the first semiconductor layer 3. Thus one- dimensional electrons are formed in the first semiconductor layer. A one- dimensional channel is formed by said one-dimentional electrons. In this way, the one-dimensional channel having the excellent characteristics can be formed readily and positively.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular,
It is suitable for application to a semiconductor device having a -dimensional channel structure.

[Summary of the Invention] In the present invention, a region with a predetermined crystal plane orientation is selectively formed on a semiconductor substrate, and a first semiconductor layer and a first semiconductor layer are formed on the region with a predetermined crystal plane orientation. and a second semiconductor layer having a smaller electron affinity than the second semiconductor layer are alternately stacked by vapor phase growth in a convex shape in which the upper layer has a smaller area. As a result, a quantum well wire is formed, and a one-dimensional channel is formed by this quantum well wire. When forming a third semiconductor layer containing an impurity whose electron affinity is smaller than that of the first semiconductor layer on the first and second semiconductor layers, the third semiconductor layer is formed on the first and second semiconductor layers.
Electrons are supplied from the semiconductor layer into the first semiconductor layer to form one-dimensional electrons in the first semiconductor layer, and a one-dimensional channel is formed by the -dimensional electrons. According to the present invention, it is possible to realize a FET with a -dimensional channel structure and a quantum interference type semiconductor device with a multi-channel structure.

[Conventional technology]

In recent years, semiconductor devices having a -dimensional channel have attracted attention. Semiconductor devices with this -dimensional channel have the problem of so-called Anderson localization, in which the electron wave function may become localized if the localized potential exceeds a certain limit value, but the localized potential < kT (However, k is Boltzmann's constant and T is absolute temperature.) Operation is possible under the following conditions.

In a one-dimensional channel, the electron states after scattering are limited, so the scattering probability of electrons is extremely small, and a significant increase in electron mobility μ is expected. Therefore, attempts have been made to form this -dimensional channel. One such method is to form a one-dimensional channel using lithography using an electron beam or the like. According to this method, it is possible to form a one-dimensional channel with a width of about 200 people, but it is currently difficult to form a one-dimensional channel with a width smaller than that. Furthermore, if a large number of one-dimensional channels are formed adjacent to each other using this method, there is a drawback that the width becomes wide due to the so-called proximity effect, and it is not possible to narrow the spacing. Furthermore, this method has the disadvantage that damage is likely to occur when forming a one-dimensional channel by reactive ion etching (RIE) or the like.

FIG. 10 shows a conventional one-dimensional channel structure.

As shown in FIG. 10, in this example, AlXGa, -1
lAs layer 102, aluminum arsenide (AIAs) layer 10
3. GaAsJii 104 and AlAs layer 103 are sequentially formed. These AlxGa, -x Asl
102, AlAs71103 and GaAsJi 10
A groove 105 is formed in the V groove 105, and a gate voltage ti+106 is formed in this V groove 105. In this example, one-dimensional electrons are formed in the GaAs layer 104 at the interface with the gate electrode 106, and a one-dimensional channel is formed by these -dimensional electrons.

On the other hand, the conventional one-dimensional channel structure shown in FIG.
After patterning the As layer 102 by etching, an AIX Gap layer 107 is formed on the side surfaces of the As layer 102.

A gate electrode 106 is formed on a Ga, -xAs layer 107. In this example, AIX Ga1-xAs layer 1
GaA at the hetero interface between 07 and GaAs layer 104
One-dimensional electrons formed in the s-layer 104 form a one-dimensional channel.

Furthermore, a one-dimensional channel structure as shown in Fig. 12 is also known (^pp1. Phys, Lett, 4
1(7).

1982, pp. 635-638). As shown in FIG. 12, in this example, an AI layer is formed on a semi-insulating GaAs substrate 101.

Ga+-xAs (X""0, 25) layer 10
2 and GaAsJi 104 are alternately stacked on the entire surface, and these GaAs layers 104 and A11l Ga, -, As
After forming a mesa structure having a triangular cross-sectional shape by processing the layer 102 using photolithography and chemical etching, semi-insulating A1. Ga1-, As (
x-0,31) layer 108 is formed. In this example,
AlXGa+-x As1N 102 as barrier layer
, 108, a one-dimensional channel is formed within the quantum well wire consisting of a GaAs layer 104 surrounded by .

However, in the conventional one-dimensional channel structures shown in FIGS. 1O, 11, and 12, the surface of the GaAs layer 104 where -dimensional electrons are formed is exposed to the atmosphere during manufacturing. , the disadvantage is that the properties of this surface are degraded, resulting in a deterioration of the properties of the -dimensional channel. Furthermore, the example shown in FIG. 12 has the disadvantage that it is not necessarily easy to form a mesa structure having a triangular cross-sectional shape.

[Problem to be solved by the invention]

As described above, with the conventional techniques, it is difficult to obtain a one-dimensional channel with good characteristics.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can obtain a one-dimensional channel with good characteristics.

The above objectives and other objectives will become clear from the following description.

[Means to solve the problem]

In order to achieve the above object, the present invention is configured as follows.

The invention of claim 1 provides a method for manufacturing a semiconductor device, including the steps of selectively forming a region (1a) with a predetermined crystal plane orientation on a semiconductor substrate (1);
a) a first semiconductor layer (3) on top and a first semiconductor layer (3) on top;
The invention of claim 2 is characterized by a step of alternately stacking second semiconductor layers (4) having a smaller electron affinity than the first semiconductor layer (4) by vapor phase growth in a convex shape in which the upper layer has a smaller area. In the invention of 1, the region (1a) having a predetermined crystal plane orientation is a region having a (001) plane orientation, and the vapor phase growth of the first and second semiconductor layers (3, 4) is performed using a trimethyl compound-based raw material. This is done using

The invention of claim 3 provides a step of selectively forming a region (1a) with a predetermined crystal plane orientation on a semiconductor substrate (1), and a step of forming a first semiconductor layer on the region (1a) with a predetermined crystal plane orientation. (3) and a second semiconductor layer (4) having a smaller electron affinity than the first semiconductor layer (3) are alternately laminated by vapor phase growth in a convex shape in which the area becomes smaller as the upper layer increases; A step of forming a third semiconductor layer (5) containing impurities and having a lower electron affinity than the first semiconductor layer (3) by vapor phase growth so as to cover the convex portion. According to a fourth aspect of the present invention, in the third aspect of the present invention, the third semiconductor layer (5) is grown in a vapor phase using a triethyl compound-based raw material.

The invention of claim 5 provides a semiconductor device in which the first semiconductor layers (
3) and a second semiconductor layer (4) having a lower electron affinity than this first semiconductor layer (3), and a first semiconductor layer containing an impurity formed so as to cover the convex portion; (
3), and a gate electrode (G) formed on the third semiconductor layer (5).
) and a channel formed in the first semiconductor layer (3) at the hetero interface between the first semiconductor layer (3) and the third semiconductor layer (5), In the invention of claim 5, in the invention of claims 1 to 6, wherein the channel is a multi-channel, the method for selectively forming the region (1a) with a predetermined crystal plane orientation includes forming a semiconductor with a predetermined crystal plane orientation. The surface of the base (1) is partially coated with an insulating film (2).
) or a semiconductor substrate with a predetermined crystal plane orientation (1)
A method of partially etching can be used.

[Effect]

According to the invention of claim 1, it is possible to easily form a thin quantum well wire made of the first semiconductor layer (3) on the region (1a) with a predetermined crystal plane orientation without using advanced etching technology or the like. can. Thereby, a one-dimensional channel can be easily formed using this quantum well thin wire.

According to the invention of claim 2, the region (1
a) The first and second semiconductor layers (3°4) can be easily and selectively grown thereon.

In addition, since vapor phase growth is performed using a trimethyl compound-based raw material, the growth automatically starts when the first and second semiconductor layers (3, 4) are alternately stacked and the apex is formed. Stop. Therefore, the first and second semiconductor layers (3, 4
) can be reliably formed into a convex shape. Thereby, a -dimensional channel can be easily and reliably formed.

According to the invention of claim 3, since electrons are supplied from the third semiconductor layer (5) into the first semiconductor layer (3), the third semiconductor layer (5) and the first semiconductor layer One-dimensional electrons are formed in the first semiconductor layer (3) at the hetero interface with (3), and a one-dimensional channel is formed by these -dimensional electrons. In this case, since the growth of the third semiconductor layer (5) can be performed continuously in the same vapor phase growth apparatus following the growth of the first and second semiconductor layers (3, 4), - The surface of the first semiconductor layer (3) where dimensional electrons are formed is not exposed to the atmosphere during manufacturing.

Thereby, a one-dimensional channel with good characteristics can be easily and reliably formed.

According to the fourth aspect of the invention, the first and second semiconductors 7! are formed in a convex shape by performing vapor phase growth of the third semiconductor layer (5) using a triethyl compound-based raw material. (3
, 4), it is possible to reliably grow the third semiconductor layer thereon. Thereby, a one-dimensional channel with good characteristics can be easily and reliably formed.

According to the invention of claim 5, the third semiconductor layer (5) and the first
A one-dimensional channel is formed by one-dimensional electrons formed in the first semiconductor layer (3) at the hetero interface with the semiconductor layer (3). Furthermore, since the growth of the first, second and third semiconductor layers (3, 4, 5) can be performed continuously in the same vapor phase growth apparatus, The surface of the first semiconductor layer (3) is not exposed to the atmosphere during manufacturing, thereby making it possible to realize an FET with a one-dimensional channel structure with good characteristics.

According to the sixth aspect of the invention, since the channels constitute a multiple channel, it is possible to realize a quantum interference type semiconductor device that operates by utilizing the interference of electronic waves passing through the multiple channels.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In addition, in all the figures of the embodiment, parts having the same function are given the same reference numerals.

Back layer ■work 1A to 1C show Embodiment I of the present invention.

This embodiment (2) is an embodiment in which the present invention is applied to the manufacture of a semiconductor device having a one-dimensional channel using a quantum well thin wire made of GaAs.

In this embodiment I, as shown in FIG. 1A, an insulating film 2 such as a SiO□ film is first formed on a semi-insulating GaAs substrate 1 by, for example, a CVD method, and then the insulating film 2 is A predetermined portion is etched away to form a striped opening 2a.

In this case, the semi-insulating GaAs substrate l is, for example, (0
01), and the direction in which the opening 2a extends is the <110> direction. Within this frontage 2a (001)
A region 1a having a plane orientation is selectively formed.

Next, as shown in Figure 1B, semi-insulating GaA
An s-layer 3 and semi-insulating AI, Ga, -, and As layers 4 are grown alternately. A trimethyl compound-based raw material is used as a raw material for this MOCVD, and specifically trimethyl gallium ((C) is used as a raw material for Ga, AI, and As.
H3):l Ga, TMG),) trimethylaluminum ((CH3)! AI, TMA) and trimethylarsenic (
(CHz)s As, TMAs). In this case, these GaAs layers 3 and AI, IGa, -, A
The s-layer 4 does not grow on the insulating film 2, but selectively grows only on the region la within the opening 2a of the insulating film 2. In addition, during MOCVD using this trimethyl compound-based raw material, the GaAs layer 3 and AI.

The Ga1-X As layer 4 grows so that the area becomes smaller toward the upper layer, and the semi-insulating AI, Ga,
Growth automatically stops when a vertex is formed in the XAsAsO2 length. In this way, a mesa structure having a triangular cross-sectional shape is formed.

Next, as shown in Figure 1C, MOCV under reduced pressure or normal pressure
D method, for example, silicon (Si) doped n-type A1. This MOC performs Ga, -xAsABO3 length
A triethyl compound-based raw material is used as a raw material for VD,
Specifically, triethylgallium ((C□H6)3Ga, TEG) is used as a raw material for Ga, AI, and As, respectively.
) ethylaluminum ((C2Hs) 3 Al,
TEA) and triethyl arsenic ((C2Hs) 3
As, TEAs) are used. In this case, this n-type ^I
X Gap-11As1J 5 does not grow on the insulating film 2, but grows on the above-mentioned GaAs layer 3 and A1. Ga, -xAsA
It grows only on s. In this way, At as a barrier layer.

Ga1-x As layer 4 and n-type A11l Ga1-x
A quantum well wire consisting of a GaAs layer 3 surrounded by an As layer 5 is formed.

In this case, one-dimensional electrons are formed in the GaAs layer 3 at the hetero interface between the n-type AlXGa, -, As layer 5 and the GaAs layer 3, and a one-dimensional channel (indicated by a dotted line) is formed by these -dimensional electrons. .

As described above, according to this embodiment I, a one-dimensional channel using a quantum well thin wire can be easily and reliably formed. In this case, the GaAs layer 3, ^1°Ga1-,
Since the growth of the As layer 4 and the n-type Al11 Ga1-2 As layer 5 can be performed continuously in the same MOCVD apparatus, the growth of the GaAs layer 3 in the portion where -dimensional electrons are formed
The surface of the channel is not exposed to the atmosphere, so the properties of this one-dimensional channel are good.

Figure 2 shows the embodiment (2) of the present invention. This example ■ is -
This is an example in which the present invention is applied to manufacturing an FET with a dimensional channel structure.

In this embodiment (2), as shown in FIG. 2, after forming a striped opening 2a of a predetermined length in the insulating film 2,
The area la within this frontage 2a is
A GaAs layer 3, an AIX Gap-x As layer 4 and an n-type A111 cal-x AsN 5 are selectively grown thereon.

Next, an ohmic metal film such as AuGe/Ni is formed over the entire surface by, for example, vapor deposition, and then this ohmic metal film is patterned into a predetermined shape by etching. Next, by performing heat treatment, this ohmic metal film and n-type AIX Gap-, As layers 5, A1. Ga,
-, the As layer 4 and the GaAs layer 3 are alloyed.

As a result, a source S and a drain D made of an ohmic metal and an alloy layer thereof having a predetermined shape are formed.

Next, a Schottky metal film such as Al or tungsten (W) is formed on the entire surface by, for example, vapor deposition or sputtering, and then this Schottky metal film is patterned into a predetermined shape by etching to form a gate electrode G. . As a result, an FET with a -dimensional channel structure is completed.

As described above, according to this embodiment (2), an FET having a one-dimensional channel structure with good characteristics can be easily manufactured. As already mentioned, the mobility .mu. of electrons traveling through this -dimensional channel is extremely high, so that an FET with this -dimensional channel structure can operate at extremely high speed.

1.IL FIGS. 3A to 3D illustrate Embodiment 2 of the present invention.

This example (■) is based on the so-called Aharanov-Bohm (Aha
Transistor using the ronov-Bohm effect (
This is an example in which the present invention is applied to the manufacture of an AB effect transistor (hereinafter referred to as an AB effect transistor). This AB effect transistor utilizes the interference of electron waves passing through multiple channels.

In this embodiment (2), as shown in FIG. 3A, first, a boat-shaped opening 2a is formed in the insulating film 2.

Next, as shown in FIG. 3B, the area la within this frontage 2a
AtXGa, As
Layer 4 and GaAs layer 3 are grown alternately.

Next, as shown in FIG.
Grow lx Ga1-xAs1i5.

Next, as shown in the third diagram, a source S and a drain D are formed by the same method as in Example I, and an n-type A
Gate electrodes Gl, G on lx Ga1-x As1i5
form t. Note that these source S and drain D
It is preferable that the dimensions of the connecting portion between the substrate and the one-dimensional channel formed on both sides of the GaAs layer 3 be equal to or smaller than the de Broglie wavelength λ of electrons.

Through the above steps, the desired AB effect transistor is completed. A plan view of this AB effect transistor is shown in FIG. 4. In FIG. 4, n-type A11l Ga1-
, illustration of the As layer 5 is omitted. Also, v in Figure 4
-V line and Vl-Vl line are shown in FIG. 5 and FIG. 6, respectively.

In the AB effect transistor configured as described above, an electron wave emitted from the source S is divided into two electron waves that pass through two one-dimensional channels formed on both sides of the GaAs layer 3, and then these electron waves are The waves rejoin at drain D. During this merging, interference of electronic waves occurs. In this case, the phase difference between these two electron waves is determined by the gate electrodes G,,G! The transistor operation is performed by controlling the gate voltage applied to the transistor.

According to this embodiment (2), it is possible to realize an AB effect transistor with good characteristics and high interference with electron waves.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the above-mentioned embodiment (2), the opening 2 of the insulating film 2
Although the shape of a is boat-shaped, if the shape of this frontage 2a is, for example, rectangular as shown by the dashed line in FIG. 3A, an AB effect transistor having the structure as shown in FIGS. It is possible to achieve this. In this case, in order to make the dimensions of the connecting portions between the source S and drain D and the one-dimensional channels formed on both sides of the GaAs layer 3 equal to or smaller than the electron de Broglie wavelength λ, It is preferable to form the source S and drain D so that the corners of the source S and drain D are connected to the one-dimensional channel.

Further, in the above-mentioned Example I, the opening 2a of the insulating film 2
GaAs layer 3 and All GaI-x
Although the As layer 4 is selectively grown, it is also possible to grow it as follows, for example. That is, as shown in FIG. 9A, first, the surface of the semi-insulating GaAs substrate 10 is selectively removed by etching to form a region 1a having the same shape as shown in FIG. 1A. This etching is carried out by, for example, forming a resist pattern (not shown) on the semi-insulating GaAs base Fi1, using this resist pattern as a mask, wet-etching the semi-insulating GaAs substrate 1 to a predetermined depth, and then performing, for example, RIE etching. This semi-insulating GaAs substrate 1 is anisotropically etched to a predetermined depth in a direction perpendicular to the substrate surface by a method. Thereafter, as shown in FIG. 9B, GaAs layer 3 and A1. Ga,
The x As layer 4 is selectively grown, and the n-type AIX Gat-X As layer 5 is further grown thereon to complete the one-dimensional channel structure. The FET of Example (2) and the AB effect transistor of Example (2) can also be manufactured by the same method. In the case of Example (2), a boat-shaped opening 2a as shown by the dashed line in FIG. 9A may be formed in the insulating film 2.

Furthermore, although the AB effect transistor of Example 3 has a single quantum well structure, the present invention provides an AB effect transistor with a multiple quantum well structure.
It can be applied to effect transistors and other quantum interference devices.

Moreover, the above-mentioned Example 1. In II and III, ^1llGa, -x As/GaAs heterostructure is used, but in the present invention, ^IX Ga, -, As/G
It is possible to apply the present invention to various semiconductor devices using semiconductor heterostructures other than aAs heterostructures.

〔Effect of the invention〕

Since the present invention is configured as described above, it has the following effects.

According to the invention of claim 1, a -dimensional channel can be easily formed.

According to the invention of claim 2, a -dimensional channel can be easily and reliably formed.

According to the invention of claim 3.4, a one-dimensional channel with good characteristics can be easily and reliably formed.

According to the invention of claim 5, an FET having a one-dimensional channel structure with good characteristics can be realized.

According to the invention of claim 6, it is possible to realize a quantum interference type semiconductor device with good characteristics.

[Brief explanation of the drawing]

1A to 1C are perspective views for explaining the actual layer side I of the present invention in the order of steps, FIG. 2 is a perspective view for explaining Embodiment 2 of the present invention, and FIG. 3A - The third drawing is a perspective view for explaining the embodiment (1) of the present invention in the order of steps, FIG. 4 is a plan view of the third drawing, and FIG. 5 is a sectional view taken along the line V-V in FIG. 4. , FIG. 6 is a sectional view taken along the line VI-VI in FIG. 4,
FIG. 7 is a plan view for explaining a modification of the embodiment (2) of the present invention, FIG. 8 is a sectional view taken along the line (■-■) in FIG. 7, and FIGS. 9A and 9B are FIGS. 10, 11, and 12 are perspective views for explaining a modified example of the embodiment (2) of the present invention in the order of steps, and sectional views for explaining conventional techniques, respectively. The main symbols in the drawings are explained as follows: semi-insulating GaAs substrate, 1a: region with predetermined crystal plane orientation, 2: insulating film, 2a: opening, 3: GaAs layer, 4: A1. Gal-11As layer, 5:
n-type A1. Gap-, As layer, S: source,
D Nidrain, G, G+, Gz: Gate electrode. Agent Patent Attorney Tadashi Sugiura Chiten O (Evening・1■ Figure 1A Lol/l! Punishment! Figure 1C Oyodo Jto II Figure 1B Figure 2 Jitsukatahi 4?1■ Figure 3 A Mu Fig. 3 B Fig. 4 @vr4 pasted - Fig. 6 Actual brother example ■ Fig. 3 C r death A!'Ij1 Fig. 3 ■ - 1'l nita 11 Fig. 7 Fig. 8 Example of protrusion Figure 9A Figure 9B Figure 10 Figure 11 Figure 12

Claims (1)

[Claims] 1. A step of selectively forming a region with a predetermined crystal plane orientation on a semiconductor substrate; a first semiconductor layer on the region with the predetermined crystal plane orientation; A method for manufacturing a semiconductor device, comprising the step of alternately stacking second semiconductor layers having a smaller electron affinity than the second semiconductor layer by vapor phase growth in a convex shape in which the area of the upper layer becomes smaller. 2. The region with the predetermined crystal plane orientation is a region with a (001) plane orientation, and the vapor phase growth of the first and second semiconductor layers is performed using a trimethyl compound-based raw material. A method for manufacturing a semiconductor device according to claim 1. 3. selectively forming a region with a predetermined crystal plane orientation on the semiconductor substrate; and a first semiconductor layer on the region with the predetermined crystal plane orientation and having an electron affinity smaller than that of the first semiconductor layer. a step of alternately stacking a second semiconductor layer by vapor phase growth in a convex shape whose area becomes smaller as the upper layer increases;
forming a third semiconductor layer having a lower electron affinity than the semiconductor layer by vapor phase growth so as to cover the convex portion. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the vapor phase growth of the third semiconductor layer is performed using a triethyl compound-based raw material. 5. A first semiconductor layer that is alternately stacked in a convex shape whose area becomes smaller as the upper layer increases, and a second semiconductor layer that has a smaller electron affinity than the first semiconductor layer, and a layer that covers the convex portion. a third semiconductor layer containing impurities and having a lower electron affinity than the first semiconductor layer, a gate electrode formed on the third semiconductor layer, and the first semiconductor layer. and a channel formed in the first semiconductor layer at a heterointerface with the third semiconductor layer. 6. The semiconductor device according to claim 5, wherein the channels constitute a multiple channel.