JPH1093075A - Compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make rising and falling sharp by providing a heterojunction, utilizing the running of a single conductivity type two-dimensional carrier gas in an interface, and utilizing the running of single conductivity type carriers provided between two layers of a one conductivity type two-dimensional carrier gas. SOLUTION: A two-dimensional electron gas 28 is produced in the vicinity of the heterojunction interface between an n-type AlGaAs carrier supplying layer 14 and an i-type GaAs carrier running layer 15. A two-dimensional electron gas 27 is produced in the vicinity of the heterojuction interface between an i-type GaAs carrier running layer 20 and an n-type AlGaAs carrier supply layer 21. The carrier concentrations of the two-dimensional electron gases 27, 28 and an n-type GaAs layer 18 are set so as to be higher, since they separate from a Schottky barrier gate electrode 3. Consequently, it becomes possible to obtain sharply rising and falling characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device, and more particularly to a compound semiconductor device for power having characteristics of HEMT (high electron mobility transistor) and MESFET (Schottky barrier gate FET). It is.

[0002]

2. Description of the Related Art Conventionally, a power compound semiconductor device centered on a GaAs compound semiconductor has been used for high-frequency communication over microwaves. MESFE to use
A typical example is a HEMT using a two-dimensional carrier gas caused by T or a heterojunction, in particular, a two-dimensional electron gas.

[0003] Such a power compound semiconductor device is required to have particularly low distortion characteristics. However, in order to improve the distortion characteristics, the DC (direct current) characteristics must have a flat g _m (mutual conductance). Is desirable, and g
It is required that the rise and fall of _m be sharp.

[0004]

However, in the case of a MESFET in which electrons caused by impurities determining the conductivity type are used, that is, the traveling of electrons in the n-type active layer is controlled by a gate voltage applied to a gate electrode. the, as shown by the solid line in FIG., g _m is a flat, there is a problem that the rise and fall is not sharp.

On the other hand, two-dimensional electron gas is used, that is,
In a HEMT in which the traveling of a two-dimensional electron gas generated at a heterojunction interface formed between semiconductors having different electron affinities is controlled by a gate voltage applied to a gate electrode, rising and falling as shown by broken lines in FIG. although a sharp, there is a problem that the g _m is less likely to be flat.

Accordingly, it is an object of the present invention to flatten g _m in the DC characteristics of a compound semiconductor device, particularly, a compound semiconductor device for power, and to sharpen rising and falling.

[0007]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. 1 (a) and 1 (b) (1) The present invention provides a compound semiconductor device having a plurality of heterojunctions 1 and 2 and a one-conductivity type two-dimensional carrier gas 3 at an interface between each heterojunction 1 and 2. , 4 and the traveling of one conductivity type carrier generated in the one conductivity type semiconductor layer 5 provided between at least two layers of one conductivity type two-dimensional carrier gas 3, 4. And

As described above, the operating characteristics of the HEMT can be obtained by utilizing the traveling of the one-conductivity type two-dimensional carrier gas 3, 4. The operating characteristics of the MESFET can be obtained by utilizing this.

(2) In the present invention according to the above (1), the traveling of the one-conductivity type two-dimensional carrier gas 3, 4 and the one-conductivity type carrier is controlled by the gate electrode 6 and applied to the gate electrode 6. When the voltage is 0, the depletion layer 7 caused by the gate electrode 6 extends to the one conductivity type semiconductor layer 5.

As described above, when the operation is controlled by the gate electrode 6, when the voltage applied to the gate electrode 6 is 0, the depletion layer 7 caused by the gate electrode 6, that is, the Schottky depletion layer becomes a semiconductor of one conductivity type. by so spread layer 5, during shallow gate bias, similar flat g _m characteristic and MESFET can be obtained.

(3) According to the present invention, in the above (2), the layer provided between the hetero junctions 1 and 2 has a layer structure of an intrinsic semiconductor layer-a semiconductor layer of one conductivity type-an intrinsic semiconductor layer. It is characterized by the following.

As described above, the layer provided between the heterojunction 1 and 2 is an intrinsic semiconductor layer—one conductivity type semiconductor layer 5—intrinsic semiconductor layer, and the intrinsic semiconductor layer is a one conductivity type two-dimensional carrier gas 3.
By using the traveling layer of No. 4, it is possible to prevent a decrease in operating speed due to scattering of carriers by impurities.

(4) The present invention is characterized in that, in the above (2) or (3), the one-conductivity-type semiconductor layer 5 has a high carrier concentration at a central portion thereof.

As described above, by increasing the carrier concentration in the central portion of the one conductivity type semiconductor layer 5, the MESF
Can enhance the operating characteristics of the ET, it is possible to obtain a flat g _m characteristic. The change in the impurity concentration may be changed in a graded manner or in a stepped manner.

(5) The present invention is characterized in that in (2) or (3), the composition of the layer provided between the heterojunctions 1 and 2 is partially different.

(6) The present invention is characterized in that, in the above (5), the composition of the layer provided between the hetero junctions 1 and 2 is changed in an inclined manner.

As described above, by partially changing the composition of the layer provided between the heterojunctions 1 and 2 in a different manner, in particular, by changing the composition in an inclined manner, the crystallinity is not reduced due to lattice mismatch. , it is possible to increase the carrier concentration in the heterozygous 1 side, whereby it is possible to increase the overall g _m.

(7) Further, according to the present invention, in any one of the above (2) to (6), the carrier concentration of the one-conductivity type two-dimensional carrier gas 3, 4 and the one-conductivity type semiconductor layer 5 is reduced by the gate electrode 6 It is characterized in that it becomes higher in order from a side closer to the distant side.

As described above, the carrier in each carrier traveling section is
Rear concentration from the side closer to the gate electrode 6 to the side farther from the gate electrode 6.
If the depletion layer 7 does not spread by increasing
In this case, the traveling of the one conductivity type two-dimensional carrier gas 3, 4 and
Travel of one conductivity type carrier generated in one conductivity type semiconductor layer 5
By utilizing the traveling of the three carriers of g _m
The rising characteristics of the device as sharp as HEMT
Can be.

Further, when the depletion layer 7 reaches the one conductivity type semiconductor layer 5, by utilizing the traveling of the one conductivity type carriers in the one conductivity type semiconductor layer 5, to the flat of the g _m as a MESFET Can be.

Further, the gate electrode 6 is deeply biased.
As a result, the depletion layer 7 is separated from the gate electrode 6
When reaching the vicinity of the electric two-dimensional carrier gas 3,
Only one conductivity type two-dimensional carrier gas 3 is responsible for the operation.
However, this one-conduction type two-dimensional carrier gas 3 is
Since the concentration is the highest, g_mWithout reducing g _m
To make the falling characteristics as sharp as HEMT
Can be.

[0022]

FIG. 2 shows a first embodiment of the present invention.
This will be described with reference to FIG. FIG. 2 is a schematic element cross-sectional view of the HEMT according to the first embodiment of the present invention.
FIG. 3 is an explanatory diagram of the operation. First, referring to FIG. 2, a thickness of 500 to 150 is formed on a semi-insulating GaAs substrate 11 by MOVPE (metal organic chemical vapor deposition).
Undoped i-type GaAs of 00 °, eg 4000 °
An s buffer layer 12 and an undoped i-type AlGaAs buffer layer 13 having a thickness of 300 to 3000 〜, for example, 1000 Å are grown.

Subsequently, a thickness of 130 to 400 Å, for example, 200 な る serving as an electron supply layer of the lower HEMT is formed thereon.
Then, an Si-doped n-type AlGa having an impurity concentration of 1.0 to 3.0 × 10 ¹⁸ cm ⁻³ , for example, 2.0 × 10 ¹⁸ cm ^−3.
An As carrier supply layer 14 and a traveling layer for electrons;
An undoped i-type GaAs carrier transit layer 15 having a thickness of 100 to 400 °, for example, 200 ° is grown.

Subsequently, a 300-500 .mu.m thick, for example, 400 .mu.m thick Si is formed thereon to form a MESFET structure.
A doped n-type GaAs layer 16 is grown.

The n-type GaAs layer 16 has an initial impurity concentration of 5.0 to 8.0 × 10 ¹⁷ cm ⁻³ , for example, 7.0 × 10 ¹⁷ cm ⁻³ .
From the n-type GaAs layer 17 of 10 ¹⁷ cm ^-3, the n-type GaAs layer ¹⁸ having an impurity concentration of 1.0 to 2.0 × 10 ¹⁸ cm ^{-3 at} the center, for example, 1.5 × 10 ¹⁸ cm ^-3. , And the final impurity concentration from the n-type GaAs layer 18 to 5.0 to 5.0.
8.0 × 10 ¹⁷ cm ⁻³ , for example, 7.0 × 10 ¹⁷ cm ⁻³
The n-type GaAs layer 19 is grown such that the impurity concentration decreases in a graded manner.

The n-type GaAs layer 16 has a thickness of 1
30 to 210 °, for example, 150 °, and the impurity concentration is
5.0-8.0 × 10¹⁷cm^-3, For example, 7.0 × 10
¹⁷cm ^-3N-type GaAs layer 17, having a thickness of 50 to 150 °,
For example, at 100 °, the impurity concentration is 1.0 to 2.0 × 1.
0¹⁸cm^-3, For example, 1.5 × 10¹⁸cm^-3N-type Ga
As layer 18 and a thickness of 130 to 210 °, for example, 1
At 50 °, the impurity concentration is 5.0 to 8.0 × 10¹⁷c
m^-3, For example, 7.0 × 10¹⁷cm^-3N-type GaAs layer
It has a three-layer structure in which the impurity concentration of 19 changes stepwise.
You may comprise.

Subsequently, a thickness of 100 to 300 Å, for example, 200 な る
The thickness of the undoped i-type GaAs carrier traveling layer 20 and the electron supply layer is 200 to 400 Å, for example, 300 Å, and the impurity concentration is 5.0 to 9.0 × 10 ^17.
A Si-doped n-type AlGaAs carrier supply layer 21 of cm ^-3 , for example, 7.0 × 10 ¹⁷ cm ^-3 is grown.

Further, a contact layer having a thickness of 500 to 1500 Å, for example, 1000 、 and an impurity concentration of 1.0 to 4.0 × 10 ¹⁸ cm ^-3 , for example, 3.0
A x10 ¹⁸ cm ^-3 Si-doped n-type GaAs contact layer 22 is grown.

Next, the n-type GaAs contact layer 2
2 is selectively removed to expose the n-type AlGaAs carrier supply layer 21, and a Schottky barrier gate electrode 23 made of Ti / Au is formed on the exposed portion by a lift-off method, and Au and Ge are formed on both sides thereof. / Ni / A
u, source / drain electrodes 24 and 25 are formed,
Finally, the SiN film 26 is provided as a passivation film.

In this case, in the vicinity of the heterojunction interface between the n-type AlGaAs carrier supply layer 14 and the i-type GaAs carrier transit layer 15, the two-dimensional electron gas 28 is generated due to the difference in electron affinity and forbidden band width between the two. Occur, and the i-type GaAs carrier traveling layer 20 and the n-type AlGaAs
The two-dimensional electron gas 27 is also generated near the heterojunction interface with the s carrier supply layer 21.

The two-dimensional electron gas 27, 28 and the n-type G
The carrier concentration of the aAs layer 18 is set such that the carrier concentration increases as the distance from the Schottky barrier gate electrode 23 increases.

In this case, in a state where the Schottky barrier gate electrode 23 is not biased, that is, at the time of 0 V bias, the thickness of each layer is set so that the depletion layer extending from the Schottky barrier gate electrode 23 reaches at least the n-type GaAs layer 19. It is necessary to set the impurity concentration.

The source / drain electrodes 24, 25
It is necessary to electrically conduct ohmic contact with the two-dimensional electron gas layers 27 and 28 and the n-type GaAs layer 16 by heat treatment.

Next, the operation of the compound semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. FIG. 3A shows the spread of the depletion layer 29 when the Schottky barrier gate electrode 23 is deeply biased positively, and shows a state where the two-dimensional electron gas 27 is not cut off. ing.

In this case, the two-dimensional electron gas 27 and the n-type G
aAs layer 16, in particular, electron traveling through the n-type GaAs layer 18, and, it means operated by a two-dimensional electron gas 28, deeply positively biased state, that is, the falling characteristics of the g _m characteristic, The characteristics of the HEMT become dominant, and a sharp falling characteristic can be obtained similarly to the HEMT.

FIG. 3 (b) shows the Schottky barrier gate electrode 2
This shows the expansion of the depletion layer 29 when 3 is biased to 0 V, and reaches a part of the n-type GaAs layer 16.

In this case, the two-dimensional electron gas 27 is cut off by the depletion layer 29, and the n-type GaAs layer 16, particularly,
and n-type GaAs layer 18 electrons and the two-dimensional electron gas 28 traveling (not shown) becomes a subject of operation, similar flat g _m characteristic and MESFET by electrons traveling n-type GaAs layer 18 is obtained .

FIG. 3C shows the Schottky barrier gate electrode 2.
3 shows the expansion of the depletion layer 29 in a state where the N.sub.3 is deeply negatively biased.
The s layer 16 is blocked.

In this case, since the operation is performed only by the two-dimensional electron gas 28, the HEM is not applied in a deeply negatively biased state, that is, in the rising characteristic of the g _m characteristic.
The characteristic of T appears, and a sharp rising characteristic is obtained.

Since the two-dimensional electron gas 28 constituting the lower HEMT has the highest carrier concentration, the absolute value of g _m is not significantly reduced even if the two-dimensional electron gas 28 is operated only by the two-dimensional electron gas 28. There is no.

Therefore, the same rise and fall in the g _m characteristic as in the HEMT can be obtained, and the ME
A flat characteristic similar to that of the SFET is obtained, and the distortion characteristic is improved.

For example, a conventional double heterojunction structure M
In the ESFET type compound semiconductor device, the third-order intermodulation distortion was −44 dBc at 10 dBm back-off, but is −49 dBc in the present invention,
Substantial improvements were obtained.

It should be noted that this third-order intermodulation distortion is caused by the nonlinearity in the compound semiconductor device when two signals f ₁ and f ₂ having substantially the same frequency, that is, f ₁ −f ₂ = several tens of MHz are supplied as input signals. As a result, a signal having a frequency of (2f ₂ −f ₁ ) or (2f ₁ −f ₂ ) is output, and this output signal level is represented by a ratio to the signal level of the basic signal f ₁ or f ₂ .

Next, a second embodiment of the present invention will be described with reference to FIG. First, referring to FIG. 4, a thickness of 500 to 15000 Å, for example, 4000 Å is formed on a semi-insulating GaAs substrate 11 by MOVPE.
Å undoped i-type GaAs buffer layer 12, and
An undoped i-type AlGaAs buffer layer 13 having a thickness of 300 to 3000 Å, for example, 1000 Å is grown, and then an electron supply layer of lower HEMT having a thickness of 130 to 3000 Å is formed.
400 °, for example, 200 °, and the impurity concentration is 1.0 to
3.0 × 10 ¹⁸ cm ⁻³ , for example, 2.0 × 10 ¹⁸ cm ⁻³
Then, a Si-doped n-type AlGaAs carrier supply layer 14 is grown.

Subsequently, a traveling layer of electrons is formed thereon.
Undoped i-type InGaAs graded carrier traveling layer 30 having a thickness of 100 to 150 °, for example, 140 °
Is grown so that its In composition ratio changes from 0.20 to 0.10, and subsequently, a MESFET structure is formed at a thickness of 250 to 500 °, for example, 350 ° and an impurity concentration of 1.0 to 2 °. 0.0 × 10 ¹⁸ cm ⁻³ , for example, 1.
The Si doped n-type InGaAs graded layer 31 of 5 × 10 ¹⁸ cm ⁻³ has an In composition ratio of 0.10 to 0.1%.
00, that is, grown so as to change to GaAs.

Subsequently, a thickness of 100 to 400 Å, for example, 200
The thickness of the undoped i-type GaAs carrier traveling layer 20 and the electron supply layer is 150 to 350 °, for example, 250 °, and the impurity concentration is 0.7 to 1.5 × 10 ^18.
A Si-doped n-type AlGaAs carrier supply layer 21 of cm ^-3 , for example, 1.0 × 10 ¹⁸ cm ^-3 is grown.

Further, a contact layer having a thickness of 500 to 1500 °, for example, 1000 ° and an impurity concentration of 1.0 to 4.0 × 10 ¹⁸ cm ⁻³ , for example, 3.0, is formed thereon.
A x10 ¹⁸ cm ^-3 Si-doped n-type GaAs contact layer 22 is grown.

Next, as in the first embodiment, the n-type GaAs contact layer 22 is selectively removed to expose the n-type AlGaAs carrier supply layer 21, and Ti / Au A Schottky barrier gate electrode 23 is formed by a lift-off method, and source / drain electrodes 24 and 25 made of Au.Ge/Ni/Au are formed on both sides thereof.
The film 26 is provided as a passivation film.

In this case as well, in the vicinity of the heterojunction interface between the n-type AlGaAs carrier supply layer 14 and the i-type InGaAs graded carrier traveling layer 30, two-dimensional differences occur due to the difference in electron affinity and forbidden band width between the two. Electron gas 2
8 occurs and the i-type GaAs carrier traveling layer 20
The two-dimensional electron gas 27 is also generated in the vicinity of the heterojunction interface between the substrate and the n-type AlGaAs carrier supply layer 21.

The source / drain electrodes 24, 25
It is necessary to electrically conduct ohmic contact with the two-dimensional electron gas layers 27 and 28 and the n-type InGaAs graded layer 31 by heat treatment.

In the second embodiment, the reason why the InGaAs layer is adopted as the carrier traveling layer of the lower HEMT is that the difference in the forbidden band width between the lower HEMT and the n-type AlGaAs carrier supply layer 14 is increased. The reason why the two-dimensional electron gas 28 having a higher carrier concentration is generated, and the reason why the MESFET is also formed of the InGaAs layer is to make the electron mobility higher than that of the GaAs layer.

In this case, the graded structure In
The reason for using a GaAs layer is as follows.
In _0.20 Ga _0.80 A having an In composition ratio of 0.20 on the As layer
This is because when s is grown to be thick, an InGaAs layer with good crystallinity cannot be obtained due to lattice mismatch.

Also, in the second embodiment,
The carrier concentrations of the two-dimensional electron gases 27 and 28 and the n-type InGaAs graded layer 31 are set such that the carrier concentration increases as the distance from the Schottky barrier gate electrode 23 increases.

The device operating characteristics in this case are the same as those of the first embodiment.
This is almost the same as the first embodiment, but is different from the first embodiment.
By comparison, the overall carrier concentration is higher
And g _mBecomes larger.

The first embodiment and the second embodiment have been described above, but each AlG in each embodiment is described.
Although the Al composition ratio of the aAs layer is actually 0.25, that is, Al _0.25 Ga _0.75 As,
_The Al composition ratio is not limited to _0.25 Ga _0.75 As but may be any range as long as the Al composition ratio is in the range of 0.15 to 0.35.

In the description of each of the above embodiments, the MOVPE method is used as a crystal growth method.
The method is not limited to the MOVPE method, and an MBE method (molecular beam epitaxial growth method) may be used.

In the first embodiment,
The n-type GaAs layer 16 constituting the MESFET is formed by the n-type GaAs layers 17, 18 and 19 whose impurity concentration changes in a graded manner or in a stepwise manner. Is increased at the center, that is, at the center of the n-type GaAs layer 18, but the impurity concentration does not necessarily need to be changed, and the n-type GaAs layer 16 is formed only by the n-type GaAs layer having a uniform impurity concentration. It may be configured.

Further, in the above-described second embodiment,
Is a carrier traveling layer and a MES constituting a lower HEMT.
As the n-type semiconductor layer constituting the FET, the composition ratio is graded.
Adopts an InGaAs graded layer that changes
However, the composition ratio may be changed stepwise.
Rear running layer is In_0.20Ga_0.80When composed of As layer
The n-type semiconductor layer constituting the MESFET is changed to In_0.15G
a_0.85As-In_0.10Ga _0.90As-In_0.05Ga_0.95
It may be configured with an As structure.

[0059]

According to the present invention, the device operation can be reduced by the lower H
EMT, MESFET, and, because performed by a combination of upper HEMT, the g _m of the DC characteristics flat,
In addition, since the rising and falling edges can be sharpened, distortion characteristics can be improved, and this greatly contributes to higher performance of power devices.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of an operation according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

5 is an explanatory diagram of g _m characteristic of the conventional compound semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Heterojunction 2 Heterojunction 3 One conductivity type two-dimensional carrier gas 4 One conductivity type two-dimensional carrier gas 5 One conductivity type semiconductor layer 6 Gate electrode 7 Depletion layer 11 Semi-insulating GaAs substrate 12 i-type GaAs buffer layer 13 i-type AlGaAs Buffer layer 14 n-type AlGaAs carrier supply layer 15 i-type GaAs carrier travel layer 16 n-type GaAs layer 17 n-type GaAs layer 18 n-type GaAs layer 19 n-type GaAs layer 20 i-type GaAs carrier travel layer 21 n-type AlGaAs carrier supply layer Reference Signs List 22 n-type GaAs contact layer 23 Schottky barrier gate electrode 24 source electrode 25 drain electrode 26 SiN film 27 two-dimensional electron gas 28 two-dimensional electron gas 29 depletion layer 30 i-type InGaAs graded carrier traveling layer 31 n-type InGaAs graded layer

Claims (7)

[Claims] 1. A two-dimensional carrier gas having a plurality of heterojunctions, wherein the two-dimensional carrier gas of one conductivity type is used at an interface between the heterojunctions, and is provided between at least two layers of the two-dimensional carrier gas of one conductivity type. A compound semiconductor device utilizing the traveling of one conductivity type carrier generated in the obtained one conductivity type semiconductor layer. 2. The two-dimensional carrier gas of one conductivity type and the traveling of the carrier of one conductivity type are controlled by a gate electrode, and when a voltage applied to the gate electrode is zero, a depletion layer caused by the gate electrode is reduced. 2. The compound semiconductor device according to claim 1, wherein said compound semiconductor device extends to said one conductivity type semiconductor layer. 3. The compound semiconductor device according to claim 2, wherein the layer provided between the heterojunctions has a layer structure of an intrinsic semiconductor layer-a semiconductor layer of one conductivity type-an intrinsic semiconductor layer. 4. The compound semiconductor device according to claim 2, wherein the one-conductivity-type semiconductor layer has a high carrier concentration at a central portion thereof. 5. The composition of a layer provided between said heterojunctions is
The compound semiconductor device according to claim 2, wherein the compound semiconductor device is partially different. 6. The composition of a layer provided between the hetero junctions is as follows:
6. The compound semiconductor device according to claim 5, wherein said compound semiconductor device is inclined. 7. The one-conductivity-type two-dimensional carrier gas and the carrier concentration of the one-conductivity-type semiconductor layer increase in order from a side closer to the gate electrode to a side farther from the gate electrode. 7. The compound semiconductor device according to any one of items 1 to 6.