JPH10116837A - Field effect type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve voltage-resistance and such characteristics as harmonic distortion, by epitaxially growing a p-type buffer layer and a channel layer on a p-type semiconductor substrate. SOLUTION: On a p-type buffer layer 2 of a p-type GaAs layer, an n-type channel layer 3 of an n-type GaAs layer is epitaxially grown. A voltage of about 4V is applied between a gate and a drain, and when, especially, a gate voltage is negatively biased, an electric field reaches 1×10<5> (V/cm), resulting in avalanche amplification in the channel at a recess end on a drain side directly under the gate. The hole resulting from avalanche multiplication in a channel layer flows without delay into the p-type GaAs layer 2 with about 0.4eV lower electric potential than the channel layer 3, this no hole accumulation occurs. As a result, a high gate voltage-resistance is kept. Therefore, a gate voltage- resistance of a high output power transistor and such distortion characteristics as harmonic distortion of small signal device are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect type semiconductor device, and more particularly to a high-output field-effect type semiconductor device in which a high electric field is generated at a high frequency at which avalanche multiplication occurs, and a low-distortion characteristic during small signal operation. The present invention relates to a low distortion field effect type semiconductor device having the same.

[0002]

2. Description of the Related Art A conventional field effect type semiconductor device will be described.

FIG. 5 shows a first conventional example. "IEEE Elect
ron Device Letters), EDL-8, No. 3, No. 1,
987, March 116, pp. 116-117, "Improved GaAs Power Performance Using Be Co-I.
mplantation ", a field-effect semiconductor device having a p-type buffer layer. The semi-insulating GaAs substrate 11 has a concentration of 1.2 × 10 ¹² (cm ⁻² ) to 1.6 × 10 ¹² (cm).
^-2 ) ohmic contacts to the p-type GaAs layer 12 formed by Be ion implantation, the n-type GaAs layer 13 formed by silicon ion implantation at a concentration of 6 × 10 ¹² (cm ⁻² ), and the n-type GaAs layer 13 It has a source electrode 16, a drain electrode 17, and a gate electrode 18 that is Schottky-bonded to the n-type GaAs layer 13. Annealing is performed at 850 ° C. for 20 minutes for activation after implantation.

In this field effect type semiconductor device, when a high drain voltage of about 4 V or more is applied since the distance between the gate and the drain is on the order of submicrons, the electric field at the gate end 19 on the side of the drain electrode 17 becomes critical of GaAs. Since the electric field reaches about 1 × 10 ⁵ (V / cm), avalanche multiplication occurs, and some of the holes generated by the avalanche multiplication follow the electric field distribution and have a potential lower than the p-type GaAs layer 12 by about 0.4 eV or more. Into the p-type GaAs layer 12
Alternatively, it diffuses and disappears in the semi-insulating GaAs substrate 11.
Therefore, accumulation of holes is unlikely to occur, and n channels (n
The influence on the type GaAs layer 13) is reduced.

FIG. 2 shows a second conventional example. JP-A-8-1
No. 53733, a field-effect semiconductor device having a low-temperature buffer layer and a p-type buffer layer proposed in “Field-Effect Transistor and Manufacturing Method Thereof,
A non-doped GaAs layer 22 grown at a substrate temperature of 200 ° C., a p-type GaAs layer 23 grown at a substrate temperature of 600 ° C., an n-type GaAs layer 24 grown at a substrate temperature of 600 ° C., and n ⁺ -type GaAs on an As substrate 21 by MBE. made from layer 25, the source electrode 26 which forms an ohmic contact to the n ⁺ -type GaAs layer 25, the drain electrode 27, n-type GaAs
The gate electrode 28 has a Schottky junction with the layer 24.

In this field effect type semiconductor device, when a high drain voltage of about 4 V or more is applied since the distance between the gate and the drain is on the order of submicrons, the electric field at the drain end 29 on the gate side becomes the critical electric field of GaAs. Of about 1 × 10 ⁵ (V / cm), avalanche multiplication occurs, and some of the holes generated thereby follow the p-type GaAs layer 2 serving as a buffer layer while following the electric field distribution.
Flow into the 3 side. Thereafter, holes collected near the interface between 22 and 23 disappear through the recombination center 30.

[0007]

However, the above-mentioned conventional field effect type semiconductor device has the following problems.

In the first embodiment using the p-type buffer layer 12, holes easily flow into the p-type GaAs layer 12 having a low potential with respect to the holes, but holes in the p-type GaAs layer or the semi-insulating GaAs substrate 11 are used. It is considered that the recombination centers of the holes are not present at a high concentration, and the lifetime of the holes is prolonged. Therefore, since the recombination ratio is low with respect to the number of hole inflows, holes are accumulated, and as a result, there is a problem that kink is generated or gate breakdown voltage is deteriorated.

Also, non-doped Ga grown at 200 ° C.
In the second embodiment using the As layer and the p-type GaAs layer grown at 600 ° C., the non-doped G
The band structure of the aAs layer 22 is close to the i-type, and the Fermi level is substantially at the center of the band. Therefore, p-type GaAs
The potential of the valence band is lower than that of the layer 23, and the n-type G
The holes generated in the aAs layer 24 hardly flow into the non-doped GaAs layer 22 from the p-type GaAs layer. Non-doped G
Although the aAs layer 22 is grown at 200 ° C.,
The temperature rises to ℃ and grows again, so the crystallinity improves,
As a result, it is considered that the concentration of deep levels decreases.

A large amount of holes generated by avalanche multiplication in the channel near the drain-side gate end 29 first flow into the p-type GaAs layer 23, and then collect near the interface of the non-doped GaAs layer 22 to form a non-doped GaAs layer.
Although recombination and annihilation occur due to recombination centers in the As layer 22,
The avalanche multiplication itself in the channel layer is caused by a fast reaction, and it is considered that the recombination center exists at a high concentration enough to recombine all the holes generated in large numbers one after another. Example 1
In the same manner as described above, accumulation of holes occurs, kink increases, and gate breakdown voltage deteriorates.

In any case, it has been difficult to realize a field-effect semiconductor device without deterioration of gate breakdown voltage due to accumulation of holes or deterioration of distortion characteristics such as second and third harmonic distortion. .

An object of the present invention is to provide a field effect type semiconductor device having improved withstand voltage and improved distortion characteristics such as harmonic distortion.

[0013]

SUMMARY OF THE INVENTION In order to solve these problems, the present invention provides a p-type semiconductor substrate having at least a p-type buffer layer and a channel layer epitaxially grown on a p-type semiconductor substrate. And a source electrode. For example, a p-type semiconductor substrate, a p-type buffer layer and a channel layer are formed of GaAs.
The gate electrode is a Schottky electrode, and the drain and source electrodes are ohmic electrodes.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to FIG.

An example of crystal growth using epitaxial growth such as MBE or MOCVD is shown as an example when growth is performed by MBE.

A hole concentration of 1 × 1 using Zn as a dopant
The substrate temperature is 60 on a p-type GaAs substrate 1 of 0 ¹⁶ (cm ⁻³ ).
P-type GaAs having a hole concentration of 1 × 10 ¹⁶ (cm ⁻³ ) and a thickness of 300 nm using beryllium grown as a dopant at 0 ° C.
A p-type buffer layer 2 composed of an s layer, a carrier concentration of 7 × 10 ¹⁷ (cm ⁻³ ) using silicon as a dopant, and a film thickness of 50 nm
N-type channel layer 3 made of n-type GaAs layer, thickness 100
non-doped GaAs layer 4 having a thickness of 50 nm with a carrier concentration of 2 × 10 ¹⁸ (cm ⁻³ ) using silicon as a dopant.
m of the n ⁺ -type GaAs layer 5 source electrode 6 and ohmic contact and the n ⁺ -type GaAs layer, the shot drain electrode 7, in one step recess structure undoped GaAs layer 4 is formed so as to remain approximately 50nm non-doped GaAs layer 4 It has a gate electrode 8 for key junction. The distance between the gate electrode 8 and the drain-side recess edge is about 0.45 μm. MB
The growth rate of E was about 0.5 μm / h for each layer, and all the layers were grown at 600 ° C.

In this structure, when a drain voltage of about 4 V is applied between the gate and the drain, and particularly when the gate voltage is negatively biased, the electric field reaches 1 × 10 ⁵ (V / cm) and the electric field immediately below the gate is reached. Avalanche multiplication occurs in the channel at the drain side recess end. FIG. 2 shows a band diagram at this time. The hole resulting from the avalanche multiplication in the channel layer has a lower p potential of about 0.4 eV than the channel layer.
Since it immediately flows into the type GaAs layer 2, the accumulation of holes does not occur. As a result, a high gate breakdown voltage can be maintained.

Further, when the potential of the p-type substrate is negatively biased (FIG. 3), the potential difference between the channel layer and the p-type substrate can be further increased as compared with the case of zero bias, and holes generated by avalanche multiplication can be obtained. The effect is that more can be absorbed.

FIG. 4 shows the acceptor concentration dependence of the second and third harmonic distortion substrates obtained by device simulation. Here, it is assumed that the p-type substrate and the p-type buffer layer have the same acceptor concentration. The gate width and gate length of the FET are 1.2 mm and 1 μm, respectively, the operating frequency is 400 MHz, and the input power is −20 dB.
m. Up to the acceptor concentration Na of 1 × 10 ¹⁵ cm ⁻³ , the second and third harmonic distortions do not change much, but the acceptor concentration is 5 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ^−3.
It can be seen that the strain characteristics are improved over cm ^-3 . However, if the acceptor concentration is 5 × 10 ¹⁶ cm ⁻³ or more, the element may decrease in gain due to the decrease in the width of the depletion layer and increase in the capacitance component, or the substrate leakage current may flow due to the change in the expansion of the depletion layer. Degrades the high-frequency characteristics. For these reasons, the acceptor concentration is 5 × 10
¹⁵ cm ^-3 to 5 × 10 ¹⁶ cm ^-3 is optimal.

In this embodiment, Ga using a GaAs substrate is used.
As mentioned about AsMISFET, MESFET and H
It goes without saying that the same effect can be obtained for other structures such as EMT and also for other substrates such as InP.

[0021]

As described above, the field-effect semiconductor device of the present invention uses a p-type GaAs substrate to reduce holes generated by avalanche multiplication in the channel.
The holes do not accumulate by flowing into and disappearing from the GaAs layer. As a result, there is an effect that distortion characteristics such as gate breakdown voltage of a high output power transistor and harmonic distortion of a small signal device can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a device structure according to an embodiment of the present invention.

FIG. 2 is an energy band diagram when the substrate is zero-biased in the embodiment of the present invention.

FIG. 3 is an energy band diagram when the substrate is negatively biased in the embodiment of the present invention.

FIG. 4 shows the results of 2 obtained by device simulation.
Diagram showing the dependence of the second and third harmonic distortion on the acceptor concentration

FIG. 5 is a sectional view of a device structure in a first conventional example.

FIG. 6 is a sectional view of a device structure in a second conventional example.

FIG. 7 is an energy band diagram in the second conventional example.

[Explanation of symbols]

Reference Signs List 1 p-type GaAs substrate 2 p-type buffer layer 3 n-type channel layer 4 undoped GaAs layer 5 n ⁺ -type GaAs layer 6 source electrode 7 drain electrode 8 gate electrode 9 hole 11 semi-insulating GaAs substrate 12 p-type GaAs layer 13 n-type GaAs layer 16 source electrode 17 drain electrode 18 gate electrode 19 drain side gate end 21 semi-insulating GaAs substrate 22 first buffer layer 23 second buffer layer 24 channel layer 25 n ⁺ type GaAs layer 26 source electrode 27 drain electrode 28 Gate electrode 29 Drain side gate end 30 Recombination center

Continued on the front page (72) Inventor Masahiro Maeda 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Person Junta Ota 1006 Kadoma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (11)

[Claims] 1. A field effect semiconductor device wherein at least a p-type buffer layer is epitaxially grown on a p-type compound semiconductor substrate. 2. The field effect semiconductor device according to claim 1, wherein the acceptor concentration of the p-type buffer layer is 5 × 10 ¹⁵ or more and 5 × 10 ¹⁶ or less. 3. An n-type channel layer and an n-type ohmic contact layer are sequentially epitaxially grown on the p-type buffer layer. A gate electrode is formed on the n-type channel layer, and a drain is formed on the n-type ohmic contact layer. 3. The field effect type semiconductor device according to claim 2, wherein an electrode and a source electrode are provided. 4. An n-type channel layer, a non-doped Schottky layer and an n-type ohmic contact layer are sequentially epitaxially grown on the p-type buffer layer, and a gate electrode is formed on the non-doped Schottky layer. 3. The field effect semiconductor device according to claim 2, wherein a drain electrode and a source electrode are provided on the contact layer. 5. The field effect semiconductor device according to claim 2, wherein a non-doped buffer layer is at least epitaxially grown on said p-type buffer layer. 6. An n-type channel layer and an n-type ohmic contact layer are sequentially epitaxially grown on the non-doped buffer layer, a gate electrode is provided on the n-type channel layer, and a drain electrode is provided on the n-type ohmic contact layer. 6. The field effect semiconductor device according to claim 5, further comprising: a source electrode. 7. An n-type channel layer, a non-doped Schottky layer and an n-type ohmic contact layer are sequentially epitaxially grown on the non-doped buffer layer,
6. The field effect semiconductor device according to claim 5, wherein a gate electrode is provided on the non-doped Schottky layer, and a drain electrode and a source electrode are provided on the n-type ohmic contact layer. 8. The field-effect semiconductor device according to claim 5, further comprising a structure in which a non-doped channel layer and an n-type carrier supply layer having an electron affinity smaller than that of the non-doped channel layer are sequentially epitaxially grown on the non-doped buffer layer. . 9. The semiconductor device according to claim 5, wherein a structure in which a non-doped channel layer is sandwiched between n-type carrier supply layers having a smaller electron affinity than the non-doped channel layer is sequentially epitaxially grown on the non-doped buffer layer. Field effect type semiconductor device. 10. The p-type compound semiconductor substrate, the p-type buffer layer, the n-type channel layer, the non-doped Schottky layer and the ohmic contact layer are made of GaAs, the non-doped channel layer is made of InGaAs or GaAs, and the n-type carrier supply layer is made of AlGaAs. The field-effect-type semiconductor device according to any one of claims 3, 4, 6, 6, 7, 8 and 9. 11. The field effect semiconductor device according to claim 10, wherein said p-type semiconductor substrate is biased to zero or negative.