JPH0812869B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method of forming a gate electrode of a Schottky junction type semiconductor device, and a method of manufacturing a Schottky junction type FET having a mushroom type gate electrode for the purpose of suppressing fluctuation of drain current. In the step of covering the surface of the semiconductor layer with an insulating film, and forming a first resist film mask having an opening in the gate electrode forming portion on the insulating film, and then using the first resist film mask as a protective film. A step of etching the insulating film of the gate electrode forming portion in a concave shape; then, removing the first resist film mask and using a second resist film mask having an opening larger than the first resist film mask as an electron beam; Step of forming by an exposure method, and then, using the second resist film mask as a protective film, etch the entire insulating film of the gate electrode forming portion. And a step of exposing the semiconductor layer by etching, and then forming a gate electrode in the gate electrode forming portion.

[Industrial field of application] The present invention relates to a method for manufacturing a semiconductor device, particularly to MESFET, H
The present invention relates to a method for forming a gate electrode of a Schottky junction type semiconductor device such as EMT.

GaAs-based MESFETs and HEMTs are widely used for satellite communications, terrestrial microwave communications, etc., but there is a demand for further improvements in their device characteristics.

[Prior Art] FIG. 3 is a sectional view of a HEMT, in which 1 is a semi-insulating (SI−) GaAs substrate, 2 is an i-GaAs layer (buffer layer), and 3 is n ^+.
-AlGaAs layer (electron supply layer), 4 is a gate electrode made of Al, 6
Is a spacer insulating film made of a SiO ₂ film, and 7 is a source electrode and a drain electrode made of AuGe / Ni / Au electrodes. The principle of operation is that the energy level of the conduction band is higher in the AlGaAs layer than in the GaAs layer, so electrons move from the n-AlGaAs layer to the i-GaAs layer, and the i-GaAs layer at the i-GaAs / n-AlGaAs interface Two-dimensional electron gas (electron channel; shown by dotted line) is generated on the side,
It operates at an extremely high speed under the control of the gate voltage. In such a structure, a Schottky junction is formed between the gate electrode and the active layer, and the junction is particularly important.

FIGS. 4 (a) to 4 (d) show cross-sectional views in the order of the conventional forming process, which will be described step by step. Refer to FIG. 4 (a); i-GaAs layer 2, on the Si-GaAs substrate 2, n ⁺ −A
lGaAs layer 3 is epitaxially grown, the surface of which is covered with a spacer insulating film consisting of Si ₃ N ₄ film 5 and SiO ₂ film 6 by the CVD (chemical vapor deposition) method, and further spacer insulation is performed using a photo process. The film is selectively removed, and the source electrode and the drain electrode 7 are formed in the removed portion. Next, a first resist film mask 8 having a gate electrode forming portion opened is formed on the upper surface thereof, but since the opening dimension is a fine submicron pattern of 0.5 μm or less, highly precise patterning is impossible by the light exposure method. Then, a first resist film mask is formed by using the electron beam exposure method. In this process diagram, i-GaAs is used.
Only the layers above the layer 2 are shown and the SI-GaAs substrate is not shown.

See FIG. 4 (b); then, the RIE (reactive ion etching) method is used to vertically etch the SiO ₂ film 6 and the Si ₃ N ₄ film 5 with a CF ₄ -based reaction gas,
The gate electrode formation portion is opened to expose the n ⁺ -AlGaAs layer 3.

FIG. 4 (c); Next, after removing the resist film mask 8, a second resist film mask 9 for forming a gate electrode is formed. A second resist film mask is formed.

FIG. 4 (d); Next, Al (aluminum) is deposited on the entire surface including the gate electrode forming portion by electron beam evaporation, and then the resist film mask 9 is removed by lift-off to remove Al. The gate electrode 4 is formed. Then, a mushroom-shaped (mushroom-shaped; T-shaped) gate electrode is formed.

The above is the conventional HEMT forming method. Here, the reason why the mushroom-shaped gate electrode is formed is that if the gate length is simply shortened to form a fine gate electrode, the resistance (Rg) increases in inverse proportion to the cross-sectional area and the noise figure ( Since the NF) decreases, the cross-sectional area is expanded as a gate electrode having such a shape. When the cross-sectional area is expanded, the surface area is expanded, which is useful for reducing the conductor resistance in the GHz high frequency range.

[Problems to be Solved by the Invention] By the way, in the above-described forming method, the SiO ₂ film 6 and the Si ₃ N ₄ film 5 are removed by etching by the RIE method (see FIG. 4B). N ⁺ −AlG exposed during RIE process
When the surface of the aAs layer 3 is hit with ions to be damaged, and when the portion is irradiated with an electron beam to form the second resist film mask 9 (see FIG. 4 (c)), the ions are And electron damage synergize to form high-density defects that capture carriers.

Therefore, the drain current (Idss) is remarkably reduced, and there is a problem that it cannot be recovered by the subsequent heat treatment.

The present invention proposes a method for manufacturing a semiconductor device, which aims to solve the above problems and suppress the fluctuation of the drain current.

[Means for Solving the Problem] The purpose is to cover the surface of a semiconductor layer with an insulating film and to form a first resist film mask having a gate electrode forming portion opened on the insulating film, A step of partially etching the insulating film of the gate electrode forming portion in a concave shape by using the first resist film mask as a protective film; and then removing the first resist film mask from the first resist film mask A step of forming a second resist film mask having a large opening by an electron beam exposure method, and then etching and removing the entire insulating film in the gate electrode forming portion using the second resist film mask as a protective film. To expose the semiconductor layer, and then to form a gate electrode in the gate electrode formation portion.

[Operation] That is, according to the manufacturing method of the present invention, the first resist film mask is used to etch the insulating film in the gate electrode formation portion up to the middle thereof so that the semiconductor layer is not exposed. Then, the entire insulating film is etched with the second resist film mask to expose the semiconductor layer, and a gate electrode is formed in the gate electrode formation portion.

Then, in the formation process, the Schottky junction surface that is joined to the gate electrode is not irradiated with the electron beam, the defects that capture carriers are reduced, and the fluctuation of the drain current is suppressed.

[Examples] Hereinafter, examples will be described in detail with reference to the drawings.

1A to 1E are sectional views in order of steps of the forming method according to the present invention.

See FIG. 1 (a); i-GaAs layer 2 and n ⁺ -AlGaAs layer 3 are epitaxially grown on the SI-GaAs substrate in the same manner as in the prior art.
An insulating film for spacers consisting of Si ₃ N ₄ film 5 (film thickness 500 to 1000Å) and SiO ₂ film 6 (film thickness 2000 to 2500Å) is coated on top of it by a photo process, and then spacers are formed using a photo process. The insulating film is selectively removed to form the source electrode and the drain electrode 7. Then, a first resist film mask 8 having a gate electrode forming portion opened on its upper surface is formed by using an electron beam exposure method.

1 (b); Next, only the SiO ₂ film 6 is selectively etched by a RIE method using a mixed reaction gas of CF ₄ and CHF ₃ . This reaction gas has a SiO ₂ film content of 3 relative to a Si ₃ N ₄ film content.
Since the etching rate is doubled, the SiO ₂ film is removed
_{The 3} N ₄ film can remain.

Next, after removing the resist film mask 8, a second resist film mask 9 for forming a gate electrode is formed by using an electron beam exposure method.

See FIG. 1 (d); then, the Si ₃ N ₄ film 5 is removed by etching using a reactive gas of CF ₄ + O ₂ by the RIE method to expose the n ⁺ -AlGaAs layer 3 in the gate electrode formation portion. Let This time,
The second resist film mask 9 is the first resist film mask 8
A part of the SiO ₂ film 6 is exposed due to the larger opening, but the etching selectivity is Si ₃ N ₄ / SiO ₂ > 5.
The SiO ₂ film is hardly etched.

FIG. 1 (e); Next, Al is deposited on the entire surface including the gate electrode formation portion by the sputtering method, and then the resist film mask 9 is removed by the lift-off method to form the gate electrode 4 made of Al. Form.

In the above example, two layers of the Si ₃ N ₄ film 5 and the SiO ₂ film 6 are formed as the insulating film for the spacer, and n ⁺ − is formed by utilizing the etching selectivity.
This is an example in which the second resist film mask 9 is formed without exposing the AlGaAs layer 3. However, only the SiO ₂ film is used as the insulating film for the spacer, and control etching is performed to make a small amount of SiO ₂ in the gate electrode formation portion. After leaving the film and forming the second resist film mask 9, a method of removing the remaining SiO ₂ film may be adopted.

According to the above-described forming method, the exposed surface of the n ⁺ -AlGaAs layer 3 is not irradiated with the electron beam, so that the carrier traps at the Schottky junction surface are reduced and the fluctuation of the drain current is suppressed. To be Figure 2 (a),
(B) is a characteristic comparison diagram between a HEMT formed by a conventional method and a HEMT formed by a manufacturing method according to the present invention.
In FIG. 2A, the horizontal axis represents the process number and the vertical axis represents the drain current Id.
In ss (mA), the process numbers correspond to those in FIG. 1 and FIG. 4, ... × ... are data by the conventional method, and − ○ − are data by the method according to the present invention. As shown in the figure, according to the forming method of the present invention, the drain current does not decrease, and it is found that the drain current is constant and stable in each process.

Further, in FIG. 2B, the horizontal axis represents the drain current Idss (m
A), vertical axis represents noise figure (NF) and noise minimum incidental gain (Gas)
In the data of the above, ... × ... are curves by the conventional method, and − ○ − are curves by the method according to the present invention. From this, NF is reduced by 0.2db, Ga
s shows an improvement of 1.5db or more. Furthermore, according to the forming method of the present invention, the cut-off frequency (fc) was significantly improved from 23 GHz to 35 GHz. Therefore, if the manufacturing method according to the present invention is applied to a method for forming a gate electrode such as HEMT, the device characteristics can be remarkably improved.

In addition, the above was explained in HEMT, but in addition, GaAs MESFET
Of course, it can be applied to the formation of.

[Effects of the Invention] As is clear from the above description of the embodiments, according to the present invention, a semiconductor device having a mushroom-shaped gate electrode has a great effect in improving its characteristics.

[Brief description of drawings]

1 (a) to 1 (e) are sectional views in order of the forming process according to the present invention, FIG. 2 is a characteristic comparison diagram, FIG. 3 is a sectional view of HEMT, and FIGS. 4 (a) to 4 (d) are conventional. FIG. 6 is a cross-sectional view in order of the forming process. In the figure, 1 is a SI-GaAs substrate, 2 is an i-GaAs layer (buffer layer), 3 is an n ⁺ -AlGaAs layer (electron supply layer), 4 is a gate electrode, 5 is a Si ₃ N ₄ film (spacer insulation). Film), 6 is a SiO ₂ film (spacer insulating film), 7 is a source electrode and a drain electrode, 8 is a first resist film mask, and 9 is a second resist film mask.

Claims (1)

[Claims] 1. A method of manufacturing a Schottky junction type FET having a mushroom type gate electrode, wherein a first resist film mask in which a surface of a semiconductor layer is covered with an insulating film and a gate electrode forming portion is opened on the insulating film. And then etching the insulating film of the gate electrode forming portion in a concave shape by using the first resist film mask as a protective film, and then removing the first resist film mask to remove the first resist film mask. 1
Forming a second resist film mask having an opening larger than that of the resist film mask by an electron beam exposure method, and then using the second resist film mask as a protective film, the insulating film of the gate electrode forming portion. A method of manufacturing a semiconductor device, comprising: a step of exposing the semiconductor layer by etching off the whole thereof; and a step of forming a gate electrode in the gate electrode forming portion.