JP3520625B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oxygen ashing method for stripping a resist applied on a semiconductor substrate, such as a high electron mobility transistor (hereinafter referred to as HEMT) used at high frequency. Used in semiconductor processes.

[0002]

2. Description of the Related Art Monolithic microwave IC (Monolith
ic Microwave Integrated Circuit: hereinafter referred to as MMIC), it is necessary to improve device characteristics such as HEMT constituting the MMIC in order to improve high frequency performance such as noise figure and gain. A factor that affects the device characteristics such as HEMT is the parasitic resistance between the source and drain electrodes and the gate electrode. As methods for reducing this parasitic resistance, Japanese Patent Laid-Open No. 6-244219 and Japanese Patent Laid-Open No. 62-145779 have been proposed.
The technique disclosed in Japanese Patent Laid-Open No. 6-244219 includes at least a channel layer and an electron supply layer on a semiconductor substrate, and a source electrode and a drain electrode are formed in contact with side surfaces of the channel layer to form a gate electrode. Are formed on the channel layer, and the positions of the upper surfaces of the source electrode and the drain electrode are positioned on the same plane as or lower than the position of the bottom surface of the gate electrode. With such a configuration, it is possible to avoid the arrangement relationship in which the gate electrode and the source electrode and the drain electrode are close to and face each other, and the interval between the gate electrode and the source electrode and the drain electrode is reduced to reduce the parasitic resistance. It is to try. Japanese Patent Laid-Open No. 62-1457
The technique disclosed in Japanese Patent Laid-Open No. 79 is on an InP substrate.
An nGaAs mixed crystal semiconductor layer is provided, a wide bandgap layer made of an InP and InAlAs mixed crystal semiconductor layer is provided on the mixed crystal semiconductor layer, and the gate electrode and the gate electrode are opposite to each other on the wide bandgap layer. To form a source electrode and a drain electrode, and the gate electrode is an I layer among layers forming the wide band gap layer.
The n-type impurity is ion-implanted in contact with the nAlAs mixed crystal semiconductor layer and at least between the source electrode and the gate electrode and between the gate electrode and the drain electrode. With such a structure, the gate characteristics are improved and the source resistance is reduced.

[0003]

However, in these disclosed techniques, not only the process cost is increased by the complicated manufacturing process such as ion implantation but also the parasitic resistance between the source and drain electrodes and the gate electrode is increased.
It does not mention the influence of peripheral processes such as oxygen ashing for resist stripping, which is essential for semiconductor processes. In fact, depending on the combination of the semiconductor material used for HEMT or the like and the manufacturing process, increase in parasitic resistance between the source and drain electrodes and gate electrode of HEMT or the like,
Furthermore, the current situation is that the device characteristics are deteriorated. For example, InAl is used as a doped layer for supplying carriers.
InGa is used as a carrier transit layer in which a current flows, using an As layer.
Also in the HEMT substrate using the As layer, the semiconductor process causes an increase in the sheet resistance of the semiconductor substrate, which causes an increase in the parasitic resistance between the source and drain electrodes and the gate electrode. Has become. The inventors of the present application have found that the cause of the increase in the sheet resistance of the HEMT substrate is the increase in the oxygen concentration on the surface of the semiconductor substrate due to the oxygen ashing for resist stripping, and the ohmic contact of the source and drain electrodes to be performed thereafter with the semiconductor substrate. It was found that it was due to heat treatment (alloying) for obtaining.

Therefore, in view of the above problems, it is an object of the present invention to provide a semiconductor device having a reduced sheet resistance and improved device characteristics at high frequencies.

[0005]

In order to solve the above-mentioned problems, the structure of the present invention is the heat treatment such as alloying for obtaining ohmic contact between an ohmic electrode and a semiconductor conductive layer according to any one of claims 1 to 4 . Before performing the step of removing the resist by a method that does not oxidize the surface of the semiconductor conductive layer (a method other than oxygen ashing), a resist residue generated in the step of forming an ohmic electrode after the heat treatment and before the heat treatment, and a heat treatment. This is a technical means that includes a step of removing the resist and its residue afterwards by oxygen ashing.

[0006]

[0007]

According to the first aspect of the present invention having the above structure, the resist existing on the surface of the semiconductor conductive layer before the heat treatment step is removed without oxidizing the surface, and the surface of the semiconductor conductive layer is removed after the heat treatment step. The resist and the resist residue present in the are removed by oxygen ashing. This has the effect of suppressing the diffusion of oxygen into the semiconductor conductive layer during the heat treatment process and suppressing the increase in sheet resistance. Further, since the resist residue before and after the heat treatment can be removed by the oxygen ashing after the heat treatment, it is possible to reduce the variation in the etching amount due to the resist residue in the steps such as etching after the heat treatment . In addition, the substrate is
The semiconductor conductive layer is composed of at least In _0.8 Ga.
_0.2 As channel layer and In _0.53 Ga _0.47 As
An electron distribution control layer composed of In _0.52 Al _0.48 As
And an n-type doped layer of In _0.52 Al _0.48 As.
Gate contact layer and In _0.53 Ga _0.47 As
InAlAs
A / InGaAs HEMT can be formed (claim 1).

[0008]

In the second invention, when the ohmic electrode is formed so as to contact the semiconductor conductive layer, the ohmic electrode constituent material is diffused into the semiconductor conductive layer by heat treatment at a predetermined heat treatment temperature. As a result, the ohmic electrode is brought into ohmic contact with the semiconductor conductive layer, and after the heat treatment, oxygen ashing is performed at a substrate temperature lower than the heat treatment temperature. As a result, the oxygen concentration on the surface of the semiconductor conductive layer increases due to oxygen ashing after the heat treatment, but the diffusion of oxygen into the semiconductor conductive layer does not significantly increase the sheet resistance, and the increase in sheet resistance can be suppressed (claim Item 2) .

In the third invention, a step of forming the ohmic electrode with the source electrode and the drain electrode and forming the semiconductor conductive layer in an island shape by mesa etching is further provided, and the source electrode and the drain electrode are formed before the heat treatment. The resist is removed without oxidizing the surface of the semiconductor conductive layer exposed between them, and after heat treatment, the resist and the resist residue existing on the surface of the semiconductor conductive layer between the source electrode and the drain electrode are removed by oxygen ashing. Then, a recess groove is formed on the surface of the semiconductor conductive layer between the source electrode and the drain electrode, and a gate electrode is formed in Schottky contact with the bottom of the recess groove. This makes it possible to suppress an increase in sheet resistance and suppress an increase in parasitic resistance between the source electrode and the drain electrode and the gate electrode, thereby improving the operating frequency of the field-effect transistor, achieving high gain at high frequencies, low noise figure, etc. It is possible to obtain good device characteristics (claim 3) .

[0011]

[0012] In a fourth aspect of the present invention, a buffer layer made of In _0.52 Al _0.48 As between the substrate and the channel layer, and an In _0.52 Al _0.48 between the electron distribution control layer and the doped layer
A spacer layer made of As is provided. As a result, the crystallinity of the channel layer can be improved and the traveling speed of electrons in the electron distribution control layer can be improved ( claim 4 ) .

[0013]

[0014]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) The present invention will be described below based on specific embodiments. FIG. 1 shows a semiconductor device 100 according to the present invention.
FIG. 3 is a schematic structural diagram showing a manufacturing method of. First, InP
On a semi-insulating semiconductor substrate 11 made of GaAs or
The semiconductor conductive layer 12 is mesa-etched to form the island-shaped semiconductor conductive layer 12. Then, an ohmic electrode 13 made of AuGe / Ni / Au or the like is formed on the semiconductor conductive layer 12 by a method such as metal lift-off (FIG. 1).
(A)). In this mesa etching and metal lift-off process, cleaning with an organic solvent such as acetone or remover is performed to remove the resist. Here, the semiconductor conductive layer 1
2 is MESFET (Metal Semiconductor FET: metal-
(Semiconductor field effect transistor) and HEMT. When the present invention is applied to MESFET, HEMT, etc., two ohmic electrodes 13 are formed.
Serves as a source electrode and a drain electrode, and a Schottky gate electrode (not shown) is formed on the semiconductor conductive layer 12 between the ohmic electrodes 13.

Subsequently, the ohmic electrode 13 is alloyed with the semiconductor conductive layer 12 to obtain ohmic contact, and the alloy layer 14 in which the electrode material of the ohmic electrode 13 is diffused is formed in the semiconductor conductive layer 12 (FIG. 1).
(B)). Here, alloying is a heat treatment for diffusing an ohmic electrode material into a semiconductor. For example, when AuGe / Ni / Au is used as the ohmic electrode, heat treatment is performed for several minutes at a temperature near the eutectic temperature of AuGe in an atmosphere gas such as nitrogen. Removing ohmic contact between the ohmic electrode 13 and the semiconductor conductive layer 12 by alloying, and removing the resist residue before alloying;
Oxygen ashing is performed for the purpose of removing the resist and removing the resist residue after the alloying, and the oxide layer 15 is formed on the surface of the semiconductor substrate by the ashing (FIG. 1C).
At this time, oxygen ashing is performed by lowering the substrate temperature below the alloy temperature.

By forming the semiconductor device 100 by such a method, in a photo step such as mesa etching of the semiconductor conductive layer 12 and metal lift-off of the ohmic electrode 13, a method other than oxygen ashing such as cleaning with an organic solvent is performed. Since the resist is peeled off in step 1, the surface of the semiconductor conductive layer 12 can be suppressed from being oxidized. Thereby, diffusion of oxygen from the oxide layer on the surface of the semiconductor conductive layer 12 due to alloying can be suppressed,
It is possible to suppress an increase in sheet resistance of the semiconductor conductive layer 12. Also, by oxygen ashing after alloying,
Since the residue of the resist generated in the steps before and after the alloying can be removed, it is possible to prevent the variation of the etching amount due to the resist residue in the etching step such as the recess etching for forming the gate electrode after the alloying. In the oxygen ashing after alloying, since the substrate temperature is kept lower than the alloy temperature, the oxygen concentration on the surface of the semiconductor conductive layer 12 increases, but the diffusion of surface oxygen to the semiconductor conductive layer 12 is
The sheet resistance of the semiconductor conductive layer 12 cannot be significantly increased.

On the other hand, as a comparative example, a method of manufacturing a semiconductor device 200 configured to remove the resist residue after the ohmic electrode formation by oxygen ashing is schematically shown in FIG.
Shown in. A semiconductor conductive layer 22 is formed in an island shape on the semiconductor substrate 21 by mesa etching, and an ohmic electrode 23 for obtaining ohmic contact is formed on the semiconductor conductive layer 22 by a method such as metal lift-off (FIG. 2A). ).
Next, by removing the resist residue after forming the ohmic electrode 23 by oxygen ashing, the ohmic electrode 2
An oxide layer 24 having an oxide layer thickness 25 is formed on the surface of the semiconductor conductive layer 22 exposed between the layers 3 (FIG. 2B).
Then, alloying is performed, and the alloy layer 2 in which the material forming the ohmic electrode 23 is diffused in the semiconductor conductive layer 22.
8 is formed, and the ohmic electrode 23 is formed on the semiconductor conductive layer 22.
Ohmic contact can be made (Fig. 2
(C)).

However, in this method, oxygen is diffused from the oxide layer 24 toward the semiconductor conductive layer 22 at the time of alloying, and the oxide layer 26 having the oxide layer thickness 27 larger than the oxide layer thickness 25 is formed.
Are formed, and the sheet resistance of the semiconductor conductive layer 22 increases. In particular, in the case of a HEMT in which the semiconductor conductive layer 22 is composed of a plurality of extremely thin semiconductor layers, the semiconductor layer on the surface is oxidized, so that the resistance of the oxidized semiconductor layer itself is increased and the semiconductor layer is accumulated in the channel. Carriers are reduced, and the sheet resistance of the semiconductor conductive layer 22 exposed between the ohmic electrodes 23 is significantly increased. Therefore, by suppressing the formation of the oxide film on the surface of the semiconductor conductive layer 12 before alloying as shown in FIG. 1, it is possible to suppress the increase in the sheet resistance of the semiconductor device 100.

(Second Embodiment) FIG. 3 is a schematic structural diagram in the case where the method for manufacturing a semiconductor device according to the present invention is applied to a HEMT substrate. Substrate 30 made of semi-insulating InP
A buffer layer 30 made of In _0.52 Al _0.48 As
2 (film thickness 100 to 200 nm), In _0.8 Ga _0.2 As channel layer 303 (film thickness 16 nm), In _0.53 Ga _0.47 As
Distribution control layer 304 (thickness: 4 nm), In _0.52
A spacer layer 305 (film thickness 5 nm) made of Al _0.48 As,
Doped layer 306 (film thickness 10: In _0.52 Al _0.48 As)
nm), a gate contact layer 307 (film thickness 10 nm) made of In _0.52 Al _0.48 As, and a cap layer 308 (film thickness 20 nm) made of In _0.53 Ga _0.47 As are sequentially laminated, and then subjected to mesa etching to obtain a buffer layer 302. The upper semiconductor layer is formed into an island shape (FIG. 3A). At this time, the resist is stripped with an organic solvent such as acetone or remover. still,
Of the above semiconductor layers, the cap layer 308 and the doped layer 30.
6 is doped with Si at a high concentration (carrier concentration of about 1 × 10 ¹⁹ cm ⁻³ ).

Next, the source electrode 309 and the drain electrode 310 made of AuGe / Ni / Au or the like are formed by a method such as metal lift-off. At this time, the resist is stripped with an organic solvent as in the mesa etching. After this,
Near the eutectic temperature of AuGe in an atmosphere gas such as nitrogen (40
Source electrode 30 after alloying for 2 minutes at around 0 ℃
9 and the electrode material forming the drain electrode 310 form an alloy layer 311 diffused deeper than the channel layer 303, and ohmic contact can be obtained with the channel layer 303 in which the source electrode 309 and the drain electrode 310 run electrons. (FIG.3 (b)). Before alloying here,
Mesa etching, source electrode 309 and drain electrode 3
In the photo step such as the metal lift-off of 10, the method of washing with an organic solvent such as acetone or remover is used for removing the resist and the resist residue after the resist is removed, and oxygen ashing is not used.

Subsequently, a wiring 312 made of Au or the like is formed on the source electrode 309 and the drain electrode 310 by a method such as metal lift-off, and then the cap layer exposed between the source electrode 309 and the drain electrode 310 by oxygen ashing. The resist residue on 308 is removed. At this time, oxygen ashing is performed by lowering the substrate temperature below the alloy temperature. By this oxygen ashing, the cap layer 30
An oxide layer 313 is formed on the surface of No. 8 (FIG. 3C).
Here, the resist residue on the cap layer 308 means not only the resist residue in the photo process for forming the wiring 312 after alloying by metal lift-off, but also mesa etching and metal lift-off of the source electrode 309 and the drain electrode 310. It also contains the resist residue by the photo process before alloying.

After that, the oxide layer 313 between the source electrode 309 and the drain electrode 310 and the cap layer 308 are removed by etching, and a recess groove 314 is formed so that the gate contact layer 307 is exposed. And recess groove 3
A gate electrode 315 is formed on the exposed gate contact layer 307 in 14 in Schottky contact. The gate electrode 315 is formed on the resist pattern obtained by etching the recess groove 314 by Ti / electrodeposition by a method such as electron beam evaporation.
After forming a gate electrode constituent material such as Pt / Au by vapor deposition, the gate electrode constituent material on the resist is dissolved and removed by an organic solvent such as acetone (metal lift-off method). In this way, the HEMT 300 is formed (FIG. 3D).

With such a structure, in a photo process such as mesa etching before alloying and metal lift-off of the source electrode 309 and the drain electrode 310, the resist is removed by a method other than oxygen ashing such as cleaning with an organic solvent. By peeling off, the cap layer 3
It is possible to suppress the oxidation of the 08 surface. In addition, the mesa etching before the alloying, the removal of the resist residue in the photo process of the source electrode 309 and the drain electrode 310, and the resist ashing and the removal of the resist residue in the photo process when the wiring 312 is formed by metal lift-off are performed after the oxygen ashing. By doing so, it is possible to suppress the formation of an oxide layer on the surface of the cap layer 308 before alloying. Thereby, the diffusion of the oxidation from the oxide layer on the surface of the cap layer 308 due to alloying to the semiconductor layer including the cap layer 308 can be suppressed, and the increase of the sheet resistance can be suppressed.

Further, by oxygen ashing after alloying, the cap layer 3 is formed by a photo process before and after alloying.
Since the resist residue on 08 can be removed, the gate electrode 3
It is possible to prevent variations in the etching amount due to the resist residue in the step of etching the recess groove 314 for forming 15. By keeping the substrate temperature during the oxygen ashing lower than the alloying temperature, even if the oxygen ashing is performed after the alloying, the cap layer 308 is formed.
Although the oxygen concentration on the surface increases, the cap layer 3
The diffusion of oxygen on the 08 surface does not significantly increase the sheet resistance between the source electrode 309 and the drain electrode 310.

Here, FIG. 5 shows the HEMs with and without oxygen ashing before alloying.
The change of the sheet resistance of T300 is shown. The initial stage on the horizontal axis in FIG. 5 means immediately after each semiconductor layer is epitaxially grown on the substrate 301. Further, after alloying means immediately after alloying in FIG. 3B, and after ashing means immediately after oxygen ashing in FIG. 3C. Furthermore, the presence / absence of ashing before alloying means that the source electrode 3 in FIG.
This is whether or not oxygen ashing is performed to remove the resist or remove the resist residue after the formation of the 09 and the drain electrode 310.

For oxygen ashing, a parallel plate type plasma asher is used, reaction pressure is 2 Torr, oxygen flow rate is 4 SLM,
3% hydrogen / nitrogen flow 240SCCM, RF power 800W, basic temperature
The ashing time was 2 minutes at 200 ° C. The change in oxygen concentration on the surface of the cap layer 308 due to the oxygen ashing was measured by Auger analysis.
68.8at%, 83.7at% after oxygen ashing (both are ratios to In), and cap layer 3 is formed by oxygen ashing.
08 The oxygen concentration on the surface increases.

In FIG. 5, when oxygen ashing is performed before alloying, the sheet resistance is 2 due to alloying.
It has more than doubled. This is because oxygen on the surface of the cap layer 308, the concentration of which has been increased by oxygen ashing, is allowed to flow to the cap layer 308 and further to the cap layer 3.
08 lower gate contact layer 307 and doped layer 30
The band structure from the cap layer 308 to the channel layer 303 is changed due to the diffusion into the channel layer 6 and the like, so that the amount of carriers accumulated in the quantum well of the channel layer 303 is decreased and the sheet resistance of the HEMT 300 is increased. It is thought that

On the other hand, when oxygen ashing before alloying is carried out and oxygen ashing is carried out after alloying to remove the resist residue, it is understood that there is almost no increase in sheet resistance due to alloying. Further, the oxygen ashing after alloying did not cause a significant increase in sheet resistance. Although the sheet resistance is not increased by the oxygen ashing after alloying in FIG. 5, the relationship between the oxygen ashing time and the sheet resistance is shown in FIG. It can be seen from FIG. 4 that the sheet resistance hardly increases depending on the oxygen ashing time, and there is no problem even if oxygen ashing is added after alloying. By manufacturing the HEMT 300 by the method shown in this embodiment, it is possible to suppress an increase in sheet resistance, improve the operating frequency, and obtain good device characteristics such as high gain and low noise figure at high frequencies. You can

Although the buffer layer 302 is disposed between the substrate 301 and the channel layer 303 in this embodiment, the buffer layer 302 is a layer provided to improve the crystallinity of the channel layer 303. The buffer layer 302 may not be provided if necessary. Although the spacer layer 305 is provided on the electron distribution control layer 304 in this embodiment, the spacer layer 305 is a layer provided to improve the traveling speed of electrons in the electron distribution control layer 304, and is necessary. Accordingly, the spacer layer 305 may not be provided.

(Third Embodiment) FIG. 6 is a schematic structural view showing the configuration of the third embodiment according to the present invention. The feature of this embodiment is that the oxide layer 66 formed on the surface of the semiconductor conductive layer 62 during oxygen ashing is removed before alloying, and the manufacturing method thereof will be described below. InP and GaAs
The semiconductor conductive layer 62 formed on the semi-insulating semiconductor substrate 61 made of, for example, is mesa-etched to form the island-shaped semiconductor conductive layer 62 (FIG. 6A). Next, an ohmic electrode 63 made of AuGe / Ni / Au or the like is formed on the semiconductor conductive layer 62 by a method such as metal lift-off, and the resist residue at the time of mesa etching or formation of the ohmic electrode 63 is removed by oxygen ashing. An oxide layer 66 is formed on the surface of the semiconductor conductive layer 62 between 13 (see FIG. 6).
(B)). Subsequently, the oxide film 66 formed on the surface of the semiconductor conductive layer 62 between the ohmic electrodes 63 is removed by etching with diluted hydrofluoric acid or the like. Then, the ohmic electrode 63 performs alloying on the semiconductor conductive layer 62 to obtain ohmic contact, and the ohmic electrode 6 is applied to the semiconductor conductive layer 62.
The alloy layer 64 in which the electrode material forming 3 is diffused is formed (FIG. 6C). Then, the resist residue before the alloying is removed, and the oxygen ashing is performed for the purpose of removing the resist and removing the resist residue after the alloying, and the oxide layer 65 is formed on the surface of the semiconductor conductive layer 62 by the oxygen ashing (FIG. 6). (D)). In this way, the semiconductor device 60
0 is formed.

The presence of the oxide layer 66 formed on the surface of the semiconductor conductive layer 62 during oxygen ashing before the alloying causes the increase of the sheet resistance of the semiconductor conductive layer 62. Therefore, as shown in this embodiment, the alloying is performed. By previously removing the oxide layer 66 formed on the surface of the semiconductor conductive layer 62, an increase in sheet resistance of the semiconductor conductive layer 62 due to alloying can be suppressed. Similar to this example,
Even when oxygen ashing is performed on the mesa-etched structure (see FIG. 6A), the oxide layer 66 on the surface of the semiconductor conductive layer 62 is removed by a method such as etching with diluted hydrofluoric acid after oxygen ashing. It is possible to suppress an increase in sheet resistance due to alloying.

As described above, according to the present invention, the resist on the surface of the semiconductor conductive layer is removed without oxidizing the semiconductor conductive layer before the heat treatment, and the resist and the resist residue on the surface of the semiconductor conductive layer are removed by oxygen ashing after the heat treatment. By doing so, it is possible to reduce the oxygen concentration on the surface of the semiconductor conductive layer and prevent oxygen from diffusing into the semiconductor conductive layer during heat treatment,
The sheet resistance of the semiconductor device can be suppressed. Further, the resist residue on the surface of the semiconductor conductive layer can be removed by oxygen ashing after the heat treatment, and it is possible to prevent variations in the etching amount due to the resist residue during etching after the heat treatment.

[Brief description of drawings]

FIG. 1 is a schematic structural diagram showing a configuration of a first embodiment according to the present invention.

FIG. 2 is a schematic structural diagram showing a manufacturing method when alloying is performed after removing a resist residue by oxygen ashing.

FIG. 3 is a schematic structural diagram showing a configuration of a second embodiment according to the present invention.

FIG. 4 is a graph showing the relationship between ashing time after alloying and sheet resistance.

FIG. 5 is a graph showing changes in sheet resistance with and without oxygen ashing before alloying.

FIG. 6 is a schematic structural diagram showing the configuration of a third embodiment according to the present invention.

[Explanation of symbols]

11 Semiconductor substrate 12 Semiconductor conductive layer 13 Ohmic electrode 14 Alloy layer 15 Oxidized layer 100 semiconductor devices 300 HEMT 301 substrate 302 buffer layer 303 channel layer 304 electron distribution control layer 305 Spacer layer 306 Dope layer 307 Gate contact layer 308 Cap layer 309 Source electrode 310 drain electrode 311 Alloy layer 312 wiring 313 oxide layer 314 recess groove 315 Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/3065

Claims (4)

(57) [Claims] 1. A semiconductor device having at least a semiconductor conductive layer on a semi-insulating substrate, which is a manufacturing method having at least a heat treatment step, and is present on the surface of the semiconductor conductive layer before the heat treatment step. resist, and removing without oxidizing the surface, the resist and resist residue present on the surface of the semiconductor conductive layer after the heat treatment step e Bei and removing by oxygen ashing, the substrate is of InP The semiconductor conductive layer is at least In _0.8 Ga _0.2 As
A channel layer composed of In _0.53 Ga _0.47 As
N type consisting of electron distribution control layer and In _0.52 Al _0.48 As
With a doped layer of In _0.52 Al _0.48 As
Contact layer and an n-type key consisting of In _0.53 Ga _0.47 As.
A method for manufacturing a semiconductor device, comprising: a cap layer . 2. The method further comprises the step of forming an ohmic electrode in contact with the semiconductor conductive layer, wherein the heat treatment step comprises forming a material forming the ohmic electrode in the semiconductor conductive layer at a predetermined heat treatment temperature. The semiconductor device according to claim 1, wherein the ohmic electrode is diffused into ohmic contact with the semiconductor conductive layer, and the substrate temperature during the oxygen ashing is lower than the heat treatment temperature in the heat treatment step. Production method. 3. The ohmic electrode comprises a source electrode and a drain electrode, further comprising a step of forming the semiconductor conductive layer in an island shape on the substrate by mesa etching, wherein the surface of the semiconductor conductive layer is oxidized. The step of removing the resist without removing the resist present on the surface of the semiconductor conductive layer between the source electrode and the drain electrode, the resist and the resist present on the surface of the semiconductor conductive layer In the step of removing the residue by oxygen ashing, the resist and the resist residue existing on the surface of the semiconductor conductive layer between the source electrode and the drain electrode are removed, and the resist between the source electrode and the drain electrode is removed. A step of forming a recess groove on the surface of the semiconductor conductive layer, and a gate on the semiconductor conductive layer at the bottom of the recess groove. The method of manufacturing a semiconductor device according to claim 2, characterized in that a step of forming an electrode Schottky contact. 4. The semiconductor conductive layer includes a buffer layer made of In _0.52 Al _0.48 As between the substrate and the channel layer, and In _0.52 A between the electron distribution control layer and the doped layer.
_{4. The} method for manufacturing a semiconductor device according to claim 1, further comprising a spacer layer made of _0.48 As.