JP2526385B2 - Method for manufacturing field effect transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a compound semiconductor field effect transistor in which the distance between a gate electrode and a source electrode / drain electrode is shortened to the limit to improve the characteristics. Is.

(Prior Art) Research on compound semiconductor devices has been vigorously carried out to realize high-speed and high-frequency devices. An example thereof is a gallium arsenide field effect transistor (hereinafter, also abbreviated as GaAs FET) having a recess structure gate electrode. The following documents (Technical report of IEICE)
The structure of a conventional GaAs FET and a method of manufacturing the same will be briefly described by using an example of an inverted structure HEMT (High Electron Mobility Transistor) disclosed in ED86-57 (1986) PP.57-64).

FIG. 3 is a conventional reverse structure disclosed in the above-mentioned document.
It is sectional drawing which shows HEMT roughly. In order to avoid complication of the drawing, some hatching showing a cross section is omitted.

In FIG. 3, reference numeral 11 indicates Cr (chromium) doping.
HB (Horizontal Bridgman) Semi-insulating GaAs substrate. this
On the GaAs substrate 11, from the substrate side, as a buffer layer,
Undoped GaAs layer 13, AlGaAs layer 15, n ⁺ type AlGaAs layer 17 as a carrier supply layer, undoped as a spacer layer
AlGaAs layer 19, undoped GaAs layer 21 as a channel layer,
Further, the n-type GaAs layer 23 and the n ⁺ -type GaAs layer 25 are provided in this order. In FIG. 3, 21a indicates a two-dimensional electron gas, and 35 indicates an element isolation region. Furthermore, on this GaAs substrate 11, a recess 27 is provided from the surface of the n ⁺ type GaAs layer 25 to the n type GaAs layer 23.
A gate electrode indicated by 29 is provided in the recess 27. Further, a source electrode indicated by 31 is provided at a position separated from the edge portion 27a of the recess 27 on one of the regions on both sides of the recess 27 of the n ⁺ type GaAs layer 25, and on the other region. A drain electrode indicated by 33 is provided at a position separated from the edge 27b of the recess 27. Source electrode 31 here
The reason why the drain electrode 33 and the drain electrode 33 are provided apart from the edge portions 27a and 27b of the recess 27, that is, apart from the gate electrode 29 is that the source electrode and the drain electrode of the conventional GaAs FET are AuGe-Ni-Au ( This is because the p-type GaAs layer is made of an alloy material such as Au-Zn). In other words, conventionally, AuGe / Ni / Au was laminated as a material for forming the source electrode 31 and the drain electrode 33, and this was heat-treated (sintered) and alloyed, and Ge was diffused into the n ⁺ GaAs layer to achieve a high concentration. An ohmic contact is formed by forming an impurity region (alloyed layer), but the alloyed layer exudes to the gate electrode side, so if the gap between the gate electrode and the source or drain electrode is too narrow, the Schottky characteristics, etc. deteriorate. Will be done. For such a phenomenon, for example, refer to the literature (Journal of Vacuum Science,
Technology (J.Vac.Sci.Technol.) B5. (1987) P.103
0). Therefore, it is necessary to separate the source electrode and the drain electrode from the gate electrode by a predetermined distance.

Further, the conventional GaAs FET shown in FIG. 3 was manufactured by the method described below, for example. FIG. 4 (A)-
FIG. 6C is a diagram used for the description, and is a diagram showing a state of the element in a main process of the manufacturing process with a cross-sectional view.
In these drawings, hatching showing a cross section is partially omitted.

First, the GaAs layer 13, the AlGaAs layer 15, the n ⁺ -type AlGaAs layer 1 are formed on the GaAs substrate 11 by, for example, the MBE (molecular beam epitaxy) method.
7, undoped AlGaAs layer 19, undoped GaAs layer 21, n-type G
The aAs layer 23 and the n ⁺ type GaAs layer 25 are grown in this order. Next, after a resist pattern (not shown) is formed on the n ⁺ GaAs layer 25 to expose the element isolation region formation planned region,
¹⁶ O ⁺ ions are implanted into the n ⁺ GaAs layer 25 and the like to form an element isolation region 35 to isolate the elements (see FIG. 4 (A)).

Next, the resist pattern used for element isolation is removed, and then the known thin film forming method and lift-off method are used.
AuGe / Ni / Au electrodes are formed as the source electrode 31 and the drain electrode 33 of the GaAs FET at predetermined positions on the n ⁺ GaAs layer 25, and thereafter sintering is performed to make ohmic contact (see FIG. 4 (B)). .

Next, on the n ⁺ GaAs layer 25 including the ohmic electrodes 31 and 33, a resist pattern 37 having an overhanging cross section is formed.
Is formed, and then the recess 27 is formed by low acceleration voltage Ar ion milling using this as a mask. GaAs FET
The threshold voltage of can be controlled by this ion milling amount (4th
(See FIG. (C)). Then, for example, Al for forming a gate electrode is vapor-deposited on the resist pattern 37 and the recess 27, and then the gate electrode 29 is formed by self-alignment by the lift-off method (see FIG. 3).

(Problems to be solved by the invention) However, in the conventional GaAs FET, since the source electrode and the drain electrode are obtained by the ohmic electrode formation method by the alloying method, the distance between the gate electrode and the source electrode and the drain electrode is narrowed. Was limited for the reasons already explained. For this reason, there is a problem in that it is impossible to further reduce the source resistance by narrowing the gap between the gate electrode and the source and drain electrodes and improve the characteristics of the FET.

The present invention has been made in view of such points,
Therefore, an object of the present invention is to provide a compound semiconductor field effect transistor in which the distance between the gate electrode and the source and drain electrodes is significantly shortened as compared with the prior art, and a method for manufacturing the same.

(Means for Solving the Problems) In order to achieve this object, the present invention provides a field effect transistor having a recess structure,
A source electrode is provided in one of regions on both sides of the recess of the compound semiconductor layer so as to extend to the edge of the recess, and the source and drain electrodes are ohmic electrodes. In manufacturing a field effect transistor, a step of forming, on the compound semiconductor layer, an ohmic electrode layer formed of a semiconductor layer having a high impurity concentration that does not react with the compound semiconductor layer; and the field effect transistor on the ohmic electrode layer. A step of forming an element isolation pattern that exposes the element isolation area formation planned area, a step of forming the element isolation area by ion implantation using the element isolation pattern as a mask, and the element isolation pattern as a mask As a step of removing an exposed portion of the ohmic electrode layer, After the gate pattern to expose regions corresponding to the gate electrode formation region of the remaining portion of the formation, characterized in that it comprises a step of performing recess etching and the gate electrode formed using the gate pattern as a mask.

Note that the ohmic electrode layer made of a semiconductor layer having a high impurity concentration that does not react with the compound semiconductor layer here is formed of, for example, Ge (germanium) containing As (arsenic) at a high concentration such as 10 ¹⁹ cm ⁻³ . It can be composed of substances.

(Operation) On the other hand, according to the method for manufacturing the field effect transistor of this application, the pattern for element isolation is used not only for element isolation but also for the portion exposed from the element isolation pattern of the ohmic electrode layer. Also used to remove. The gate pattern is also used as a mask for recess etching, a lift-off mask for forming a gate electrode, and a mask for dividing the ohmic electrode layer and patterning the source and drain electrodes. In this way, each pattern is shared in a plurality of steps. Further, the element isolation region, the gate electrode, the source electrode and the drain electrode are formed in a self-aligned manner.

(Example) Hereinafter, a method for manufacturing a field effect transistor according to the present invention will be described with reference to an example applied to an inverted HEMT. It should be noted that the drawings used in the following description of each embodiment are only schematically illustrated to the extent that the present invention can be understood, and therefore, the dimensions, shapes, arrangement relationships, etc. of each constituent component are limited to the illustrated examples. It should be understood that this is not what is done. Also, in each of the drawings used in the following description, the same components are denoted by the same reference numerals, and the same components as those already described with reference to FIG. 3 and FIG. The same numbers as those used in the figure are attached.

Description of Structure of Field-Effect Transistor FIG. 1 is a sectional view schematically showing an inverted HEMT manufactured according to the present invention. In order to avoid complication of the drawing, some hatching showing a cross section is omitted.

In FIG. 1, reference numeral 11 is a Cr (chromium) -doped HB (horizontal Bridgman) semi-insulating GaAs substrate used for manufacturing the inverted HEMT. A buffer layer and an operation layer are provided on the GaAs substrate 11, and specifically, from the substrate side, as a buffer layer, an undoped GaAs layer 13, an AlGaAs layer 15,
N ⁺ type AlGaAs layer 17 as a carrier supply layer, undoped AlGaAs layer 19 as a spacer layer, undoped GaAs layer 21 as a channel layer, and n type GaAs layer 23 and n ⁺ type GaAs layer
25 are provided in this order. In FIG. 1, 21a indicates a two-dimensional electron gas, and 35 indicates an element isolation region. Furthermore, n-type Ga is formed on the GaAs substrate 11.
A recess 27 having a depth reaching the As layer 23 is provided, and a gate electrode 29 is provided in the recess 27. In addition, the recess of the compound semiconductor layer (n ⁺ GaAs layer 25 in this case)
A source electrode 41 and a drain electrode 43 are provided in one of the regions on both sides of the recess 27 so as to extend to the edges 27a and 27b of the recess 27, respectively. And these source electrodes 41
The drain electrode 43 is an ohmic electrode that does not react with the compound semiconductor used here (hereinafter referred to as "non-alloy ohmic electrode"). Although it is a constituent material of the non-alloy ohmic electrode, in this embodiment, it is composed of As (arsenic) such as Ge (germanium) contained at a high concentration such as 10 ¹⁹ cm ⁻³ order. According to the inverted structure HEMT shown in FIG.
In addition, since the source electrode 41 and the drain electrode 43 are much closer than in the conventional case, the source resistance is further reduced, and the height can be increased to 9 m.

It should be noted that the present invention is not applicable only to the inverted structure HEMT, and for example, a normal HEMT having a recess structure is used.
It is widely applicable to field effect transistors of other structures such as MESFET. Therefore, in the embodiment, since the present invention is applied to the inverted HEMT having the purpose of suppressing the gate capacitance, the compound semiconductor layer for providing the source electrode and the drain electrode is the n ⁺ GaAs layer 25 and the recess reaches the nGaAs layer 23. Although the depth is set to the depth, it is to be understood that the compound semiconductor layer provided with both electrodes and the compound semiconductor layer provided with the recess are changed to appropriate layers according to the type of the field effect transistor.

Description of Manufacturing Method FIGS. 2 (A) to 2 (F) are manufacturing process diagrams for explaining an embodiment of the present invention, in which sectional views show the state of the sample in the main process during the manufacturing process. It is a thing. In these drawings, hatching showing a cross section is partially omitted in order to avoid making the drawings complicated.

In this example, first, it is necessary to form a laminated body of compound semiconductor layers in order to manufacture a HEMT. Therefore, an undoped GaAs layer 13 (thickness 100 nm) as a buffer layer, A, is formed on the GaAs substrate 11 by, for example, the MBE (molecular beam epitaxy) method.
lGaAs layer 15 (thickness 100 nm), n ⁺ type as carrier supply layer
AlGaAs layer 17 (dope amount 1.1 × 10 ¹⁸ cm ⁻³ , thickness 15 nm), undoped AlGaAs layer 19 (thickness 4 nm) as a spacer layer,
Undoped GaAs layer 21 (thickness 20 nm) as a channel layer,
Furthermore, the n-type GaAs layer 23 (thickness 50 nm, carrier concentration 5 × 10 ¹⁷
cm ^-3 ) and n ⁺ GaAs layer 25 (thickness 50 nm, carrier concentration 4 × 10
¹⁸ cm ^-3 ) are grown in this order.

Next, the non-alloy ohmic electrode layer 51 is formed on the n ⁺ GaAs layer 25, which is the uppermost layer of the compound semiconductor layer in which the recess is to be formed. This is as described below in this embodiment. went.

As the non-alloy ohmic electrode layer 51, As (arsenic)
^{Was formed on the} order of 10 ¹⁹ cm ⁻³ to form a Ge (germanium) layer 51. Then, the InAs layer 51 is formed on the n ⁺ GaAs layer 25 by MBE.
Method (see FIG. 2 (A)). InAs layer
The formation of 51 is not limited to the MBE method, and other suitable methods such as MOCVD (metalorganic pyrolysis vapor phase growth method) can also be used.

Next, on the non-alloy ohmic electrode layer 51, a resist pattern shown by 53 covering the active region is formed as an element isolation pattern exposing the element isolation area formation planned region of the field effect transistor (see FIG. 2 ( B)
reference).

Next, the element isolation region 35 is formed by O ⁺ ion implantation using the resist pattern 53 as a mask (see FIG. 2C), and the resist pattern 53 is directly used as an etching mask for the non-alloy ohmic electrode layer 51. Used as the resist pattern of the non-alloy ohmic layer 51
The portion exposed from 53 is removed by, for example, Ar ion milling (see FIG. 2 (D)).

Next, a resist pattern 53 which is an element isolation pattern
After removing the remaining portion 51a of the non-alloy ohmic electrode layer
As a gate pattern 55 exposing a region corresponding to the gate electrode formation planned region of, for example, a resist pattern 55 having an overhang-shaped cross section is formed on the n ⁺ GaAs layer 25 including the remaining portion 51a of the non-alloy ohmic electrode layer. . Then, using this resist pattern 55, for example, by Ar ion milling, the remaining portion 51 of the non-alloy ohmic electrode layer is formed.
Recess etching is performed from the a surface to the nGaAs layer 23. When this recess etching is completed, the remaining portion 51a of the non-alloy ohmic electrode layer is divided, the source electrode 41 can be configured by one of the divided portions, and the drain electrode can be formed by the other portion.
43 can be configured (see FIG. 2 (E)). Then, a gate electrode forming material (such as Al) is deposited on the resist pattern 55 and the recess 27 used for the recess etching, and then the resist pattern 55 is removed to remove unnecessary portions of the gate electrode forming material. (Lift off), and the gate electrode 29 is formed in the recess 27 (see FIG. 2 (F)). The deposition of the gate electrode forming material is preferably performed by using a film forming method having a strong directivity.

Through the above procedure, the inverted HEMT shown in FIG. 1 can be obtained.

It should be noted that the invention of this manufacturing method is not limited to the above-described embodiments, and modifications such as those described below can be added.

Although the element isolation is performed by oxygen ion implantation in the embodiment, the element isolation may be performed by etching away the element isolation region and leaving the mesa type active region.

Further, it should be understood that the numerical conditions such as the film thickness described in the embodiments of the manufacturing method are merely examples and may be changed according to the design of the inverted structure HEMT.

Further, the manufacturing method of the present invention is not only applicable to the inverted HEMT, but can be widely applied to the manufacture of field effect transistors having other structures having the recess structure. Therefore, the compound semiconductor layer provided with the source electrode and the drain electrode (n ⁺ GaAs layer 25 in the embodiment) and the compound semiconductor layer for recess etching (the same n ⁺ GaAs layer 25, nGaAs)
It is to be understood that layer 23) is modified to the appropriate layer depending on the type of field effect transistor.

(Effects of the Invention) As is apparent from the above description, according to the method for manufacturing a field effect transistor of the present invention, the pattern for element isolation is used not only for element isolation but also in the non-alloy ohmic electrode. It is also used to remove the exposed portion of the element isolation pattern of the layer. Therefore, the element isolation region and the active layer region can be accurately separated. The gate pattern is also used as a mask for recess etching, a lift-off mask for forming a gate electrode, and a mask for dividing the non-alloy ohmic electrode layer and patterning the source and drain electrodes. Therefore, the source and drain electrodes can be formed by self-alignment with respect to the gate electrode. Further, as described above, one pattern is used as a common mask for many steps, so that the pattern forming step can be simplified.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a field effect transistor manufactured according to the present invention, and FIGS. 2 (A) to (F) are views for explaining an embodiment of the present invention. FIG. 3 is a sectional view schematically showing a conventional field effect transistor, and FIGS. 4A to 4C show a conventional manufacturing method. It is a process drawing to show. 11 ... Semi-insulating GaAs substrate, 13 ... Undoped GaAs layer 15 ... Undoped AlGaAs layer 17 ... n ⁺ AlGaAs layer, 19 ... Undoped AlGaAs layer 21 ... Undoped GaAs layer (channel layer) 21a ... Two-dimensional electron gas, 23 ... nGaAs layer 25 ... n ⁺ GaAs layer, 27 ... recess 27a, 27b ... recess edge 29 ... gate electrode, 35 ... element isolation region 41 ... source electrode (non-alloy ohmic electrode) 43 ... drain electrode (non-alloy ohmic electrode) 51 ... Non-alloy ohmic electrode layer 53 ... Element isolation pattern (resist pattern) 55 ... Gate pattern (resist pattern).

Claims (1)

(57) [Claims] 1. A field effect transistor having a recess structure, wherein a source electrode extends to one of regions on both sides of a recess of a compound semiconductor layer and a drain electrode extends to an edge of the recess. Is provided in
In manufacturing a field effect transistor in which the source and drain electrodes are ohmic electrodes, a step of forming, on the compound semiconductor layer, an ohmic electrode layer made of a semiconductor layer having a high impurity concentration that does not react with the compound semiconductor layer, A step of forming an element isolation pattern on the ohmic electrode layer to expose an element isolation area formation planned region of the field effect transistor; and an element isolation area is formed by ion implantation using the element isolation pattern as a mask And a step of removing the exposed portion of the ohmic electrode layer using the inter-element isolation pattern as a mask, and after forming a gate pattern that exposes a region corresponding to the gate electrode formation planned region of the remaining portion of the ohmic electrode layer. , Recess etching using the gate pattern as a mask and Method of manufacturing a field effect transistor which comprises a step of performing over gate electrode formation.