JPH0298946A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To surely reduce a contact resistance and a parasitic resistance in an easy process by using a molecular beam crystal growth method. CONSTITUTION:A GaAs layer as a buffer layer 11 is grown to be at 6000Angstrom on the surface of a semiconductor substrate 10; an AlGaAs layer as a two-dimensional electron-gas supply layer 2 is formed to be at 350Angstrom in thickness on the surface of the buffer layer 11. In succession, a GaAs layer as a contact layer 3 is grown to be at 2000Angstrom . A gate-electrode formation position of the contact layer 3 is etched. A V-groove is formed; after that, an InAs layer as a non-alloy ohmic contact layer 4 is formed to be at 10Angstrom in thickness on the surface of a surface protective layer 50 by using a molecular beam crystal growth method again; after the non-alloy ohmic contact layer 4 has been grown, elements are isolated by a mesa etching operation; Al is evaporated to be at about 3000@R as an ohmic electrode 7 and a gate electrode 8; they are formed by a lift-off method. Thereby, a contact resistance and a parasitic resistance can be reduced.

Description

[Detailed Description of the Invention] [4 Already Required] It is an object of the present invention to provide a manufacturing method of field effect transistors such as high electron mobility transistors, which can reliably reduce contact resistance and parasitic resistance through easy steps. A step of forming a second semiconductor layer on the surface of the first semiconductor layer on the surface of the semiconductor substrate whose main surface is (100), and a step of forming a third semiconductor layer on the surface of the second semiconductor layer. A step of etching away the surface of the third semiconductor layer to form a surface in which the (111) plane of the crystal is exposed, and using a molecular beam crystal growth method to form a surface on the (100) surface of the third semiconductor layer. Optionally, Ing
a step of forming a fourth semiconductor layer made of Gap-x As (where 0.5≦x≦1) (indium gallium arsenide); a step of forming an ohmic electrode on the surface of the fourth semiconductor layer; 3. Forming a gate electrode on the etched and removed surface of the third semiconductor layer.

[Industrial application field]

The present invention relates to a method for manufacturing a field effect transistor such as a high electron mobility transistor.

This semiconductor device, called a high electron mobility transistor, is a type of field effect transistor, and its main feature is that it has an exceptionally high switching speed. However, when trying to make this device capable of operating at even higher speeds, several problems arose.

[Conventional technology]

Hereinafter, indicators of switching performance will be explained, and then contact resistance and parasitic resistance, which are obstacles to improving switching performance, will be explained with reference to FIG.

FIG. 4 is an explanatory diagram of the contact resistance Rel and the parasitic resistance RC2 in the circuit diagram of the high electron mobility transistor. In the figure, ■ indicates data l-voltage, 1. is the drain current.

There is a value called "transfer conductance J(G,)" that serves as an index of the switching performance of an element.

ΔI0 G - ΔVG This value is the gate i% pressure ■ as described above. change ΔV,
It shows the ratio of change △Io in drain current '/A Io with respect to the transfer conductance G,
, , is the key to improving device performance.

Now, the current flowing between the ohmic electrode and the underlying layer is blocked by the contact resistance PCI. This contact resistance PCI increases as the bandgap of the lower layer in which the ohmink electrode is provided increases. Furthermore, there is a parasitic resistance R between the ohmic electrode and the gate electrode.
C2 occurs and again impedes current flow. This parasitic resistance Rc
The longer the distance between the two electrodes, the larger z becomes.

The sum Rc of the contact resistance RCI and the parasitic resistance Rcz is the fourth
As shown in the figure, it acts in parallel to the ideal current flow path between the source and channel.

Therefore, the transfer conductance explained earlier is actually
Ideal value G of transfer conductance. and a resistor Rc in parallel.

In other words, G.

G! I+RC-G.

becomes.

Therefore, in reality, this value G is somewhat smaller than the ideal value G1° of transfer conductance.

Therefore, in order to exhibit the original switching performance of a field effect transistor such as a high electron mobility transistor, it is necessary to reduce the contact resistance RCI and the parasitic resistance RC1.

Therefore, a method was developed that reduces contact resistance by providing a contact layer below the ohmic electrode and lowering the band gap. This method will be explained below with reference to FIG.

FIG. 5 is a sectional view of a main part of a conventional high electron mobility transistor, and illustrates the contact resistance Rc1 and the parasitic resistance Rcz near the electrode. In FIG. 5, 10 is a semiconductor substrate made of GaAs (gallium arsenide). 1
1 is a buffer layer made of AIGaAs (aluminum gallium arsenide). l is the channel layer, GaA
Consists of s (gallium arsenide).

2 is a two-dimensional electron gas supply layer, which is made of AIGaAs (aluminum gallium arsenide) with Si (silicon) added thereto. 3 is a contact layer, which is made of GaAs (gallium arsenide) doped with Si (silicon). 7 is an ohmink electrode made of AuGe/Au (gold germanium alloy/gold). 8 is game 1”! pole,
It consists of AuGe/Au (gold germanium alloy/gold).

In this method, a buffer layer 11° channel layer 1. After sequentially depositing the two-dimensional electron gas supply layer 2, a GaAs (gallium arsenide) layer doped with impurities to about 2 XIO"cm-' is placed between the two-dimensional electron gas supply layer 2 and the ohmic electrode 7. This is an attempt to reduce the contact resistance at the bottom surface of the electrode by forming the contact layer 3) with a relatively thick thickness (about 0.1 μm).

However, even with the conventional technique shown in FIG. 5, the band gap between the GaAs (gallium arsenide) layer (contact layer 3) and the ohmic electrode 7 is large, and the drawback is that the contact resistance RC1 cannot be reduced to a negligible value. It has become.

Therefore, materials 1 with a much smaller bandgap than GaAs (gallium arsenide), such as n -1nGaAs (
A method (invention of Japanese Patent Application No. 63-57257) has emerged in which a non-alloy ohmic contact layer is formed by growing indium gallium arsenide (indium gallium arsenide) on the surface of the contact layer 3 to reduce the contact resistance Rc+.

[Problem to be solved by the invention]

In this method, Sing (silicon dioxide) or a silicon nitride film is used as a mask by etching away the gate electrode forming position of contact i and then selectively forming a non-alloy ohmic contact layer. As a result, the process of forming the non-alloy ohmic contact a becomes extremely troublesome. In addition, there is a strong possibility that the formed non-alloy ohmic contact layer will come into contact with the gate it electrode, making it impossible to form the non-alloy ohmic contact layer to the very edge of contact a.

Note that, unlike the above-mentioned procedure, after uniformly forming up to the non-alloy ohmic contact layer, the layer up to the GaAs (gallium arsenide) layer (contact layer 3) which is the lower layer of the non-alloy ohmic contact layer is Even with the cutting and removal method, it is impossible to form a non-blowing ohmic contact layer to the very edge of the contact layer.

The reason for this is that until now InAs (indium arsenide) has been used.

Alternatively, because no etching gas suitable for etching InGaAs (indium gallium arsenide) has been found, dry etching cannot be used, and chemical etching must be used exclusively. However, when attempting to remove the GaAs (gallium arsenide) JW (contact layer 3) together with the non-alloy ohmic contact layer using chemical etching, it is difficult to remove the rnAs (indium arsenide) or InGaAs (indium arsenide) that forms the non-alloy ohmic contact layer. indium gallium arsenide)
and GaAs (gallium arsenide) forming the contact layer 3.
This is because there is a difference in etching rate between the two.

In the end, no matter which current method is used, contact layer 3
It is not possible to form a non-alloy ohmic contact layer right up to the very edge. Therefore, the distance between the non-blowing ohmic contact layer and the gate electrode cannot be reduced, and the parasitic resistance RczO problem cannot be solved.

The present invention has been made in view of the problems of the prior art described above, and an object of the present invention is to provide a manufacturing method that can reliably reduce contact resistance and parasitic resistance with easy steps.

[Means to solve the problem]

In order to solve such problems, the present invention includes a step of forming a second semiconductor layer on the surface of the first semiconductor layer on the surface of the semiconductor substrate whose main surface is (100), and a step of forming the second semiconductor layer on the surface of the second semiconductor layer. , a step of forming a third semiconductor layer, a step of etching away the surface of the third semiconductor layer to form a surface in which the (111) plane of the crystal is exposed, and a step of forming the third semiconductor layer using a molecular beam crystal growth method. Inx Ga1 selectively on the (100) surface of the third semiconductor layer
-x As (however, 0.5≦x≦1) (indium gallium arsenide), a step of forming a fourth semiconductor layer;
The method includes the steps of forming an ohmic electrode on the surface of the fourth semiconductor layer, and forming a gate electrode on the etched and removed surface of the third semiconductor layer.

[Effect]

Hereinafter, the operation of the present invention will be explained with reference to FIG. 2.

FIG. 2 is a structural diagram of a high electron mobility transistor according to an embodiment of the present invention. In the figure, 10 is a semiconductor substrate, 11 is a buffer layer, and ■ is a first semiconductor layer (channel layer).
, 2 is the second semiconductor layer (two-dimensional electron gas supply N), 3 is the third semiconductor layer (contact N), 4 is the fourth semiconductor layer (non-alloy ohmic contact N), 7 is the ohmic electrode, 8 is the gate It is an electrode.

The inventor has the general formula 1nz Ga, -1As (0,5≦
Through molecular beam crystal growth experiments of indium gallium arsenide represented by 111) plane can be exposed, and if a molecular beam crystal growth method is used when forming the non-alloy ohmic contact layer 4 on the surface of the contact layer 3, InGaAs (indium gallium arsenide) can be formed on the (100) plane. The growth rate was very high, while the etched-out formation (111
) The present invention was achieved by taking advantage of the phenomenon that growth occurs only to a negligible extent in areas where the surface is exposed.

In the present invention, if all the plane orientations of the crystals on the surface formed by etching are (111) planes (that is, if the surface formed by etching removal is (111) plane), then during growth Best selectivity. For reference, InGaAs grown on a slope formed by etching away the surface of the contact layer 3 is shown.
(indium gallium arsenide) film thickness (10
A graph showing the relative ratio of the thickness of the grown film on the 0) surface for each growth temperature during molecular beam crystal growth is attached as Figure 3.

The horizontal axis of this graph shows the growth temperature (in °C) of the non-alloyed mink contact layer 4 by molecular beam crystal growth, while the vertical axis shows the (1
00) shows the growth film thickness ratio of the plane. If the slope formed by etching and removal becomes a (111) plane as shown in this graph, there will be almost no growth of InAs (indium arsenide) on this slope. General formula 1nx Ga+-x As (0,5≦x
Similarly, selective growth is possible for indium gallium arsenide expressed by ≦1). Furthermore, this slope is (311,)
, (711) may have a gentle slope, but as shown in FIG. 4, the selectivity of crystal growth deteriorates, so the crystal must be grown at a somewhat higher temperature in order to function as an element. It won't happen.

Moreover, the general formula 1nx Ga+-x As (0,5≦x
≦1) When growing indium gallium arsenide on the substrate surface, the growth FIIJJ! shown in FIG. X
According to the ratio, for the (100) plane, InXGa1-
x As grows, but the etched part is (111)
If the etched partial surface consists of only the fine (111,) planes of the crystal, Ga
As (gallium arsenide) grows. In general, (10
0) When In, Ga, and As grow on a surface, the gentler the slope, the more rnGa grows on the slope.
The proportion of In (indium) in As (indium gallium arsenide) tends to decrease. In order to function as a device, indium arsenide grown on the inclined surface must be
It is desirable that xGa, -xAs (0≦x≦0.5).

If the above-mentioned conditions are satisfied, the non-broiohmic contact layer 4 can be selectively grown on surfaces other than the inclined surfaces by the molecular beam crystal growth method. Therefore, in addition to being able to reduce the contact resistance as in the past, the non-blowing ohmic contact layer 4, which could not be brought close to the gate electrode, can now be formed in a self-aligned manner up to the edge of the contact layer, which has been an issue. The problem of parasitic resistance can be solved with a simple manufacturing process.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a process explanatory diagram according to this embodiment.

In Fig. 1, 10 is a semiconductor substrate whose main surface is (100).
11 is a buffer layer made of GaAs (
1 is the first semiconductor layer (channel layer), which is made of GaAs (gallium arsenide), and 2 is the second semiconductor layer (two-dimensional electron gas supply layer), which is AlGaAs (aluminum gallium arsenide). 3 is a third semiconductor layer (contact layer); 4 is a layer made of GaAs (gallium arsenide) doped with Si (silicon); 4 is a fourth semiconductor layer (contact layer); A semiconductor layer (non-alloy ohmic contact layer) is a layer made of rnAs (indium arsenide) doped with Si (silicon), and 7 is an ohmic electrode made of AuGe/Au (gold germanium/gold). 8 is a gate electrode, made of AuGe/
Made of Au (gold germanium/gold).

See Figure 1a].

FIG. 1a) is an explanatory diagram of the process of forming up to the two-dimensional electron gas supply N2 on the surface of the semiconductor substrate 10.

The main surface made of GaAs (gallium arsenide) is (100)
Layers are formed on the surface of the semiconductor substrate 10 using the molecular beam crystal growth method in the order described below.

First, 6,000 GaAs (gallium arsenide) layers are grown as a buffer layer 11 on the surface of the semiconductor substrate 10 .

On the surface of this buffer N11, an AlGaAs (aluminum gallium arsenide) layer is formed as a two-dimensional electron gas supply layer 2 to a thickness of 350 nm. 2X10”cm for this layer
St (silicon) is doped to a concentration of -'.

Subsequently, 2000 GaAs (gallium arsenide) layers are grown as contact N3. This layer has 2×10”
S+ (silicon) is doped to a concentration of C11l-'. Furthermore, in this state, since surface states are generated on the surface of the contact layer 3, I
The surface of the contact layer 3 is covered with nAs (indium arsenide), and the first growth is completed. The surface protective layer 50 formed at this time is made of TnAs (indium arsenide)N with a thickness of 10 layers.
Dope Si (silicon) to a concentration of XIO"cm-'.

Note that since the surface of the semiconductor substrate 10 is a (100) plane, the surface of the buffer N11 formed on the surface is a (10) plane.
0) side. Similarly, the surface of the channel layer 1 formed on the surface of the buffer layer 11 is also a (100) plane, and the two-dimensional electron gas supply N2. The surface of contact layer 3 is (1
00) side.

See Figure 1 b).

FIG. 1b) is a step of etching the contact layer 3 at the location where the gate electrode is to be formed.

For this reason, the gate recess structure portion is processed into an inverted triangular shape (■ groove). At this time, holes with a diameter of 0.2 μm were made in the resist by electron beam exposure, and the substrate surface ((100) plane) was
A groove ((111) plane) is formed by etching with an anisotropic etchant that is highly selective to the substrate. The etching solution used at this time is sulfuric acid: hydrogen peroxide: water =
This is a solution with a ratio of 3:l:1 (volume ratio). The size of the hole formed in the resist is determined by the gate length of the semiconductor element, the thickness of the contact layer, and the etch rate of the etching solution.

See Figure 1 C).

FIG. 1C) is an explanatory diagram of the process of forming the non-alloy ohmic contact N4.

After forming the groove, the molecular beam crystal growth method is again used to form a non-blowing ohmic contact N on the surface of the surface protection layer 50.
4, an InAs (indium arsenide) layer is formed to a thickness of 10 mm, and this layer is also coated with S at a concentration of 2 x 10"cm-'.
Add t (silicon). However, in this case, (1
The growth temperature is set to 450°C to 550'C so that InAs (indium arsenide) grows only on the 00) plane. The growth temperature was selected under the following conditions. growth temperature 5
If you try to perform molecular beam crystal growth at a temperature higher than 50°C, the growth of rnGaAs (indium gallium arsenide) on the (100) substrate surface will decrease, which will impede the functionality of the device. Then, increase the growth temperature to 4
If the temperature is lower than 50°C, the growth toward the (111) plane will be significant, which is unsatisfactory.

See Figure 1 d).

FIG. 1d) is an explanatory diagram of the process of forming an electrode.

After growing the non-alloy ohmic contact layer 4, device isolation is performed by mesa etching, and ohmic electrodes 7,
74 poles 8 are formed by vapor depositing AI (aluminum) by about 3000 people and lift-off.

Through the above steps, the problems of contact resistance and parasitic resistance are easily solved, and the field effect transistor shown in FIG. 2 is completed.

By the way, this embodiment can be modified in various ways according to the gist of the present invention. Although the above-mentioned embodiments have been explained using high electron mobility transistors as an example, the present invention can also be applied to, for example, M E
S F E T (Metal Semiconductor)
ctor Field Effect Transis
It can also be applied to other field effect transistors such as (tor). Furthermore, in this embodiment, InAs (indium arsenide) was used as the material forming the fourth semiconductor layer 4, but if it has the general formula InIGa14As (0,5≦x≦1) (indium gallium arsenide), it can be used as a Schottky material. The barrier is low, there is no need for a heating process for alloying with the metal forming the electrode, and furthermore, no surface states will spontaneously form even if left alone after the formation of the pores. Therefore, the material forming the fourth semiconductor layer (non-alloy ohmic contact layer) 4 may be replaced with these materials. In addition, the slope of the etched portion can be set to any slope (in other words, the etched portion surface is (111
), the proportion of crystals with exposed faces can be set to any desired value), but
As already mentioned in [Operation], indium gallium arsenide growing on the inclined surface is Ing Ga, 4 As (0≦x
≦0.5).

(Effects of the Invention) As explained above, the present invention has the greatest advantage in that it solves the problem of parasitic resistance between ohmic electrodes and gate electrodes in a field effect transistor aiming at high-speed operation through a simple process. effective.

[Brief explanation of drawings]

Of the attached drawings, FIG. 1 is a process explanatory diagram (main part sectional view) of a high electron mobility transistor according to an embodiment of the present invention, and FIG. Structural diagram of mobility transistor (
Figure 3 shows the relative ratio of the thickness of the InGaAs (indium gallium arsenide) film grown on the (100) plane to the thickness of the InGaAs (indium gallium arsenide) film grown on the slope formed by etching. Graphs shown for each growth temperature during molecular beam crystal growth,
FIG. 4 is an explanatory diagram of contact resistance and parasitic resistance, and FIG. 5 is a structural diagram (main part sectional view) of a conventional high electron mobility transistor. In the figure, 10 is a semiconductor substrate, 11 is a buffer layer, 1 is a first semiconductor layer (channel N), 2 is a second semiconductor layer (two-dimensional electron gas supply layer), and 3 is a third semiconductor layer (contact layer) 24 is the fourth semiconductor layer (non-alloy ohmic contact), 50 is the surface protection layer, 7 is the ohmic electrode, and 8 is the gate electrode.

Claims (1)

[Claims] The first surface of the semiconductor substrate (10) whose main surface is (100)
a step of forming a second semiconductor layer (2) on the surface of the semiconductor layer (1); a step of forming a third semiconductor layer (3) on the surface of the second semiconductor layer (2); and a step of forming the third semiconductor layer (3) on the surface of the second semiconductor layer (2). (3) Etch the surface and remove the crystal (1
11) Using a step of forming an exposed surface and a molecular beam crystal growth method, In_xGa_1_-_xAs (however,
a step of forming a fourth semiconductor layer (4) made of (indium gallium arsenide) (0.5≦x≦1); a step of forming an ohmic electrode (7) on the surface of the fourth semiconductor layer (4); A method for manufacturing a field effect transistor, comprising the step of forming a gate electrode (8) on the etched and removed surface of the third semiconductor layer (3).