JPH05166840A - Field effect transistor - Google Patents

Abstract

PURPOSE:To provide a field effect transistor excellent in controllability of threshold voltage by forming a GaP layer, as a recess etching stop layer, between an electron supply layer and a cap layer for reduction of contact resistance. CONSTITUTION:If an electron supply layer 14 is, for example, Al0.3Ga0.7As, the etching can be stopped certainly with a GaP layer 15, in case of recessing a cap layer 16 for reduction of contact resistance, using etchant, by forming undoped Gag as an etching stop layer 15, in the thickness below the thickness of a critical film, for example in the thickness of 20Angstrom on an electron supply layer 14. Since the thickness of this GaP layer 15 is very thin at approximately 20Angstrom , there is almost no problem in the action of an FET Hereby, for the control of the threshold voltage, the error within surface can be suppressed to 3% or less.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recess type field effect transistor.

[0002]

2. Description of the Related Art A two-dimensional electron gas field effect transistor (hereinafter referred to as 2DEGFET) is a field effect transistor utilizing two-dimensional electron gas accumulated at a heterojunction interface and has excellent high speed and low noise. It has been put to practical use as an amplifying element for ultra-low noise and high frequency. Further, research and development of integrated circuits and the like using 2DEGFET have been actively conducted.

FIG. 3 is a schematic structural diagram of a conventional AlGaAs / GaAs 2DEGFET as a typical example of the 2DEGFET. This 2DEGFET comprises an undoped GaAs buffer layer 32, an undoped GaAs electron transit layer 33, an impurity-doped AlGaAs electron supply layer 34, and an impurity-doped GaAs on a semi-insulating GaAs substrate 31.
The contact resistance reducing cap layer 35 is sequentially laminated by an epitaxial growth method. Then, the gate electrode 36 is formed on the surface of the central portion of the electron supply layer 34,
Source and drain electrodes 37, 38 on the cap layer 35
Are provided respectively.

On the other hand, a metal / semiconductor field effect transistor (hereinafter referred to as MESFET) is the most general element of an ultra-high frequency / ultra-high speed device that has been studied for a long time, and is currently being put into practical use. Most of the.

FIG. 4 is a schematic structural diagram of a conventional GaAs MESFET as a typical example of the MESFET.
In this MESFET, an undoped GaAs buffer layer 42, an impurity-doped GaAs operating layer 43, and an impurity-doped GaAs contact resistance reducing cap layer 44 are sequentially laminated on a semi-insulating GaAs substrate 41 by an epitaxial growth method. Then, the gate electrode 45 is formed on the surface of the central portion of the operating layer 43, and the cap layer 44 is formed.
Source and drain electrodes 46 and 47 are provided on the top, respectively.

Here, as shown in FIGS. 3 and 4, in 2DEGFET and MESFET, a recess structure is used as a method of defining the threshold voltage. The formation of the recess structure shown in FIGS. 3 and 4 is performed by removing the impurity-doped GaAs contact resistance reducing cap layers 34 and 44 in the gate electrode forming portion by etching using a photoresist pattern or the like as a mask, and recessing the gate electrode. It is formed inside.

[0007]

By the way, in the recess structure in the FET shown in FIGS. 3 and 4, in order to remove the cap layer for reducing the GaAs contact resistance, an etching solution such as H ₂ SO ₄ —H ₂ O is used. _Two systems are used. However, the etching rate changes depending on the conditions such as the concentration of the etching solution, the temperature, and the stirring conditions.
In the GFET, since the etching ratio of GaAs and AlGaAs cannot be selected, the electron supply layer of Al is used.
Even GaAs is etched, and MESF
Even in ET, the operation layer is etched, the control of the threshold voltage cannot be made uniform, and there is a problem that an error of about 8% appears in the plane.

An object of the present invention is to solve such a problem and to provide a field effect transistor having good controllability of threshold voltage.

[0009]

The present invention comprises a semiconductor substrate, a buffer layer formed on the semiconductor substrate, an electron transit layer made of an intrinsic semiconductor adjacent to the buffer layer, and the electron transit layer. And an electron supply layer formed on the electron transit layer made of a semiconductor doped with impurities having an electron affinity smaller than that of the intrinsic semiconductor, and a contact resistance reducing cap laminated on the electron transit layer. And forming a Schottky junction gate electrode on the electron supply layer, the portion directly below the gate electrode of the contact resistance reducing cap layer laminated on the electron supply layer is removed by etching. In a two-dimensional electron gas field effect transistor having a recess structure obtained by the method described above, the GaP layer is used as a recess etching stop layer, Characterized in that formed between the the layer contact resistance reducing cap layer.

According to the present invention, a semiconductor substrate, a buffer layer formed on the semiconductor substrate, an operation layer adjacent to the buffer layer, and a contact resistance reducing cap layer laminated on the operation layer are provided. And a recess structure obtained by etching away a portion of the contact resistance reducing cap layer immediately below the gate electrode laminated on the operation layer when forming a Schottky junction gate electrode on the operation layer. In the metal-semiconductor field effect transistor having, a GaP layer is formed as a recess etching stop layer between the operating layer and the contact resistance reducing cap layer.

[0011]

In the present invention, for example, as the recess etching stop layer, GaP which is hardly etched except aqua regia, hot phosphoric acid, and Br-methanol is used to etch the adjacent electron supply layer or operation layer. Without doing so, the in-plane error of the threshold voltage can be suppressed within 3%, and uniform control can be realized. GaP used as this etching stop layer is GaAs or Al.
Although it has a difference of about 4% in lattice constant from GaAs, GaP
When the layers have a thickness equal to or less than the critical film thickness, stacking is realized without causing dislocation. The critical film thickness of GaP on this GaAs layer or AlGaAs layer is as follows. See year; JW Matt
hews and A. E. Blakeslee. , J
individual of Crystal Growth,
vol. 27, 1974, p. By the method of 118), it can be obtained from the relationship of the stress at the interface.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 Here, as an example, AlGa
An example of an As / GaAs 2DEGFET will be described. However, the material is not limited to this material, and Ga having a thickness equal to or less than the critical thickness as an etching stop layer on the electron supply layer is described.
By forming the P layer, the impurity-doped GaA is reliably formed.
The s contact resistance reducing cap layer can be selectively etched.

FIG. 1 shows a cross section of an element according to an embodiment of the present invention.
In this 2DEGFET, the following layers are formed on a semi-insulating GaAs substrate 11 by epitaxial growth. 12: undoped GaAs buffer layer 13: undoped GaAs electron transit layer 14: impurity-doped Al _0.3 Ga _0.7 As electron supply layer 15: undoped Gap etching stop layer (thickness of about 20 Å) 16: impurity-doped GaAs contact resistance reducing cap layer Here, the impurity-doped GaAs contact resistance reducing cap layer 16 is a layer for making good ohmic contact.

Next, source and drain electrodes 17 and 18 made of a metal for ohmic contact are formed on the surface of the growth substrate.
Is formed by a lift-off method or the like, and an undoped Ga is formed in which a two-dimensional electron gas is formed by an alloy method for applying heating or the like
It is in contact with the As electron transit layer 13. Next, impurity-doped GaAs between the source and drain electrodes 17 and 18
The contact resistance reducing cap layer 16 is partially removed by etching, and a gate electrode 19 made of a metal for Schottky junction is formed in that portion.

As shown in FIG. 1, for example, the electron supply layer 14
Is Al _0.3 Ga _0.7 As, the undoped GaP is used as the etching stop layer 15 in a thickness not more than the critical film thickness, for example, in a thickness of 20 angstrom.
When the contact resistance reducing cap layer 16 is recessed by using an etching solution, the G
Etching can be reliably stopped by the aP layer. Since the GaP layer has a very small thickness of about 20 Å, there is almost no problem in FET operation.

In the above embodiments, the Al composition ratio of AlGaAs is set to 0.3, but it goes without saying that it is not limited to this. Further, the thickness of the GaP layer is set to 20 angstroms here, but if the thickness is 56 angstroms or less, which is the critical film thickness, there is no problem in crystal growth.

(Embodiment 2) Here, GaAs is used as an example.
Although an example of a system MESFET will be described, the material is not limited to this material, and by forming a GaP layer having a thickness equal to or less than the critical film thickness as an etching stop layer on the electron supply layer, the impurity-doped GaAs is surely formed. The contact resistance reducing cap layer can be selectively etched.

FIG. 2 shows a cross section of an element according to an embodiment of the present invention.
In this MESFET, the following layers are formed by epitaxial growth on a semi-insulating GaAs substrate 21. 22: undoped GaAs buffer layer 23: impurity-doped GaAs operating layer 24: undoped GaP etching stop layer (thickness: about 20 Å) 25: impurity-doped GaAs contact resistance reducing cap layer Here, the impurity-doped GaAs contact layer 25 is ohmic. -A layer for making good contact.

Next, the source and drain electrodes 26 and 27 made of ohmic contact metal are formed on the surface of the growth substrate.
Are formed by a lift-off method or the like, and then the impurity-doped GaAs contact resistance reducing cap layer 25 between the source and drain electrodes 26 and 27 is partially removed by etching, and a gate electrode 28 made of a metal for Schottky junction is formed on the portion. Is formed.

As shown in FIG. 2, for example, when the operating layer 23 is impurity-doped GaAs, the etching stop layer 2 is formed.
4, undoped GaP having a thickness equal to or less than the critical film thickness,
For example, when the contact resistance reducing cap layer 25 is recessed by using an etching solution by forming it on the electron supply layer 23 with a thickness of 20 angstroms, GaP is used.
The layer can stop the etching reliably. This Ga
Since the thickness of the P layer is as thin as about 20 angstrom, there is almost no problem in FET operation.

In the above embodiment, the thickness of the GaP layer is set to 20 angstrom here, but it is 5 which is the critical film thickness.
If it is 6 Å or less, there is no problem in crystal growth.

[0023]

As described above, according to the present invention,
Selective etching, which has been a problem in conventional wet etching when forming a recess structure, is reliably performed by forming a GaP layer having a critical film thickness or less as an etching stop layer, and the threshold voltage is controlled within a plane error. It can be suppressed to 3% or less.

[Brief description of drawings]

FIG. 1 is a sectional view of an element structure showing an embodiment of a 2DEGFET of the present invention.

FIG. 2 is a cross-sectional view of a device structure showing an embodiment of MESFET of the present invention.

FIG. 3 is a sectional view of a device structure of a conventional 2DEGFET.

FIG. 4 is a sectional view of a device structure of a conventional MESFET.

[Explanation of symbols]

11, 21 GaAs substrate 12, 22 undoped GaAs buffer layer 13 undoped GaAs electron transit layer 14 impurity-doped Al _0.3 Ga _0.7 As electron supply layer 15, 24 undoped GaP etching stop layer 16, 25 impurity-doped GaAs contact resistance reduction cap layer 17 , 26 Source electrode 18, 27 Drain electrode 19, 28 Gate electrode 23 Impurity-doped GaAs operating layer

Claims (2)

[Claims] 1. A semiconductor substrate, a buffer layer formed on the semiconductor substrate, an electron transit layer made of an intrinsic semiconductor adjacent to the buffer layer, and an electron affinity of the intrinsic semiconductor constituting the electron transit layer. An electron supply layer laminated on the electron transit layer made of a semiconductor having a small electron affinity and doped with impurities, and a contact resistance reducing cap layer laminated on the electron transit layer.
When forming a Schottky junction gate electrode on the electron supply layer, a recess structure obtained by etching away a portion directly below the gate electrode of the contact resistance reduction cap layer laminated on the electron supply layer is formed. Have 2
A three-dimensional electron gas field effect transistor, wherein the GaP layer is formed as a recess etching stop layer between the electron supply layer and the contact resistance reducing cap layer. 2. A semiconductor substrate, a buffer layer formed on the semiconductor substrate, an operation layer adjacent to the buffer layer, and a contact resistance reducing cap layer laminated on the operation layer, When forming a Schottky junction gate electrode on the operation layer, a metal having a recess structure obtained by etching away a portion directly below the gate electrode of the contact resistance reducing cap layer laminated on the operation layer. A semiconductor field effect transistor, characterized in that a GaP layer is formed as a recess etching stop layer between the operation layer and the contact resistance reducing cap layer.