JP2985456B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recess type field effect transistor.

[0002]

2. Description of the Related Art A two-dimensional electron gas field effect transistor (hereinafter referred to as a 2DEGFET) is a field effect transistor using a two-dimensional electron gas accumulated at a heterojunction interface, and has excellent high-speed performance and low noise. It has been put to practical use as an ultra-low noise high frequency amplifying element. Also, research and development of integrated circuits and the like using 2DEGFETs have been actively conducted.

FIG. 3 is a schematic structural view of a conventional AlGaAs / GaAs 2DEGFET as a typical example of a 2DEGFET. The 2DEGFET includes an undoped GaAs buffer layer 32, an undoped GaAs electron transit layer 33, an impurity-doped AlGaAs electron supply layer 34, and an impurity-doped GaAs on a semi-insulating GaAs substrate 31.
The contact resistance reducing cap layers 35 are sequentially stacked by an epitaxial growth method. Then, a gate electrode 36 is formed on the central surface of the electron supply layer 34,
Source and drain electrodes 37 and 38 are formed on the cap layer 35.
Are provided respectively.

On the other hand, metal / semiconductor field effect transistors (hereinafter referred to as MESFETs) are the most common elements of ultra-high frequency / ultra-high speed devices which have been studied for a long time, and FETs which are currently being put to practical use Most of them are closed.

FIG. 4 is a schematic structural view of a conventional GaAs-based MESFET as a typical example of the MESFET.
In this MESFET, an undoped GaAs buffer layer 42, an impurity-doped GaAs operation layer 43, and an impurity-doped GaAs contact resistance reducing cap layer 44 are sequentially stacked on a semi-insulating GaAs substrate 41 by an epitaxial growth method. Then, a gate electrode 45 is formed on the central surface of the operation layer 43, and the cap layer 44 is formed.
Source and drain electrodes 46 and 47 are provided thereon.

Here, as shown in FIGS. 3 and 4, in 2DEGFETs and MESFETs, a recess structure is used as a method of defining a threshold voltage. The recess structure shown in FIG. 3 and FIG. 4 is formed by removing the impurity-doped GaAs contact resistance reducing cap layers 34 and 44 in the gate electrode formation portion by etching using a photoresist pattern or the like as a mask, and recessing the gate electrode. Formed within.

[0007]

[SUMMARY OF THE INVENTION Incidentally, the recess structure of the FET shown in FIGS. 3 and 4 in order to remove the GaAs contact resistance reducing cap layer, for example, as an etchant, H ₂ SO ₄ -H ₂ O _Two systems are used. However, the etching rate changes depending on the conditions such as the concentration of the etching solution, the temperature, and the stirring conditions.
In the GFET, since the selectivity of the etching rate between GaAs and AlGaAs cannot be obtained, the electron supply layer Al
Etching to GaAs etc., and MESF
Even in the ET, there is a problem that the operation layer is etched, the threshold voltage cannot be controlled uniformly, and an error of about 8% appears in the plane.

An object of the present invention is to solve such a problem and to provide a field-effect transistor with good controllability of the threshold voltage.

[0009]

According to the present invention, there is provided a semiconductor substrate, a buffer layer formed on the semiconductor substrate, an electron transit layer made of an intrinsic semiconductor adjacent to the buffer layer, and the electron transit layer. Al _x laminated on the electron transit layer made of a semiconductor doped with impurities having an electron affinity smaller than that of an intrinsic semiconductor having
An electron supply layer composed of a Ga _1-x As layer and a contact resistance reducing cap layer composed of a GaAs layer laminated on the electron transit layer. A Schottky junction gate electrode is formed on the electron supply layer. In the formation of a two-dimensional electron gas field effect transistor having a recess structure obtained by removing a portion immediately below a gate electrode of a contact resistance reducing cap layer laminated on the electron supply layer by wet etching, Is formed between the electron supply layer and the contact resistance reducing cap layer as a recess etching stop layer.

[0010] The present invention includes a semiconductor substrate, a semiconductor substrate on which is formed on the buffer layer, and the active layer of GaAs layer adjacent to the buffer layer, a GaAs layer laminated on the active layer on the A contact resistance reducing cap layer, and forming a Schottky junction gate electrode on the operation layer, wet the portion immediately below the gate electrode of the contact resistance reduction cap layer laminated on the operation layer. In a metal / semiconductor field effect transistor having a recess structure obtained by etching and removing, a GaP layer is formed as a recess etching stop layer between the operating layer and the contact resistance reducing cap layer.

[0011]

According to the present invention, for example, GaP which is hardly etched except for aqua regia, hot phosphoric acid and Br-methanol is used as a recess etching stop layer, so that an adjacent electron supply layer or operation layer is etched. Thus, uniform control can be realized in which the in-plane error of the threshold voltage can be suppressed within 3%. GaP used as the etching stop layer is GaAs or Al.
It has a lattice constant difference of about 4% or less from GaAs, but GaP
When the thickness of the layer is equal to or less than the critical thickness, lamination can be realized without dislocation. The critical film thickness of GaP on the GaAs layer or the AlGaAs layer is determined by J.W.Mashews and A.E. Year; JW Matt
heads and A. E. FIG. Blakeslee. , J
own of Crystal Growth,
vol. 27, 1974, p. 118) can be obtained from the relationship of the interface stress.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) Here, as an example, AlGa
An example of an As / GaAs-based 2DEGFET will be described. However, the present invention is not limited to this material, and a Ga film having a thickness equal to or less than a critical thickness is formed as an etching stop layer on an electron supply layer.
By forming the P layer, the impurity-doped GaAs is surely formed.
The selective etching of the s-contact resistance reducing cap layer can be performed.

FIG. 1 shows a cross section of an element according to an embodiment of the present invention.
In the 2DEGFET, the following layers are formed on a semi-insulating GaAs substrate 11 by epitaxial growth. 12: undoped GaAs buffer layer 13: undoped GaAs electron transit layer 14: impurity-doped Al _0.3 Ga _0.7 As electron supply layer 15: undoped Gap etching stop layer (about 20 Å thick) 16: impurity-doped GaAs cap layer for reducing contact resistance Here, the impurity doped GaAs contact resistance reducing cap layer 16 is a layer for making good ohmic contact.

Next, source and drain electrodes 17, 18 made of a metal for ohmic contact are formed on the surface of the growth substrate.
Is formed by a lift-off method or the like, and an undoped Ga in which a two-dimensional electron gas is formed by an alloy method of heating or the like.
It is in contact with the As electron transit layer 13. Next, impurity-doped GaAs between the source and drain electrodes 17 and 18
The contact resistance reducing cap layer 16 is partially removed by etching, and a gate electrode 19 made of a Schottky junction metal is formed in that portion.

As shown in FIG. 1, for example, the electron supply layer 14
Is Al _0.3 Ga _0.7 As, the undoped GaP is used as the etching stopper layer 15 in a thickness less than the critical thickness, for example, 20 angstrom.
4 is formed on the contact resistance reducing cap layer 16 using an etchant.
Etching can be reliably stopped at the aP layer. Since the thickness of the GaP layer is as thin as about 20 angstroms, there is almost no problem in the operation of the FET.

In the above embodiment, the Al composition ratio of AlGaAs is set to 0.3, but it is needless to say that the present invention is not limited to this. Although the thickness of the GaP layer is set to 20 angstroms here, there is no problem in crystal growth if the thickness is equal to or less than the critical thickness of 56 angstroms.

(Embodiment 2) Here, GaAs is used as an example.
An example of a system-based MESFET will be described. However, the present invention is not limited to this material. By forming a GaP layer having a thickness equal to or less than a critical thickness as an etching stop layer on an electron supply layer, it is ensured that impurity-doped GaAs is formed. The selective etching of the contact resistance reducing cap layer can be performed.

FIG. 2 shows a cross section of an element according to an embodiment of the present invention.
In this MESFET, the following layers are formed on a semi-insulating GaAs substrate 21 by epitaxial growth. 22: undoped GaAs buffer layer 23: impurity-doped GaAs operation layer 24: undoped GaP etching stop layer (about 20 Å in thickness) 25: impurity-doped GaAs cap layer for reducing contact resistance Here, the impurity-doped GaAs contact layer 25 is an ohmic -It is a layer for making good contact.

Next, source and drain electrodes 26 and 27 made of metal for ohmic contact are formed on the surface of the growth substrate.
Is formed by a lift-off method or the like, and then the impurity-doped GaAs contact resistance reducing cap layer 25 between the source and drain electrodes 26 and 27 is partially removed by etching, and the gate electrode 28 made of a metal for Schottky junction is Is formed.

As shown in FIG. 2, for example, if the operation layer 23 is made of impurity-doped GaAs,
4, the thickness of the undoped GaP is equal to or less than the critical thickness,
For example, when the contact resistance reducing cap layer 25 is recessed by using an etchant by forming it on the electron supply layer 23 to a thickness of 20 Å,
Etching can be reliably stopped at the layer. This Ga
Since the thickness of the P layer is as thin as about 20 angstroms, there is almost no problem in FET operation.

In the above embodiment, the thickness of the GaP layer is set to 20 angstroms here, but the critical thickness is 5 Å.
If it is 6 Å or less, there is no problem in crystal growth.

[0023]

As described above, according to the present invention,
Conventionally, selective etching, which has been a problem in wet etching when forming a recess structure, is surely performed by forming a GaP layer having a thickness less than or equal to a critical thickness as an etching stop layer. It can be suppressed to 3% or less.

[Brief description of the drawings]

FIG. 1 is a sectional view of an element structure showing an embodiment of a 2DEGFET of the present invention.

FIG. 2 is a sectional view of an element structure showing an example of a MESFET of the present invention.

FIG. 3 is a cross-sectional view of a device structure of a conventional 2DEGFET.

FIG. 4 is a sectional view of an element structure of a conventional MESFET.

[Explanation of symbols]

11 and 21 GaAs substrate 12, 22 an undoped GaAs buffer layer 13 of undoped GaAs electron transit layer 14 doped Al _0.3 Ga _0.7 As electron supply layer 15, 24 an undoped GaP etch stop layer 16, 25 doped GaAs contact resistance reducing cap layer 17 , 26 Source electrode 18, 27 Drain electrode 19, 28 Gate electrode 23 Impurity-doped GaAs operation layer

Claims (2)

(57) [Claims] 1. A semiconductor substrate, a buffer layer formed on the semiconductor substrate, an electron transit layer made of an intrinsic semiconductor adjacent to the buffer layer, and an electron affinity of an intrinsic semiconductor constituting the electron transit layer. An electron supply layer composed of an Al _x Ga _1-x As layer laminated on the electron transit layer composed of a semiconductor doped with impurities having a small electron affinity, and a GaAs layer laminated on the electron transit layer. And forming a Schottky junction gate electrode on the electron supply layer when the contact resistance reduction cap layer is stacked on the electron supply layer. In a two-dimensional electron gas field effect transistor having a recess structure obtained by removing a portion immediately below a gate electrode by wet etching, GaP
A field effect transistor, wherein a layer is formed between the electron supply layer and the contact resistance reducing cap layer as a recess etching stop layer. 2. A semiconductor substrate, a buffer layer formed on the semiconductor substrate, and GaAs adjacent to the buffer layer.
Layer composed of layers and GaAs laminated on this layer
a contact resistance reducing cap layer made of an s layer, and when a Schottky junction gate electrode is formed on the operation layer, the contact resistance reduction cap layer is formed immediately below the gate electrode stacked on the operation layer. In a metal / semiconductor field-effect transistor having a recess structure obtained by wet- etching a portion of
A field effect transistor, wherein a P layer is formed between the operating layer and the contact resistance reducing cap layer as a recess etching stop layer.