JPH01175264A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a field-effect transitor whose gate length is very fine by a method wherein a gate part is irradiated with an electron beam, a resist material to be used as a mask during formation of a gate is deposited, a carrier concentration value of delta doped layer just under the part irradiated with the electron beam is lowered and a channel region is formed. CONSTITUTION:An insulating AlGaAs layer 2 is formed on a GaAs substrate 1; after that, a GaAs layer 3a as a semiconductor layer causing discontinuity is formed without being doped with an impurity; a delta doped Si layer 4 doped with an impurity ot high concentration on the way is formed; in additon, an insulating GaAs layer 3b is formed on it. Then, ohmic metal layers 7a, 7b are formed selectively; after that, they are alloyed; a source region 5 and a drain region 6 are formed in the insulating GaAs layer 3a, 3b. Then, Al to be used as a gate metal is evaporated on the front; an Al layer 8 is formed; after that, a part used to form a gate is irradiated with an electron beam 9 in an atmosphere containing, e.g., alkyl naphthalene as a raw material gas; a resist material 10 is deposited. The, the Al layer 8 is etched by making use of the resist material 10 as a mask; a gate 11 is formed; a field-effect transistor 13 whose gate length Lg is very fine is manufactured.

Description

[Detailed description of the invention] 5 industrial application fields] The present invention relates to a method for manufacturing a field effect transistor.

[Summary of the invention]

The present invention is a method for manufacturing a semiconductor device, in which a resist material is used as a mask when a gate is formed by irradiating an electron beam onto a gate portion to be formed in an atmosphere containing a source gas, and a resist material is used to form a gate. A field effect transistor having a fine gate length can be obtained by forming a channel region by lowering the carrier concentration of the δ dove layer directly under the irradiated part.

[Conventional technology]

Conventional self-alignment field effect transistors are fabricated for the purpose of narrowing the distance between the source and drain and lowering the source-gate resistance. Specifically, after forming a gate, using this gate as a mask,
Type impurity ions are implanted to form n- source and drain regions in the semiconductor layer on both sides of the gate.

[Problem that the invention seeks to solve]

According to the conventional manufacturing method described above, the gate′ and source regions,
In order to prevent short circuits between the drain regions, it is necessary to form sidewalls, which makes the process complicated and reduces the yield. In order to prevent short circuits, it is sufficient to form a δ-doped channel region, but since the ion implantation process and annealing process are essential in the manufacturing process, there is a risk that the steep impurity distribution of the δ-doped region that has been formed may be disrupted. There is. In addition, the gate length Lg of conventional semiconductor devices is 1 to 174 μm, but since the sidewall width is several hundred times 2 (because it is on both sides of the gate), it is impossible to achieve a gate length of about 1000 Å or less. It gets closer. In order to reduce the gate length Lg to 1000 Å or less, electron beam writing is required, but since high-resolution resist has poor resistance to reactive ion etching (RIE), extremely fine gates are formed by lift-off. There is.

However, according to this method, it is impossible to form by self-alignment.

The present invention provides a method for manufacturing a semiconductor device that can solve the above problems.

[Means for solving problems]

In the method for manufacturing a semiconductor device (13) according to the present invention, δ
An insulating semiconductor layer (3, a) is placed above and below the doped layer (4).
).

(3b) and this insulating semiconductor layer (3b).
) to deposit a resist material (lO) by irradiating the gate part to be formed with an electron beam (8) in an atmosphere containing source gas; Step (9) of reducing the carrier concentration of the δ-doped layer (4) directly under the resist material (10) to form a channel region (12);
10) is used as a mask to selectively remove the gate metal layer (8) to form a gate [11].

A method of depositing a resist material (10) on a substrate by irradiating an electron beam (9) in an atmosphere containing a raw material gas has already been proposed (for example, Japanese Patent Application No. 1982).
-299405).

[Effect]

As shown in the means for solving the above problems, the electron beam (9) is irradiated onto the gate portion to be formed in an atmosphere containing source gas to deposit the resist m<to; 9) reduces the carrier concentration of the δ-doped layer (4) directly under the resist material (10) to form the channel region (12), so the resist material (11) which becomes a mask for forming the resist material (11) 10) and the channel region (12) can be formed simultaneously. Moreover, since this channel region (12) is formed by self-alignment, the effective distance between the source region (5A) and the drain region (6A), that is, the gate length Lg, is set to 100.
It also becomes possible to form the film with a thickness of 0 Å or less.

〔Example〕

The present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, an insulating AIG, aAs layer (2) is formed on a G, aAs substrate (1), and then a carrier (electron in this example) band (in this example, a conductive layer) is formed on the insulating AIG, aAs layer (2). band)
G, aAs layer (3a), which is a semiconductor layer that causes discontinuity in
A δ-doped S1 layer (ns=10"cm-2
) (4) is formed, and an insulating G, aAs layer (3b>) is further formed thereon.

Next, as shown in FIG. 1B, ohmic metal layers (e) are applied to the areas where the source region (5) and drain region (6) are to be formed at intervals of about 1 to 0.5 μm using IJ lithography.
7, a>, (7b) After selectively forming, the insulating G, a As layer (
A source region (5) and a drain region (6) are formed in 3a) and (3b).

Next, as shown in Figure 1C, A
After evaporating β and forming the A1 layer (8), for example, in an atmosphere containing alkylnaphthalene as a raw material gas, only the gate portion to be formed is irradiated with an electron beam (9) to deposit a resist material (10). , by this electron beam (9), the δ-doped S1 located directly under the resist material (10) is
By damaging the layer (4) and lowering the carrier concentration (the concentration decreases by about one order of magnitude, n, becomes about 1o1
2cm-2), δ-doped S directly under the gate (11)
1. The layer (4) can be made into a channel region (12) that can be sufficiently pinched off with a gate bias.

Next, as shown in the first diagram, by etching the /1 layer (8) using this resist material (10) as a mask, a gate H1l) is formed, and a field effect transistor ( 13).

According to the field effect transistor (13) according to the fifth embodiment, n of the original δ-doped Si layer (4), which is not damaged by the electron beam (9) irradiation, is approximately IQ 13 cm.
-2, and the concentration of bonds is distributed at a depth of about several dozen people, so n ==1013Cm-"150 people!1
0"150xto-'Cm-3-=2X1019cm
-', and is almost the same as metal. Therefore, the effective channel region (12) between the source region (5A) and drain region (6A) has a gate length Lg. As described above, since the channel region (12) can be formed by self-alignment, Lg can be formed to 1000 Å or less, and the short channel effect can also be suppressed.

That is, according to the above manufacturing method, a mask for forming a channel region (12), an effective source region (5A), a drain region (6A), and a gate (11) that can be sufficiently pinched off by irradiation with an electron beam (9) is formed. Resist material (
10) can be formed simultaneously by self-alignment. The steps necessary to fabricate this field effect transistor include forming the required epitaxial layer (2
), (3,a), (4), (3b), and after forming the source region (5) and drain region (6), an electron beam (9) irradiation step and the A1 layer (8) are performed. Since only two etching steps are required, and formation can be performed by self-alignment, the manufacturing method can be significantly simplified.

〔Effect of the invention〕

According to the present invention, the channel region directly under the gate and the resist material serving as a mask for forming the gate can be formed by self-alignment. Since the distance between the effective source region and the effective drain region becomes the gate length, a semiconductor device having a minute gate length of 1000 Å or less can be obtained. Moreover, according to this manufacturing method, since the depth from the surface to the channel region is shallow, the influence of multiple scattering during electron beam irradiation is reduced, and the controllability of the gate length is improved. Moreover, since the main steps can be performed with self-alignment, manufacturing becomes extremely simple.

[Brief explanation of the drawing]

FIG. 1 is a process diagram of an example. (1) is a G, aAs substrate, (3a), (3b) are insulating GaAs layers, (4) is a δ-doped Si layer, (5)
is the source region, (6) is the drain region, (8) is the i-layer,
(9) is an electron beam, (10) is a resist material, (11)
(12) is a channel region, and (13) is a field effect transistor. Agent Paige Ito
Hide Matsukuma Award example process diagram Figure 1 Procedural amendment damage July 5, 1988 Director General of the Patent Office Yoshi 1) Takeshi Moon 1, Indication of the case 1988 Patent Application No. 332383 2, Invention Name of Semiconductor Device Manufacturing Method 3, Relationship with the Amendment Person Case Patent Applicant Address No. 6-7-35, Kitashinyo, Tokyo Parts Ward Name (2)
18) Sony Corporation Representative Director Norio Ohga 4, Agent name (338B) Patent attorney Sada Ito, ♀h5
, the date of the amendment order Showa year, month, day C (the number of inventions will increase due to Misaki Soro and Sadamasa + 11 In the specification, it will be 101-12 at the end of gAG page), followed by ``Also, this concentration itself is also (2) Ibid., page 7, lines 11-12 [In volume concentration,
``Due to the fact that there are...'' is corrected to ``The volumetric concentration is distributed over an area of about several dozen people.''that's all

Claims (1)

[Claims] A step of forming an insulating semiconductor layer above and below a δ-doped layer, a step of forming a gate metal layer on the surface of the insulating semiconductor layer, and forming the gate metal layer in an atmosphere containing a source gas. forming a channel region by depositing a resist material by irradiating the resist material with an electron beam on the desired gate portion, and reducing the carrier concentration of a δ-doped layer directly under the resist material with the electron beam; and masking the resist material. A method for manufacturing a semiconductor device, comprising the step of selectively removing the gate metal layer to form a gate.