JP2796303B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a compound semiconductor MESFET, and particularly to a high performance MESF
The present invention relates to a method for manufacturing an integrated circuit in which ET is integrated.

[Conventional technology]

Conventional GaAs FETs use high heat-resistant gates (for example, tungsten silicide) to reduce the series resistance between the gate and source to improve performance.
A self-aligned structure by n ⁺ , high temperature annealing was used. For the formation of the n ⁺ layer, a selective growth method can be used, which is described in the literature. (For example, the Japanese Journal of Applied Physics 23,5
(1984) L342 to L345 pages (Japanese Journal of
Applied Physics Vol23, No.5 (1984) p.L342-L345))
When selective growth is used, a high impurity concentration can be easily obtained, a low-resistance layer can be obtained, and deterioration of the gate shot junction is small because high-temperature annealing is not required, as compared with a case where ion implantation is used. Since the n ⁺ layer is located above the gate, the short channel effect is small.

Although this method is effective for manufacturing a single FET, there is a major problem when it is applied to an integrated circuit. This is because the selective growth has a pattern dependence, and the thickness of the GaAs growth layer is thick in an isolated pattern and thin in a dense pattern, so that a uniform growth layer cannot be obtained.
It is difficult to apply to

[Problems to be solved by the invention]

As described above, in the prior art, no consideration is given to the pattern density dependence, and it cannot be applied to LSI manufacturing as it is.

Figure 3 shows n ⁺ to avoid pattern dependence of growth rate.
This is a conventional example in which a layer is applied on the entire surface. This way,
As shown in the figure, a large step remains after removing an unnecessary n ⁺ layer, which is inappropriate for application to a highly integrated IC.

SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method in which a uniform growth layer is obtained irrespective of the density of a pattern and the wiring process is not hindered by impairing flatness.

[Means for solving the problem]

The technique of selectively growing only on the GaAs surface other than on SiO ₂ or WSi is usually performed by metal organic chemical vapor deposition (MOCVD). However, at this time, since the material is uniformly transported to the wafer surface, the material is excessively supplied on the wafer surface in a portion having a small number of selective growth portions, and as a result, a large amount of material is supplied to a growth portion in the vicinity thereof to grow thickly. It will be.

In order to eliminate such pattern dependency, a process of growing crystals in portions other than the required pattern so as not to generate extra material in rough portions of the pattern, and then removing a crystal in unnecessary portions is used. I just need. However, for application to LSI, the flatness must not be impaired at this time.

Therefore, as shown in FIG. 1, after forming the WSi gate 2, a thin polycrystalline GaAs film 4 is deposited on the SiO ₂ 3 by a three-temperature evaporation method or a molecular beam epitaxy method. After this, the insulating film SiO ₂
The GaAs layer above 3 is etched away.

In short, the above-described object is achieved by forming a polycrystalline silicon film on a part of the surface of an insulating film formed on a part of the surface of a single crystal III-V compound semiconductor substrate.
After forming a first film made of a III-V compound semiconductor, a III film is formed on the surface of the first film and the surface of the compound semiconductor substrate.
Forming a group V compound semiconductor film by a growth method,
This can be achieved by removing the compound semiconductor film grown on the surface of the first film and the first film.

[Action]

Conventionally, as shown in FIG. 3, in order to avoid the pattern dependence of the growth rate, an n ⁺ layer is deposited on the entire surface and an unnecessary n ⁺ layer is removed. It was unsuitable for application.

Therefore, as shown in FIG. 2 (c), an n ⁺ GaAs layer 5 is simultaneously grown on the insulating film 3 via the polycrystalline GaAs film 4 and then removed by etching. As shown in FIG. 2E, a flat wafer can be obtained over the entire surface of the LSI.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

Cross section of GaAs MESFET, the main part of GaAs LSI
It is shown in FIG. FIG. 2B is a plan view of the same part.

FIG. 2 is a view for explaining a manufacturing process of the MFSFET. First, as shown in FIG. 1A, after forming an FET active layer 6 on a semi-insulating GaAs substrate 1, a heat-resistant gate electrode 2 is formed. The gate electrode is made of WSi, is deposited by a sputter method, and is then lowered by dry etching using a photolithography method. On top of this, a 3000 mm thick SiO ₂ film 3
A polycrystalline GaAs layer is formed thereon by a CVD method, and a polycrystalline GaAs layer having a thickness of 500 mm is formed by a three-temperature evaporation method or a molecular beam epitaxy method (FIG. 2B).

Next, a portion of the wafer other than the FET (portion 4 in FIG. 1 (b)) is covered with a photo-resist, and the FET is covered.
Part of the polycrystalline GaAs layer is removed by etching. Further FET
A hole is formed in the SiO ₂ film 3 by reactive ion etching (RIE) at a portion serving as a source / drain of the GaAs.
The substrate 1 is exposed. At this time, the second around the gate electrode 2
As shown in FIG. 2B, the SiO ₂ side wall 7 for separating the n ⁺ layer and the gate electrode remains.

Next, an n ⁺ GaAs layer 5 is grown thereon by MO / CVD (metal organic chemical vapor deposition).

At this time, GaAs is formed in the source / drain windows and on the polycrystalline GaAs layer by utilizing the selective growth property of the MO / CVD method, but GaAs is grown on SiO ₂ and WSi.
Set the growth conditions for the O-CVD method. In the present embodiment, selective growth was performed with the substrate temperature set to 640 ° C. and the flow ratio of Ga and As set to 1:10. However, as can be seen from FIG. 1 (a), the portion that does not grow is a part around the gate and the element of the FET, and its area is sufficiently smaller than the entire wafer area. Accordingly, the growth rate of GaAs does not depend on the pattern, and a growth layer having a uniform thickness can be obtained over the entire surface of the wafer (FIG. 2 (c)).

Thereafter, as shown in FIG. 2 (d), the FET portion is covered with a photoresist 8 and unnecessary portions of GaAs (reference numeral 4 and the reference numeral 5) are removed by etching. A flat FET as shown in FIG. At this time, if the pattern of the photoresist 8 is a pattern slightly separated from the unnecessary GaAs layer, the GaAs layer can be completely removed without leaving the GaAs layer at the boundary due to misalignment during photolithography.

By the above steps, as shown in FIG. 2 (e), an integrated circuit having much better flatness than the conventional example (FIG. 3) can be realized, which is suitable for application to LSI.

〔The invention's effect〕

According to the present invention, a GaAs LSI can be manufactured using the n ⁺ -GaAs selective growth technology, and the resistance is reduced to about 1/10 of the resistance of the n ⁺ layer, which is conventionally formed by ion implantation. Thus, the series resistance of the FET source was improved to about 1/5. Therefore, a memory element approximately twice as fast as the conventional one could be obtained. In addition, this is the FET characteristics improved by the self-alignment of the n ⁺ GaAs selective growth layer. However, in the conventional ion implantation, the short gate effect and the shot barrier deteriorate due to the heat treatment at 800 ° C. However, the deterioration was reduced by the selective growth, and the performance was significantly improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view and a top view of one embodiment of the present invention, FIG. 2 is a cross-sectional view of a manufacturing process of an FET of one embodiment of the present invention, and FIG.
The figure is a cross-sectional view of an FET formed by a conventional method. 1 ... Semi-insulating GaAs substrate crystal, 2 ... WSi gate electrode,
3 ... SiO ₂ insulating film, 4 ... polycrystalline GaAs layer, 5 ... MOCVD
Selective growth n ⁺ layer, 6 ... FET active layer, 7 ... Gate sidewall oxide film, 8 ... Photoresist.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (2)

(57) [Claims] A step of forming an insulating film on a part of the surface of the single crystal III-V compound semiconductor substrate; a step of forming a first film on the surface of the insulating film; A step of forming a group III-V compound semiconductor film on the surface of the compound semiconductor substrate by a growth method, and a step of removing the compound semiconductor film and the first film on the surface of the first film;
A method of manufacturing a semiconductor integrated circuit, wherein the first film is made of a polycrystalline group III-V compound semiconductor. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein said first film is formed only inside the boundary of said insulating film surface with said compound semiconductor substrate.