JP3032458B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor using a compound semiconductor, and more particularly to a method for manufacturing a field effect transistor for a high-speed compound semiconductor IC used in communication equipment and computers.

[0002]

2. Description of the Related Art Conventionally, in a manufacturing process of a field effect transistor (hereinafter referred to as FET) using a compound semiconductor such as GaAs, a parasitic source-drain resistance between a gate and a source and a gate and a drain is reduced, and In order to increase the breakdown voltage between the source and the gate / drain,
LDD (Lightly D) using refractory metal gate
(Operated Drain) Refractory metal gate self-alignment process is widely used.

[0003] Hereinafter, a manufacturing method thereof will be described with reference to FIG. First, as shown in FIG. 6A, a photoresist is applied on a semi-insulating GaAs substrate 11, and selective ion implantation is performed using a photolithography process to form a channel layer (n-layer 12). Next, the n-layer 1
After depositing a high-melting point metal film on 2, an etching mask made of Al or the like is formed using a photolithography process. Next, as shown in FIG. 6B, a refractory metal gate electrode 13 is formed on the n-layer 12 by dry etching. Next, as shown in FIG. 6C, a photoresist is applied, and selective ion implantation is performed using a photolithography process, and an n ′ layer 16 having a larger implantation amount and implantation depth than the n layer 12 is formed. Form. At this time, the refractory metal gate electrode 13 also functions as a mask for ion implantation, and the positions of the n layer 12 and the n ′ layer 16 are formed in a self-aligned manner. Next, as shown in FIG. 6D, after an insulating film (through film 14) such as SiO ₂ is deposited, a photoresist is applied as shown in FIG. Of the source / drain region of the FET (the n ⁺ layer 1
8) is formed. At this time, the refractory metal gate electrode 13
Also serves as a mask for ion implantation,
The positions of the n ′ layer 16 and the n ⁺ layer 18 are formed in a self-aligned manner. Next, as shown in FIG. 6F, an insulating film (protective film 21) such as SiO ₂ is deposited, and an annealing step is performed using the film as a protective film to activate implanted ions to form an active layer of the FET. I do. Next, as shown in FIG.
Source / drain electrodes 19 are formed on the ⁺ layer 18.

However, thus prepared was FET is equal gate-source n ⁺ layer spacing and the gate-drain-side n ⁺ layer interval is higher than the gate-source between the gate and drain of the FET at the time of three-terminal operation field Is applied,
The FET thus manufactured has a low withstand voltage between the gate and the drain. In order to improve the gate-drain withstand voltage of the FET and reduce the source resistance, it is necessary to have an asymmetric structure in which the gate-drain side n ⁺ layer spacing is longer than the gate-source side n ⁺ layer spacing. is there.

Therefore, as a method of making the distance between the n ⁺ layers on the gate / drain side longer than the distance between the n ⁺ layers on the gate / source side, an asymmetric n ⁺ layer forming process by selective ion implantation using a photolithography step is used. Hereinafter, the manufacturing method will be described with reference to FIG.

First, as shown in FIG. 7A, a photoresist is applied on a semi-insulating GaAs substrate 11, and selective ion implantation is performed using a photolithography process.
A channel layer (n layer 12) is formed. Next, after a refractory metal film is formed on the n-layer 12, an etching mask made of Al or the like is formed using a photolithography process. Next, as shown in FIG. 7B, a refractory metal gate electrode 13 is formed on the n-layer 12 by dry etching. Next, as shown in FIG. 7C, a photoresist is applied, and selective ion implantation is performed using a photolithography process, and an n ′ layer 16 having a larger implantation amount and implantation depth than the n layer 12 is formed. Form. Next, as shown in FIG. 7D, after an insulating film (through film 14) such as SiO ₂ is deposited, as shown in FIG. 7E, a photoresist is applied, and then a gate is formed by a photolithography process. By forming a resist mask 15 only on the electrode 13 and in the vicinity of the gate electrode 18 on the drain side and performing selective ion implantation, the source / drain region (n ⁺ layer 1
8) is formed. At this time, the gate electrode 13 on the drain side
The n ⁺ layer 18 is formed such that the distance between the n ⁺ layers on the gate / drain side is longer than the distance between the n ⁺ layers on the gate / source side, because it is not implanted into the vicinity. Next, as shown in FIG. 7F, an insulating film (protective film 21) such as SiO ₂ is deposited,
An annealing step is performed using the film as a protective film to activate the implanted ions to form an active layer of the FET. Next, FIG.
As shown in (g), source / drain electrodes 19 are formed on the n ⁺ layer 18.

According to this manufacturing method, it is possible to make the distance between the n ⁺ layers on the gate / drain side longer than the distance between the n ⁺ layers on the gate / source side.

[0008]

However, the asymmetric n ⁺ layer forming process by selective ion implantation using the photolithography process as described above has the following problems.

In this manufacturing method, when an asymmetric n ⁺ layer is formed, only the gate electrode 13 and the vicinity of the gate electrode 13 on the drain side are formed by photolithography so that ions are not implanted near the gate electrode 13 on the drain side of the FET. By forming a resist mask 15 and performing selective ion implantation using the resist mask 15 as a mask, an n ⁺ layer 18 is formed. Therefore, the gate-drain side n ⁺ layer spacing is determined by the pattern size of the resist mask 15. However, since the alignment accuracy in the photolithography process is about ± 0.1 μm,
Due to misalignment and variations in resist pattern dimensions, the gate-drain side n ⁺ layer spacing may vary, and the gate-drain breakdown voltage may vary.

Further, it is difficult to form a pattern of 0.5 μm or less by photolithography using UV light, so that the distance between the n ⁺ layer on the gate / drain side cannot be reduced to 0.5 μm or less. Therefore, as shown in FIG. 8, the drain resistance is greatly increased and the mutual conductance is reduced as compared with the symmetric n ⁺ -layer structure FET, which is not suitable for a high-output FET that operates with a large signal.

SUMMARY OF THE INVENTION The present invention has been made in view of the foregoing, and an object of the present invention is to form a gate-drain-side n ⁺ layer spacing with good reproducibility, to provide high gate-drain breakdown voltage and high mutual conductance, and to provide high reproducibility And to provide a method of manufacturing an FET having a good performance.

[0012]

To achieve the above object SUMMARY OF THE INVENTION, Claim 1,2,3,4,5,6,7, 8 Contact and 9
Of the method for manufacturing a field-effect transistor described in (1).

According to a first aspect of the present invention, there is provided a first step of forming a gate electrode on a substrate on which an active layer region is formed, and a step of forming a first insulating film on the substrate including the gate electrode. A second step of forming, a third step of selectively removing the first insulating film in a region on the source side of the active layer region, and using the gate electrode and the first insulating film as a mask. A fourth step of performing ion implantation, a fifth step of forming a second insulating film on the substrate, and ion implantation using the gate electrode, the first insulating film, and the second insulating film as masks And a sixth step of performing the following.

According to a second aspect of the present invention, there is provided a first step of forming a gate electrode on a substrate on which an active layer region is formed, and a second step of performing ion implantation using the gate electrode as a mask. A first electrode on the substrate including the gate electrode;
A third insulating film, a fourth step of selectively removing the first insulating film in a region on the source side of the active layer region, and a second insulating film on the substrate. And a sixth step of performing ion implantation using the gate electrode, the first insulating film, and the second insulating film as masks.

According to a third aspect of the present invention, there is provided a first step of forming a gate electrode on a substrate on which an active layer region is formed, and a second step of performing ion implantation using the gate electrode as a mask. A first electrode on the substrate including the gate electrode;
Forming a second insulating film on the substrate, selectively forming the second insulating film in a region on the source side of the active layer region. And a sixth step of performing ion implantation using the gate electrode, the first insulating film, and the second insulating film as masks.

Means taken by the invention of claim 4 is claim 1
In the second aspect, after the step of forming a first insulating film on the substrate including the gate electrode, a step of forming a sidewall made of the first insulating film on a side wall of the gate electrode by dry etching Is a method further comprising:

Means taken by the invention of claim 5 is claim 3
In the invention, after the step of forming a first insulating film on the substrate including the gate electrode, a step of forming a sidewall made of the first insulating film on a side wall of the gate electrode by dry etching is further included. It is a prepared method.

Means taken by the invention of claim 6 is claim 1
Alternatively, in the invention of 2 or 4, after the sixth step of performing ion implantation using the gate electrode, the first insulating film, and the second insulating film as a mask, the first insulating film and the second This method further includes a seventh step of performing annealing using the insulating film as a protective film.

Means taken by the invention of claim 7 is claim 3
In the invention, after the sixth step of performing ion implantation using the gate electrode, the first insulating film, and the second insulating film as a mask, the first insulating film and the second insulating film are protected. This is a method further comprising a seventh step of performing annealing as a film.

Means taken by the invention of claim 8 is claim 4
Alternatively, in the invention according to the sixth aspect, the first insulating film is an SiN film, and the second insulating film is an SiO ₂ film.

The measures taken by the invention of claim 9 are the following:
In the invention according to the seventh aspect, the first insulating film is formed of SiO ₂
And a method wherein the second insulating film is a SiN film or a WSiN film.

[0022]

[0023]

[0024]

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing an FET according to the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment will be described with reference to FIG. FIG. 1 is a sectional view showing a structure in each manufacturing process of the FET according to the first embodiment.

First, as shown in FIG. 1A, a semi-insulating GaAs substrate 11 is used as a substrate, and the semi-insulating GaAs substrate 11 is used.
The photoresist is used as a mask on an As substrate 11 at an acceleration voltage of 20 keV and a dose of about 1.0 × 10 ¹³ cm ⁻² to form S.
I channel ions are implanted to form a channel layer (n layer 12).

Next, as shown in FIG. 1B, a 200-nm thick gate metal is formed on the surface of the semi-insulating GaAs substrate 11.
After a mSi WSi film is deposited, a gate electrode 13 is formed by anisotropic dry etching by RIE using Al or the like as a mask.

Next, as shown in FIG. 1C, an approximately 200 nm-thick SiN film is deposited as a first through film 14 on the semi-insulating GaAs substrate 11 including the gate electrode 13.

Next, as shown in FIG.
Mask 1 so as to cover only the drain side region of
5 is formed, and S is formed by dry etching using RIE.
The iN film (first through film 14) is etched to expose the source-side region of the n-layer 12.

Next, as shown in FIG. 1E, Si ions are implanted on the semi-insulating GaAs substrate 11 using a photoresist as a mask at an acceleration voltage of 30 keV and a dose of about 3.0 × 10 ¹² cm ^−2. Then, an n ′ layer 16 is formed.

Next, as shown in FIG. 1F, a SiO ₂ film having a thickness of about 300 nm is deposited as the second through film 17.

Next, as shown in FIG.
Semi-insulating through the loop film 14 and the second through film 17
A photoresist is used as a mask on the GaAs substrate
Fast voltage 150 keV, dose 5.0 × 10¹³cm^-2About
Implant Si ions at a temperature of n ⁺After forming the layer 18, the first
The first through film 14 and the second through film 17 are used as protective films.
And annealing at 800 ° C. for about 15 minutes
Activate the injection layer.

Next, as shown in FIG.
A source / drain electrode 19 made of a / Ni / Au layer is formed.

In this embodiment, as shown in FIG.
After selectively removing the SiN film that is the first through film 14 on the source side region of the n layer 12, an SiO ₂ film is deposited as a _second through film 17 as shown in FIG. As shown in FIG. 1G, the first through film 14 and the second
N ⁺ layer 1 by Si ion implantation through through film 17 of
8, the distance between the gate and source n ⁺ layers is determined in a self-aligned manner by the second through film thickness, and the distance between the gate and drain n ⁺ layers is equal to the first and second through film thicknesses. Determined in a self-aligned manner by the sum. Therefore, the gate / drain side n
⁺ Variations in the layer spacing are eliminated, and the reproducibility of the gate-drain breakdown voltage is improved.

Further, as shown in FIG. 1 (g), since no resist mask is used in forming the n ⁺ layer,
The distance between the n ⁺ -layers on the drain side can be made 0.5 μm or less, and as shown in FIG. 8, the gate-drain breakdown voltage can be kept high without reducing the mutual conductance.

Further, as shown in FIG. 1G, by using the first through film 14 and the second through film 17 as a protective film for annealing, the source side region is formed by the second through film 17. Annealing is performed using only a certain SiO ₂ film as a protective film, and the drain side region is the first through film 14 which is S
Since the iN film and the SiO ₂ film serving as the second through film 17 are annealed with the protection film, the activation of the drain side region is worse than that of the source side region. Can be.

(Second Embodiment) Next, a second embodiment will be described with reference to FIG. FIG. 2 is a cross-sectional view showing a structure in each manufacturing step of the FET according to the second embodiment.

First, in the steps shown in FIGS. 2A and 2B, the same steps as those shown in FIGS. 1A and 1B in the first embodiment are performed.

Next, as shown in FIG. 2C, Si ions are implanted on the semi-insulating GaAs substrate 11 using a photoresist as a mask at an acceleration voltage of 30 keV and a dose of about 3.0 × 10 ¹² cm ^−2. Then, an n ′ layer 16 is formed.

Next, in the steps shown in FIGS. 2D and 2E, the same steps as those shown in FIGS. 1C and 1D in the first embodiment are performed.

Thereafter, as shown in FIGS. 2 (f) to 2 (h), FIG. 1 (f) to FIG.
A step similar to the step shown in (h) is performed.

The basic structure of the FET according to the present embodiment is the same as that of the FET according to the first embodiment, and the same effects can be exerted. Further, the FET according to the present embodiment includes:
Since the n 'layer 16 is also formed on the drain side, there is an advantage that the drain resistance can be reduced, a large mutual conductance can be obtained, and a higher speed operation can be performed as compared with the FET according to the first embodiment. is there.

Third Embodiment Next, a third embodiment will be described with reference to FIG. FIG. 3 is a cross-sectional view showing a structure in each manufacturing step of the FET according to the third embodiment.

First, in the steps shown in FIGS. 3 (a) to 3 (c), the steps shown in FIGS.
A step similar to the step shown in (c) is performed.

Next, as shown in FIG. 3D, a SiO ₂ film having a thickness of about 200 nm is deposited as a first through film 14 on the semi-insulating GaAs substrate 11 including the gate electrode 13.

Next, as shown in FIG. 3E, an approximately 300 nm-thick SiN film is deposited as the second through film 17.

Next, as shown in FIG.
Mask 1 so as to cover only the drain side region of
5 is formed, and S is formed by dry etching using RIE.
By etching only the iN film (second through film 17),
The SiO ₂ film (first through film 14) on the source side region of the n-layer 12 is exposed.

Thereafter, as shown in FIGS. 3G and 3H, the same steps as those shown in FIGS. 1G and 1H in the first embodiment are performed.

In this embodiment, as shown in FIG.
The second through film 17 on the source side region of the n-layer 12
After selectively removing the SiN film, as shown in FIG.
Through the first through film 14 and the second through film 17
And n by Si ion implantation ⁺The layer 18 is formed
And the gate / source side n⁺Layer spacing should be the first through film thickness
Therefore, it is determined in a self-aligned manner and the gate / drain side n⁺
The layer interval is determined by the sum of the first and second through film thicknesses.
Determined self-consistently. Therefore, the FET according to the present embodiment
Has the same basic structure as the FET according to the second embodiment.
Therefore, a similar effect can be exhibited. Further implementation
In the example, as shown in FIG.
For selectively removing the SiN film as the second through film 17
The first through film 14 and the second through film 17
A resist mask 15 is formed on the gate electrode 13 thus formed.
Therefore, as compared with the first embodiment and the second embodiment,
The pattern size of the through film on the gate electrode 13 is large.
Of the resist mask 15 when forming the resist mask 15.
For larger gates and smaller gates
There is an advantage that can also be used.

In this embodiment, the SiN film is used as the second through film 17, but the same effect can be obtained by using the WSiN film.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIG. FIG. 4 is a sectional view showing a structure in each manufacturing step of the FET according to the fourth embodiment.

First, in the steps shown in FIGS. 4A to 4D, the steps shown in FIGS.
A step similar to the step shown in (d) is performed.

Next, as shown in FIG. 4E, the SiN film as the first through film 14 is anisotropically etched by RIE without using an etching mask, and
A sidewall 20 made of a SiN film is formed on the side wall of No. 3.

Next, as shown in FIG.
Mask 1 so as to cover only the drain side region of
5 and selectively remove the side wall 20 on the source side by dry etching using RIE.

Thereafter, as shown in FIGS. 4 (g) to 4 (i), FIG. 2 (f) to FIG.
A step similar to the step shown in (h) is performed.

In this embodiment, as shown in FIG.
After selectively removing the source side wall 20,
As shown in FIG. 4G, the second through film 17 is made of S
iO _TwoA film is deposited and a first scan is performed as shown in FIG.
Side wall 20 and second through hole
-N by implantation of Si ions through the film 17⁺Shape layer 18
The gate / source side n⁺Layer spacing is second
The gate thickness is determined in a self-aligned manner by the through film thickness.
Rain side n⁺The layer spacing is the sum of the first and second through film thicknesses.
It is determined in a self-consistent manner by the total. Therefore, this embodiment
The basic structure of the FET according to the second embodiment is the same as that of the FET according to the second embodiment.
The structure is the same, and a similar effect can be exhibited.

(Fifth Embodiment) Next, a fifth embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional view showing a structure in each manufacturing step of the FET according to the fifth embodiment.

First, in the steps shown in FIGS. 5A to 5D, the steps shown in FIGS.
A step similar to the step shown in (d) is performed.

Next, as shown in FIG. 5E, the SiO ₂ film as the first through film 14 is anisotropically etched by RIE without using an etching mask, and SiO ₂ film is formed on the side wall of the gate electrode 13. _A sidewall 20 composed of _two films is formed.

Next, as shown in FIG.
A step similar to the step shown in FIG. 3E in the embodiment is performed.

Next, as shown in FIG. 5G, a resist mask 15 is formed so as to cover only the drain side region, and the SiN film (the second layer) on the source side region is formed by dry etching using RIE. Only the through film 17) is selectively removed.

Next, as shown in FIG.
Semi-insulating through the wall 20 and the second through film 17
A photoresist is used as a mask on the GaAs substrate
Fast voltage 150 keV, dose 5.0 × 10¹³cm^-2About
Implant Si ions at a temperature of n ⁺The layer 18 is formed. Next
After the second through film 17 is removed, a film is formed as a protective film 21.
A SiN film having a thickness of about 100 nm is deposited,
Anneal for about a minute to activate the ion implanted layer.
You.

Thereafter, as shown in FIG. 5I, the same steps as those shown in FIG. 3H in the third embodiment are performed.

In this embodiment, as shown in FIG.
After selectively removing the second through film 17 on the source side,
As shown in FIG. 5H, since the n ⁺ layer 18 is formed by implanting Si ions through the side wall 20 made of the first through film 14 and the second through film 17,
The gate-source side n ⁺ layer spacing is determined in a self-aligned manner by the first through film thickness, and the gate-drain side n ⁺ layer spacing is determined in a self-aligned manner by the sum of the first and second through film thicknesses. You. Therefore, the FET according to the present embodiment is
The basic structure is the same as the FET according to the third embodiment,
Similar effects can be exerted.

[0066]

As described above, according to the present invention, the following effects can be obtained.

According to the first, second, third, fourth and fifth aspects of the present invention, the n + layer 18 is formed by implanting Si ions through the first through film 14 and the second through film 17 to thereby reduce the drain side. The n ⁺ layer can be formed in a self-aligned manner with respect to the gate, and the reproducibility of the gate-drain breakdown voltage is improved.

[0068] Further, since no use of a resist mask during the n ⁺ layer forming the gate-drain-side n ⁺ layer interval 0.
8 μm or less, and as shown in FIG. 8, the gate-drain breakdown voltage can be kept high without reducing the mutual conductance.

According to the sixth and seventh aspects of the present invention, the first through film 14 and the second through film 17 are used as protective films for annealing, and annealing is performed using different protective films on the source side and the drain side. By doing so, the activation of the drain side region becomes worse than that of the source side region, and the gate-drain breakdown voltage can be further increased.

According to the eighth aspect of the present invention, the first through film is an SiN film and the second through film is an SiO ₂ film, so that the source side region is the second through film.
In it it is annealed only SiO ₂ film as a protective film, since the drain-side region is annealed SiO ₂ film is SiN film and a second through film 17 is first through film 14 as a protective film, the drain-side Since the activation of the region is worse than that of the source side region, the withstand voltage between the gate and the drain can be further increased.

According to the ninth aspect of the present invention, by forming the first through film 14 as a SiO ₂ film and the second through film 17 as a SiN film or a WSiN film, the source side region is formed as the first through film. Annealing is performed using only the SiO ₂ film 14 as a protective film, and the drain-side region is the SiO ₂ film as the first through film 14 and the SiN as the second through film 17.
Since the film or the WSiN film is annealed as a protective film, the activation of the drain side region is worse than that of the source side region, so that the gate-drain breakdown voltage can be further increased.

In the step of selectively removing the second through film on the source side, RIE using a fluorine-based gas is performed.
By utilizing the difference in etch rate between the SiO ₂ film and the SiN film or the WSiN film, the SiN film or the WSiN film serving as the second through film 17 can be selectively removed.

[0073]

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure in each manufacturing step of a field-effect transistor according to a first embodiment.

FIG. 2 is a cross-sectional view showing a structure in each manufacturing step of a field-effect transistor according to a second embodiment.

FIG. 3 is a cross-sectional view showing a structure in each manufacturing step of a field-effect transistor according to a third embodiment.

FIG. 4 is a sectional view showing a structure in each manufacturing step of a field-effect transistor according to a fourth embodiment.

FIG. 5 is a sectional view showing a structure in each manufacturing step of a field-effect transistor according to a fifth embodiment.

FIG. 6 is a cross-sectional view showing a structure in each manufacturing process of a conventional field-effect transistor.

FIG. 7 is a cross-sectional view showing a structure in each manufacturing step of a conventional field-effect transistor.

FIG. 8 is a diagram showing the dependence of the gate-drain breakdown voltage and the mutual conductance on the difference between the gate-drain side n ⁺ layer spacing and the gate-source side n ⁺ layer spacing.

[Explanation of symbols]

Reference Signs List 11 substrate (semi-insulating GaAs substrate) 12 n layer 13 gate electrode 14 first through film 15 resist mask 16 n 'layer 17 second through film 18 n ⁺ layer 19 source / drain electrode 20 side wall 21 protective film

Claims (9)

(57) [Claims] A first step of forming a gate electrode on a substrate on which an active layer region is formed; a second step of forming a first insulating film on the substrate including the gate electrode; A third step of selectively removing the first insulating film in a region on the source side of the active layer region, and a fourth step of performing ion implantation using the gate electrode and the first insulating film as a mask. A fifth step of forming a second insulating film on the substrate, and a sixth step of performing ion implantation using the gate electrode, the first insulating film, and the second insulating film as a mask. A method for manufacturing a field effect transistor, comprising: 2. A first step of forming a gate electrode on a substrate on which an active layer region is formed, a second step of performing ion implantation using the gate electrode as a mask, and a step of forming a gate electrode on the substrate including the gate electrode. A third step of forming a first insulating film on the substrate, a fourth step of selectively removing the first insulating film in a region on the source side of the active layer region, and a second step of forming a second insulating film on the substrate. A field effect transistor, comprising: a fifth step of forming an insulating film, and a sixth step of performing ion implantation using the gate electrode, the first insulating film, and the second insulating film as a mask. Manufacturing method. 3. A first step of forming a gate electrode on a substrate having an active layer region formed thereon, a second step of performing ion implantation using the gate electrode as a mask, and a step of forming a gate electrode on the substrate including the gate electrode. A third step of forming a first insulating film on the substrate, a fourth step of forming a second insulating film on the substrate, and a step of forming the second insulating film on a source side of the active layer region. A field-effect transistor comprising: a fifth step of selectively removing GaN; and a sixth step of performing ion implantation using the gate electrode, the first insulating film, and the second insulating film as a mask. Manufacturing method. 4. A method according to claim 1, wherein a first step is performed on the substrate including the gate electrode.
3. The field effect according to claim 1, further comprising, after the step of forming the insulating film, forming a side wall made of the first insulating film on a side wall of the gate electrode by dry etching. A method for manufacturing a transistor. 5. The method according to claim 5, wherein a first electrode is provided on the substrate including the gate electrode.
4. The field effect transistor according to claim 3, further comprising a step of forming a sidewall made of the first insulating film on a side wall of the gate electrode by dry etching after the step of forming the insulating film. Production method. 6. After the sixth step of performing ion implantation using the gate electrode, the first insulating film, and the second insulating film as a mask, the first insulating film and the second insulating film are removed. 5. The method for manufacturing a field effect transistor according to claim 1, further comprising a seventh step of performing annealing as a protective film. 7. After the sixth step of performing ion implantation using the gate electrode, the first insulating film, and the second insulating film as a mask, the first insulating film and the second insulating film are removed. The method according to claim 3, further comprising a seventh step of performing annealing as a protective film. 8. The method according to claim 4, wherein the first insulating film is a SiN film, and the second insulating film is a SiO ₂ film. 9. The method according to claim 1, wherein the first insulating film is a SiO ₂ film,
8. The method according to claim 3, wherein the second insulating film is a SiN film or a WSiN film.