JPH02234442A - Manufacture of field effect type semiconductor device - Google Patents

Abstract

PURPOSE:To control short-channel effect and improve reliability by providing a multi-layer gate electrode where three or more heat-resistant metal layers with different stress characteristics are laminated. CONSTITUTION:A high-resistance GaAs substrate 1, an undoped GaAs 2, an n-type GaAs 3 with impurities concentration of 2X10<18>cm<-3> and a film thickness of 20nm, an ohmic electrode 4 by Ni/Au/Ge, WSi 5, LaB6 6, and W are provided. These metals 5, 6, and 7 form a gate electrode and these are formed by the sputter method, the electron beam gun deposition method, and the sputter method, respectively. By forming a gate in multi-layer structure and inserting the LaB6 6 to control separation of a metal film for restricting stress generated at the interface between WSi 5 and W 7, thus preventing an abnormal diffusion of impurity ions due to concentration of stress at the gate electrode edge. Therefore, it is possible to control short-channel effect and improve reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a highly reliable high-speed semiconductor device and a method for manufacturing the same.

(Prior Art) In recent years, research and development of ultra-high-speed semiconductor integrated circuits using compound semiconductors such as GaAs have been actively conducted. In particular, since the establishment of highly controlled growth methods such as the molecular beam epitaxial method (MBE method), research and development of ultra-high speed semiconductor devices and integrated circuits using ultra-thin epitaxial semiconductor layers with high impurity density has rapidly progressed. Progress is being made.

Conventionally, for example, GaAs field effect transistors (GaAs
sMESFET), we aim to reduce parasitic resistance.
In order to achieve high-speed devices, ions were implanted into the parasitic region outside the gate electrode, and an electrically resistive layer was formed by heat treatment. In this case, WSi, which has excellent heat resistance and has a stable interface with GaAs, is often used for the gate electrode. In addition, ion implantation into the parasitic region is usually performed in a self-aligned manner into the WSi gate electrode after WSi processing.
Heat treatment is performed at 00°C for about 20 minutes. However, in reality, the WSi gate electrode and the Si3N4 film are
It is known that since the thermal expansion coefficients of aAs differ greatly, stress is generated at the end of the gate electrode, causing abnormal diffusion of impurity ions implanted into GaAs.

As a result, short channel effects are poorly controlled and the FE
It has been difficult to shorten the gate length, which is advantageous for increasing the speed of T.

In addition, as gate electrode materials, in order to reduce gate resistance,
For example, a two-layer structure of W and WSi may be used, but the above-mentioned problem also occurs. Furthermore, in this case, W,
Since the stress characteristics of WSi and GaAs are different, there is also the problem that the metal film is likely to peel off.

(Problems to be Solved by the Invention) An object of the present invention is to provide a high-speed semiconductor device that solves these problems, controls short channel effects, and has excellent reliability, and a method for manufacturing the same.

(Means for Solving the Problem) The structure of the field-effect semiconductor device of the present invention is characterized by comprising a multilayer electrode gate electrode in which three or more heat-resistant metal layers having mutually different stress characteristics are laminated. .

The method for manufacturing a field-effect semiconductor device of the present invention includes a step of forming three or more heat-resistant metal layers having different etching characteristics on a semiconductor layer, and a step of forming three or more heat-resistant metal layers having different etching characteristics on a semiconductor layer, and using a gas containing a halogen element to form a metal layer of a lower layer. selectively removing the overlying metal layer over the stop layer to expose the underlying metal layer;
The method is characterized by comprising at least a step of implanting ions into a semiconductor layer through an underlying metal layer, and a step of subsequently performing heat treatment.

Furthermore, the structure of the field effect semiconductor device of the present invention is such that an electrode is formed of a first heat-resistant metal layer having mutually different etching characteristics on the semiconductor layer, and a third heat-resistant multilayer metal layer on the second heat-resistant metal layer. and selectively removing a part of the third heat-resistant multilayer metal layer using a gas containing a halogen element with the second heat-resistant metal layer on top of the stop layer;
A step of exposing the second heat-resistant metal layer in this partial region, a step of implanting ions into the semiconductor layer through the exposed second heat-resistant metal layer, a step of forming an insulating film, and a step of forming an insulating film. The method includes at least the steps of performing vertical processing using an anisotropic dry etching method to form sidewalls, reinjecting ions into the semiconductor layer through the exposed second heat-resistant metal layer, and subsequently performing heat treatment. It is characterized by becoming.

Next, the present invention will be explained in detail with reference to the drawings.

(Example 1) FIG. 1 is a structural sectional view of a semiconductor device according to an example of the present invention. FIG. 1 shows, for example, metal organic chemical vapor deposition (MOC)
1 is a cross-sectional view of a semiconductor crystal grown using a VD method.

In Figure 1, 1 is a high-resistance GaAs substrate, 2 is undoped GaAs, and 3 is the impurity density, 2×1018 cm=
20 nm thick n-type GaAs, 4 is Ni/Au/G
Ohmic electrode by e, 5 is W8i, 6 is LaB6,
7 is W. A gate electrode is formed of the metals of formulas 5, 6, and 7. Gate metals 5, 6 and 7 are
They are formed by a sputtering method, an electron beam gun evaporation method, and a sputtering method, respectively. By making the gate a multilayer structure, the gate metal resistance Rg is reduced by about 1 compared to the conventional single layer WSi.
The maximum effective gain was significantly improved. In addition, the stress generated at the interface between WSi5 and W7 can be reduced by LaB66.
By inserting , the peeling of the metal film could be controlled, and a highly reliable gate electrode could be formed.

(Example 2) FIGS. 2(a) to 2(e) show main manufacturing steps of a method for manufacturing a semiconductor device according to an example of the present invention.

As shown in FIG. 2(a), using molecular beam epitaxy (MBE), undoped GaAs2 was deposited on a high-resistance GaAs substrate 1 at a thickness of 0.5 pm and an impurity density of 2×.
After sequentially epitaxially growing n-type GaAs3 with a film thickness of 20 nm at 1018 cm-3, W, which becomes the gate electrode material, was grown.
Si5 is formed by a supanota method, then LaB6 is formed by a vapor deposition method, and W7 is further formed by a sputtering method. Next, as shown in FIG. 2(b), using the photoresist (PR) 8 as a mask, the W7 is processed by dry etching using CF4 gas 9. Then, as shown in FIG. At this time, the etching rate of LaB66 is set to be sufficiently smaller than that of W7.

For example, it is desirable that the power be 100 W, the gas pressure be 1 mTorr, and the gas flow rate be about 10 SCCM. Next, as shown in FIG. 2(C), Si ions 11 were injected into the parasitic region at 5×1013 cm−2 and 100 ke by passing WSi5 and LaB66 into the parasitic region.
Inject under the condition of V.

Thereafter, heat treatment is performed at 800° C. for 20 minutes while leaving WSi5 and LaB66 in the parasitic region. Next, the second
As shown in figure (d), after removing LaB66 using, for example, Ar ion milling method, W is removed using CF4 gas.
Process Si5 using a dry etching method. Finally, Figure 2 (
As shown in e), an ohmic electrode 4 made of Ni/Au/Ge is formed.

In this embodiment, a low resistance parasitic region can be formed in the gate electrode in a self-aligned manner. This is extremely advantageous in improving the mutual conductance of the device. Furthermore, since the same material WSi5 as the gate metal can be used for the heat-treated protective film, further diffusion of impurity ions due to stress concentration at the end of the gate electrode, which was a problem in the conventional method, can be prevented. Moreover, as a result, even in a device having a short gate of 0.5 pm, good pinch-off characteristics, uniformity of characteristics, and reproducibility could be obtained. In addition, in this example, the processing of W7, which is the prototype of the gate electrode pattern, is
Since aB66 was formed on the automatic stop layer, the uniformity of the fine gate length within the substrate surface was also extremely good.

(Example 3) FIGS. 3(a) to 3(O) are main manufacturing steps of a method for manufacturing a semiconductor device according to an example of the present invention.
For example, it is a cross-sectional view of a semiconductor crystal grown using a metal organic chemical vapor deposition method (MOCVD method). In Figure 1,
1 is a high resistance GaAs substrate, 2 is undoped GaAs,
3 has an impurity density of 2 x 1018 cm-3 and a film thickness of 20 nm.
4 is an ohmic electrode made of Ni/Au/Ge, 5 is WSi, 6 is LaB6, and 7 is W. At this time, gate electrodes are formed of metals 5 and 7.

As shown in FIG. 3(a), after epitaxially growing an n-type GaAs conductive layer, WSi5, which will become the gate electrode material, is formed by sputtering, then LaB66 is formed by vapor deposition, and then W7 is formed by sputtering. Form. Next, Figure 3 (b
), using a photoresist (PR) 8 as a mask, W7 is processed by dry etching using CF4 gas 9. At that time, the etching rate of LaB66 was W7
Set it so that it is sufficiently smaller than that of .

For example, a power of 100 W, a gas pressure of 1 mTorr, and a gas flow rate of about 10 SCCM are desirable. Next, as shown in FIG. 3(c), 300nm of Si02 is deposited on the entire surface by CVD method.
m is deposited, and Si02 is processed by anisotropic dry etching using CF4 gas to form gate sidewalls 10. Furthermore, Si ions 11 are implanted into the parasitic region through WSi5 and LaB66 under conditions of 5×10 13 cm −2 and 100 keV. Next, as shown in FIG. 3(d), after removing the gate sidewalls with HF, Si ions 12 are injected into the parasitic region by 5×1012a through WSi5 and LaB66.
Implantation is performed under the conditions of m-2 and 50 keV. After that, the temperature was heated to 80°C while leaving WSi5 and LaB66 in the parasitic region.
, heat treatment for 20 minutes. Next, as shown in FIG. 3(e), after removing LaB66 using, for example, Ar ion milling, WSi5 is processed by dry etching using CF4 gas. Finally, as shown in FIG. 3 (D), an ohmic electrode 4 made of Ni/Au/Ge is formed.

In this example, since the gate sidewalls 9Si0210 are deposited on metal and dry processed, direct damage to the semiconductor layer can be minimized. This made it possible to control the frequency dispersion of device characteristics. In addition, the WSi layer 5 for the gate electrode and the semiconductor layer 3 of the parasitic part into which ions are implanted
Since the contact point with the ferrite layer has a low impurity density, it was possible to control the short channel effect. Furthermore, it was confirmed that the other effects described in Example 2 were also maintained.

In addition, in Example 2 and Example 3, S
i ion implantation was performed through LaB66, but LaB
66 may be removed. Furthermore, before the heat treatment, a protective film such as Si3N4 may be formed to control external diffusion of semiconductor constituent elements. In addition to the gate electrode materials used in this example, for example, WSiN, WAL
Metal silicides, borides, carbides, etc. having heat resistance such as WN, WAIN, MoSi, Taxi, etc. may be used. The amount of these metal materials must be able to withstand the heat treatment temperature for electrical activation of the implanted ions, which is usually 500°C.
It is desirable to have heat resistance of °C or higher. Furthermore, the present invention can be used not only for FETs but also for forming emitter electrodes of bipolar transistors, for example.

Further, the present invention is similarly effective for other semiconductor materials such as InP and Si, and other elements such as high electron mobility transistors (HEMTs).

(Effects of the Invention) As described above, in the semiconductor device having the structure described in claim 1, since the gate electrode has a multilayer structure, a gate electrode with low gate metal resistance and low stress can be obtained.

According to the method for manufacturing a semiconductor device described in claim 2, ion implantation for forming the contact layer is performed through the metal, and the metal can be used as it is as a recovery annealing protective film after the ion implantation, thereby reducing stress concentration. Damage caused by impurity ion diffusion and ion implantation is suppressed, and a manufacturing method with excellent reproducibility can be obtained. According to the manufacturing method of the third aspect, since the gate sidewall insulating film is not formed on metal, damage to the semiconductor layer during dry processing of the gate insulating film can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of the main part structure of a semiconductor device of the present invention, FIG. 2(a) to FIG. 2(e) and FIG. 3(a) to FIG. This is a main manufacturing process of a method for manufacturing a semiconductor device according to an embodiment. 1... GaAs substrate, 2... Undoped GaAs,
3... n-type GaAs, 4... ohmic electrode, 5,
6.7... Gate electrode, 8... Photoresist, 9
．． 14... Etching gas, 10... Si02, 1
1.12... Ion implantation, 13... Ion implantation region. Figure 1

Claims (3)

[Claims] (1) A field-effect semiconductor device comprising, as a gate electrode, a multilayer electrode in which three or more heat-resistant metal layers having different stress characteristics are laminated. (2) A step of forming three or more heat-resistant metal layers with different etching characteristics on the semiconductor layer, and selectively removing the upper metal layer using a gas containing a halogen element, using the lower metal layer as a stop layer. A method for manufacturing a field effect semiconductor device, comprising: exposing a lower metal layer; implanting ions into a semiconductor layer through the lower metal layer; and subsequently performing heat treatment. . (3) A first layer having different etching characteristics on the semiconductor layer.
a step of sequentially forming an electrode consisting of a heat-resistant metal layer, a second heat-resistant metal layer, and a third heat-resistant multilayer metal layer, and forming the third heat-resistant multilayer metal layer using a gas containing a halogen element. selectively removing a part of the region using a second heat-resistant metal layer as a stop layer and exposing the second heat-resistant metal layer in the part of the region; a step of implanting ions into the semiconductor layer through the layer, a step of forming an insulating film, a step of vertically processing the insulating film by an anisotropic dry etching method to form a side wall, and a step of forming the exposed second heat-resistant metal layer. 1. A method for manufacturing a field-effect semiconductor device, comprising at least the steps of reinjecting ions into a semiconductor layer through a semiconductor layer, and subsequently performing heat treatment.