JPS61239673A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a compound semiconductor FET by a method wherein an insulating wall is formed onto the side surface of a gate electrode, a high conductive layer having the same conduction type as an operating layer is shaped onto the surface of a compound semiconductor, a IV group element thin-film is superposed thereon, the same conduction type impurity is implanted and an ohmic contact material is applied. CONSTITUTION:Si ions are implanted to a semi-insulating GaAs substrate 1 under conditions of 60KeV and 2X10<12>cm<-3> to form an operating layer 2, a TiW gate electrode 3 is coated with SiO2, and insulating walls 4 are shaped through anisotropic etching by employing CF4. GaAs 5 is superposed and Si is added in 1X10<18>cm<-3>, a Ge thin-film 6 is superposed and Si ions are implanted to the whole surface under the conditions of 300KeV and approximately 1X10<15>cm<-3>, and the whole is coated with an SiO2 film and annealed at 800 deg.C in H2. The SiO2 film is removed and Ni 7 is superposed thereon, and a resist 8 is applied. The top surface of the gate electrode 3 is exposed through ion milling from a flat surface, and a resist on a wafer is removed and an electrode 9 is shaped through alloying treatment in H2. An inter-layer insulating film 10 is formed, and an electrode wiring 11 consisting of Ti-Pt-Au is attached, thus completing a semiconductor device. According to the constitution, a compound semiconductor FET, a short channel effect thereof is inhibited and parasitic resistance thereof is also reduced, is acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION (Description of the technical field to which the invention pertains) The present invention relates to a method for manufacturing a compound semiconductor field effect transistor.

(Description of Prior Art) Compound semiconductors, particularly gallium arsenide (GaAs), are currently being researched in various places because they hold great promise as post-silicon materials and can be used to manufacture field-effect transistors (FETs) and integrated circuits capable of high-speed operation. We are running out of prototypes. Due to the demand for high performance FET characteristics, currently a manufacturing method is known in which a highly conductive source/drain M (hereinafter also referred to as an n+ layer because it consists of an n+ layer) is formed close to the gate region. (19B3 IEE Solid State Circuit Conference, Digest Technical Papers, page 44 (1)
983IEEE International 5ol
idState C1rkits Conference
e, Digest of Technical Paper
rsP, 44). Figure 2 is a schematic cross-sectional view of these FETs. The high conductivity source/drain is delivered, and impurities having the same conductivity type as the active layer are implanted at a high concentration using the ion implantation method, using the gate electrode as a mask. It is manufactured by a well-known method. In FIG. 2, 1 is a semi-insulating substrate, 22
3 is an active layer, 3 is a gate electrode, 24 is a high conductivity source/drain layer, 25 is a source/drain ohmic electrode, 26
1 is an interlayer insulating film, and 11 is a source/drain electrode wiring. FE with such high conductivity source/drain layers
With T, it is possible to reduce parasitic resistance and increase mutual conductance, leading to improved FET characteristics and integrated circuit performance.

As shown in Figure 2, high conductivity source/drain layers,
That is, when forming an n+ layer by ion implantation, this n''
Regarding the depth of 1M, the greater the depth, the smaller the resistance of the n+ layer is, which is preferable.However, as the fluency of the n+ layer increases, the so-called short channel effect becomes more prominent, and as the gate length decreases, 1 ′°°゛"ta'o＊ir""
""1°, L, i'l (['[A big problem arises in that it is difficult to control the pressure. Shortening the channel is unavoidable in order to improve FET characteristics, but the shorter the channel, the lower the parasitic resistance. At present, it is very difficult to reduce both the parasitic resistance and the short channel effect using the method of forming the n+ layer by ion implantation.

As one solution to the above problems, a method of providing an n+ layer as a crystal layer on the substrate surface that will become the source/drain region has not been considered.

Figure 3 shows a schematic cross-sectional view of such a transistor, in which 1 is a semi-insulating substrate, 2 is an active layer, 3 is a gate electrode, 34 is an n+ crystal layer, 26 is an insulating film between the eyebrows, and 25 is a source. A drain ohmic electrode 11 is a source/drain electrode wiring.

Regarding the method of forming the n+ crystal layer 34, several crystal growth methods are well known, but the characteristics of the n1 crystal layer 34 are greatly influenced by the treatment conditions of the crystal surface where growth begins, and at present, none of the methods are satisfactory. No results have been obtained. That is, this n+
Although the formation of crystal N34 can be completed during FET manufacturing, in this case, the crystal growth starting surface is subjected to various treatments that are unacceptable for FET manufacturing, and in reality, n1
The crystal layer does not exhibit the same characteristics as when formed on an untreated crystal surface, and transistors manufactured by forming an N4'' crystal layer have not been able to achieve a satisfactory reduction in parasitic resistance. In the method of forming an n+ crystal layer, a high-quality n
+ It is necessary to establish a manufacturing method that can form a crystal layer. On this n+ crystal layer, it is necessary to deposit an ohmic metal and form an ohmic electrode using an alloy in order to manufacture the FET. It is possible to achieve a reduction in resistance by reducing parasitic resistance and therefore reducing the resistance of FETs.
This is essential for improving performance. The high quality n+ mentioned above
Providing a crystal layer and further providing an ohmic electrode with low contact resistance on the crystal layer in close proximity to the gate electrode is essential for manufacturing high-performance FETs, but this is a manufacturing method that can satisfy all of these requirements. has not been developed at present and is being explored.

SUMMARY OF THE INVENTION In consideration of the above points, an object of the present invention is to provide a method for manufacturing a semiconductor device including a compound semiconductor field effect transistor in which short channel effects are suppressed and parasitic resistance can be reduced.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the method of manufacturing a semiconductor device including a compound semiconductor field effect transistor provided by the present invention includes a step of forming an insulating sidewall on a side surface of a gate electrode. and a step of forming a high conductivity crystal layer having the same conductivity type as the active layer on the surface of the compound semiconductor in a region to become a source/drain portion separated from the gate electrode by the side wall;
forming a thin film of a group Ⅰ element on the high conductivity crystal layer; and adding an impurity, a compound semiconductor constituent element, or an inert element having the same conductivity type as the active layer to the high conductivity crystal layer and the active layer. The present invention is characterized in that a step of injecting the group (I) element from the surface of the thin film to a depth that passes through the interface and heat treatment, and a step of depositing an ohmic contact constituent material on the thin film of the group (I) and forming an alloy are sequentially performed.

(Function) The present invention provides an insulating side wall on the side surface of the gate electrode, and forms a high conductivity crystal layer having the same conductivity type as the active layer on the region separated by the side wall that will become the source/drain layer. Furthermore, a high conductivity crystal layer is formed by depositing a thin film of a group Ⅰ element and, for example, implanting an impurity having the same conductivity type as the active layer so as to pass through the interface between the high conductivity crystal layer and the substrate active layer. This produces a mixing effect at the interface between the substrate active layer and the group III element thin film and the high conductivity crystal layer, which maintains the high conductivity of the well-designed high conductivity crystal and also reduces the contact. The key point is to make it possible to form resistive ohmic contacts, and it is based on new experimental results that confirm that this is possible.

(Example) The present invention will be explained in more detail with reference to Examples below. FIGS. 1(a) to (c) show an embodiment of the present invention.
*aa t'', 6!'co 4'J't'4KmW
'AJ! : h 5 >Cross-sectional views of semi-finished products of ZISTA are shown in order of process. First, the formation of the structure shown in FIG. 1(a) will be explained. Si ions are applied 2X to an anti-insulating GaAs substrate 1 with an ion energy of 60 KeV using a resist as a mask.
10"Crl+-" is implanted to form active layer region 2. After removing the resist, the IiW film was removed by dry etching using a photoresist with a U3 pattern formed by depositing 5,000 TiW films as a gate electrode material by sputtering as a mask.
Gate electrode 3 is formed. Next, a silicon oxide film is formed on the entire surface of the sample to a thickness of 1,500 mm, and the silicon oxide film is etched to become source/drain regions using a parallel plate dry etching device and an anisotropic etching technique using CF4 gas. The GaAs surface is exposed and the silicon oxide film sidewalls 4 are left on the side surfaces of the gate electrode 3.

Next is the 11th f! The formation of the structure of J(b) will be explained. A GaAs crystal film 5 was grown to a thickness of 2000 nm over the entire surface of the exposed GaAs surface using a molecular beam crystal growth method to form a single crystal film. At that time, the electron concentration of the GaAs is I
Si was doped so that X 10 "cm-".

Subsequently, a Ge thin film 6 having a thickness of 800 nm was formed on the entire surface, and Si ions were heated at 300 KeV and 1×IQ”cTrI−.
A 5-ift film of 2000 mm was formed on the entire surface under the conditions of 2. Heat treatment was performed at SOO°C in a gas atmosphere for 20 minutes. Then, photoresist 8 was applied to the entire surface, and the resist was softened by baking at 180° C., so that the step of the resist film covering the gate electrode step was smoothed.

The structure shown in FIG. 1(c) is formed as follows. The entire surface is etched using an ion milling device to remove the resist 8, Ni thin film 7, Ge'f# film 6 and GaA on the gate electrode 3.
The S film 5 was removed, the resist remaining on the wafer was removed, and an alloying process was performed for 600"C520 minutes in an H gas atmosphere to form source/drain electrodes 9. Next, a silicon oxide film was formed as an interlayer film. 10 was deposited to a thickness of 3,000 yen, and the silicon oxide film was removed from the source/drain electrode and gate electrode extraction portions using the patterned resist as a mask.After the resist was further removed, Ti was deposited on the entire surface.
A -Pt-Au film is formed and patterned using an ion milling device to form one source/drain electrode wiring, thereby completing the GaAs FET shown in the figure.

In addition to the FET (A) according to the method of this embodiment described above, for comparison, an FET (B) was prepared that was manufactured without performing the Si ion implantation step after forming the Ge thin film. Gate length 0.
The threshold voltage, mutual conductance, and source resistance of 120 FE's having lengths of 6, 1, and 2.4 m were measured, and their average values were determined. The results are shown in Table 1. Gate length for both FETs (A) and (B) is 0.6 to 1-
A threshold voltage equivalent to I/T was obtained, and the short channel effect was suppressed by providing the high conductivity crystal layer. In the FET (A), the source resistance was reduced due to the effect of implanting Si ions through the Ge thin film, and a high mutual conductance value was obtained, confirming the effects of this example.

In the embodiments described above, examples using Si ions have been shown, but in addition to Si, dopants such as S, Sn, Te, Ga or As, and Ne, A are also used.
Similar effects were confirmed for inert elements such as r and Kr.

Although the case using GaAs has been described above, it is clear that the present invention can also be applied to field effect transistors using other compound semiconductors.

(Effects of the Invention) According to the present invention, as explained above, the short channel effect is suppressed, and the parasitic resistance is reduced by 1.
ll'';&(he*'f'!1KtJ'i':@:!E
)−? >') x 'l ** A method for manufacturing a semiconductor device can be provided.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) are schematic cross-sectional views showing semi-finished products of field effect transistors manufactured by the method of the present invention in the order of manufacturing steps, and FIGS. It is a schematic cross-sectional view. Representative Patent Attorney Shinsuke Honjo Figure 1 Figure 2 GaAs 1f Socket Figure 3

Claims (1)

[Claims] A step of forming an insulating sidewall on the side surface of the gate electrode, and a high conductivity crystal layer having the same conductivity type as the active layer on the surface of the compound semiconductor in a region that is to become a source/drain region separated from the gate electrode by the sidewall. a step of forming a group IV element thin film on the high conductivity crystal layer; and a step of forming a group IV element thin film on the high conductivity crystal layer; and sequentially performing a step of injecting the group IV element from the surface of the group IV element thin film to a depth that passes through the interface of the active layer and heat treating it, and a step of depositing an ohmic contact constituent material on the group IV element thin film and forming an alloy. A method for manufacturing a semiconductor device including a compound semiconductor field effect transistor, characterized by: