JPH05304172A - Manufacture of compound semiconductor device - Google Patents

Abstract

PURPOSE:To provide the manufacture of a compound semiconductor device, in which the concentration of stress at the time of annealing at the end of a gate electrode composed of a high melting-point metal is prevented and regions having high carrier concentration by self-alignment can be formed at both ends of the gate electrode for lowering source-drain resistance. CONSTITUTION:The etching of WSi 3 for forming a gate electrode 7 is stopped halfway, regions 6 having high carrier concentration are shaped on both sides of the gate electrode 7 through ion implantation and annealed, and the whole surface of WSi 3 is etched, thus completing the formation of the gate electrode 7. Accordingly, no stress is applied at the end of the gate electrode at the time of annealing, thus preventing the increase of gate leakage currents and the lowering of gate breakdown strength due to the generation of a point defect and a line defect in a GaAs surface at the end of the gate electrode. Maximum carrier concentration is lowered, and distribution is not spread wholly, thus preventing the reduction of transconductance (gm) and a K value in FET characteristics.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device, and more particularly to a field effect transistor of a III-V group compound semiconductor such as GaAs (hereinafter referred to as MES-F).
ET).

[0002]

2. Description of the Related Art In recent years, MES-FETs using high-speed III-V group semiconductors such as GaAs have been actively developed. In a GaAs MES-FET, when an electrically active layer is formed by ion implantation and subsequent annealing, a gate metal made of a refractory metal is formed in order to reduce the source / drain resistance, and then the gate metal is used as a mask for the gate metal. There is a method of forming self-aligned regions having a high carrier concentration on both sides of.

A conventional method of manufacturing this GaAs MESFET will be described with reference to FIG. First, as shown in FIG. 4A, selective ion implantation of Si ⁺ is performed on a semi-insulating GaAs substrate 61 to form a first n-type implantation region 62, and WSi 63 made of a refractory metal is sputtered on the entire surface. 200
Then, a mask 64 made of Al for processing into a gate metal is formed.

Next, WSi63 is formed by using Al64 as a mask.
By (b) of the same figure by reactive ion etching (RIE).
After processing the gate electrode 68 shown in FIG. 6A, Al 64 is removed by hydrochloric acid, and selective ion implantation of Si ⁺ is performed using the gate electrode 68 as a mask to form the second n-type implantation region 65 in the gate electrode 6.
8 is formed in self alignment. Further, as shown in FIG. 3C, an n ⁺ type implantation region (67) for obtaining ohmic contact is also formed by the selective ion implantation of Si ⁺ .

After that, as shown in FIG.
Annealed film 66 of ₂ is formed on the entire surface, and 820 ° C.
Annealing is performed for 20 minutes to electrically activate the implanted Si ⁺ . Finally, the annealed film 66 is removed, and the source electrode 69 and the drain electrode 70 shown in FIG. 6E are simultaneously formed by the vapor deposition / lift-off method, and heat treatment is performed at 450 ° C. for 3 minutes to obtain ohmic contact.

[0006]

However, in the above-described conventional manufacturing method, when the gate electrode is annealed after the formation, stress is generated due to the difference in thermal expansion coefficient between the gate electrode material and the GaAs substrate. The stress becomes particularly large at the end of the gate electrode, and point defects and line defects occur on the GaAs surface at the end of the gate electrode, increasing the gate leak current and degrading the gate breakdown voltage.

Further, due to the stress at the edge of the gate electrode, GaAs
It also affects the distribution of ions implanted in the substrate 61.
In FIG. 5, Si ⁺ + was implanted at 15 KeV under the condition of 8 × 10 ¹² cm ⁻² , and after depositing the refractory metal WSi, 100 ×
Shows a comparison of the carrier profile of WSi under each size when subjected to annealing and machining to a size of 100 [mu] m ² and 1 × 100μm ^2. Area is 1 x 100
In the case of WSi of μm ² , it corresponds to the gate electrode, but the maximum carrier concentration is lower than that in the case of an area of 100 × 100 μm ² , and the distribution is broadened overall. As a result, important FET characteristics such as transconductance (gm) and K
There was also a problem that the value became low.

Therefore, an object of the present invention is to prevent the stress during annealing from concentrating on the end of the gate electrode of refractory metal, and to reduce the source / drain resistance, the carrier concentration of the self-alignment at both ends of the gate electrode is reduced. It is an object of the present invention to provide a method for manufacturing a compound semiconductor device capable of forming a high region.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a compound semiconductor device, wherein a refractory metal to be a gate electrode is formed on the entire surface, processing of the gate electrode is stopped midway, and both sides of the gate electrode are formed. The method is characterized by including the steps of performing ion implantation, annealing, and then processing the gate electrode to the end.

A method for manufacturing a compound semiconductor device according to a second aspect is the method for manufacturing a compound semiconductor device according to the first aspect, in which the refractory metal film is formed of a mixed crystal containing at least tungsten and silicon and has a high melting point. When the metal film is selectively etched to be thin, the thin film thickness is 20
It is set to be nm or more. In the method of manufacturing a compound semiconductor device according to claim 3, after forming a refractory metal to be a gate electrode on the entire surface, a mask for processing the gate electrode made of an insulating film is formed, and ion implantation is performed on both sides of the gate electrode. The method is characterized by including a step of processing the gate electrode after performing and annealing.

According to a fourth aspect of the present invention, in the method of manufacturing a compound semiconductor, after forming a first refractory metal to be a gate electrode on the entire surface, a second refractory metal is formed by lift-off as a mask for processing the gate electrode. .. After that, the method is characterized by including a step of forming the gate electrode into a two-layer structure by performing ion implantation and annealing on both sides of the gate electrode and then processing the gate electrode.

[0012]

According to the structures of claims 1, 3, and 4, when annealing is performed, the entire surface of the compound semiconductor substrate is covered with a refractory metal serving as a gate electrode. Since the stress is not extremely applied, it is possible to prevent point defects and line defects from occurring on the GaAs surface at the end of the gate electrode, thereby increasing the gate leakage current and deteriorating the gate breakdown voltage. Further, since the source / drain resistance is reduced, it becomes possible to form regions having high carrier concentration by self-alignment at both ends of the gate electrode.

According to the structure of claim 2, when the film thickness of the refractory metal film made of a mixed crystal containing tungsten and silicon is set to 20 nm or more, the carrier concentration under the gate electrode at zero bias is increased. It becomes a high concentration.

[0014]

Embodiments of the method of manufacturing a compound semiconductor device according to the present invention will be described below with reference to the drawings. [First Embodiment] A first embodiment of the present invention will be described with reference to FIG.

In this GaAs MES-FET manufacturing method, first, as in the conventional example, as shown in FIG. 1A, the first n-type implantation region 2, the WSi 3 having a thickness of 300 nm, and the gate electrode are processed. The mask 4 made of Al is formed. Next, as shown in FIG. 6B, the gate electrode is processed by RIE, but the rest of WSi is interrupted at a thickness of 40 nm, and Si ⁺ selective ion implantation is performed to perform the second n-type implantation region. 5 is formed.

Further, as shown in FIG. 1C, Al 4 is removed by hydrochloric acid, and an n ⁺ type implantation region 6 for obtaining ohmic contact by selective ion implantation of Si ⁺ is formed. After that, the entire surface is etched by RIE and Ga
When stopped at the surface of the As surface, the shape becomes as shown in FIG. The gate electrode 7 becomes thinner than the initial thickness of 300 nm, but this is not a problem.

Finally, as in the conventional example, as shown in FIG. 3E, the source electrode 8 and the drain electrode 9 are simultaneously formed by the vapor deposition / lift-off method, and heat treatment is performed at 450 ° C. for 3 minutes to form an ohmic contact. Get in touch. In this manufacturing method, the carrier concentration at zero bias under the gate electrode 7 obtained by the CV method when annealing is performed by changing the film thickness of WSi3 left by etching shown in FIG. 6
Shown in. It can be seen that, when the remaining film thickness is 10 nm, the carrier concentration decreases, whereas when it exceeds 20 nm, a high carrier concentration is obtained.

According to the manufacturing method described above, when annealing is performed, the entire surface of the compound semiconductor substrate 1 is covered with the refractory metal WSi3 that will be the gate electrode 7, so that no stress is applied to the end of the gate electrode 7. Therefore, it is possible to prevent point defects and line defects from occurring on the GaAs surface at the end of the gate electrode 7 to increase the gate leak current and the gate breakdown voltage. Also, since the source / drain resistance is reduced,
A region having a high carrier concentration can be formed on both ends of the gate electrode 7 by self-alignment. [Second Embodiment] A second embodiment of the present invention will be described with reference to FIG.

In this GaAs MES-FET manufacturing method,
Is similar to the first embodiment, as shown in FIG.
First, the first n-type implantation region 12 and WSi having a thickness of 150 nm
13 is formed and SiO is formed on it.₂Membrane 14 and gate electrode
A mask 15 made of Al for processing is formed.
Next, as shown in FIG._Four+ H₂By gas
By RIE ₂The film 14 is etched and S
i⁺Selective ion implantation of the second n-type implantation region 16 is performed.
Form.

Further, as shown in FIG. (C), in order to obtain an ohmic contact by selective ion implantation of Si ⁺ n ⁺
Annealing is performed after forming the mold injection region 17 and removing Al15 with hydrochloric acid. After that, the WSi 13 is etched by RIE using CF ₄ + N ₂ gas to form the gate electrode 18 shown in FIG.

Finally, the SiO ₂ film on the gate electrode 18 is removed with hydrofluoric acid to remove the source electrode 1 as shown in FIG.
9. The drain electrode 20 is simultaneously formed by the vapor deposition / lift-off method, and heat treatment is performed at 450 ° C. for 3 minutes to obtain ohmic contact. According to the above-mentioned manufacturing method, when annealing is performed, the entire surface of the compound semiconductor substrate 11 is covered with the refractory metal WSi 13 that will be the gate electrode 18,
Since no stress is applied to the end of the gate electrode 18, there is no possibility that point defects or line defects occur on the GaAs surface at the end of the gate electrode 18 to increase the gate leak current or deteriorate the gate breakdown voltage. Further, since the source / drain resistance is lowered, it is possible to form regions having a high carrier concentration on both ends of the gate electrode 18 by self-alignment. [Third Embodiment] A third embodiment of the present invention will be described with reference to FIG.

In this GaAs MES-FET manufacturing method, as in the first and second embodiments, as shown in FIG. 3A, the first n-type implantation region 42 and the first refractory metal are formed. As a second refractory metal, WSi43 having a thickness of 150 nm is formed as a second refractory metal and photolithography is performed.
5 is vapor-deposited. Next, as shown in FIG. 6B, lift-off is performed and selective ion implantation of Si ⁺ is performed to form a second n-type implantation region 46.

Further, as shown in FIG. 3C, the n ⁺ -type implantation region 47 for obtaining ohmic contact is also made of Si ^+.
After forming by selective ion implantation of, annealing is performed. After that, the WSi was etched by RIE, and the same figure (d)
A gate electrode 48 having a two-layer structure shown in is formed. Finally, as shown in FIG. 7E, the source electrode 49 and the drain electrode 50 are simultaneously formed by the vapor deposition / lift-off method to form 450.
Heat treatment is performed at ℃ for 3 minutes to obtain ohmic contact.

According to the above manufacturing method, the surface of the compound semiconductor substrate 41 is covered with the gate electrode 48 when annealing is performed.
Since the entire surface is covered with the refractory metal WSi43 that becomes a stress, stress is not applied to the end of the gate electrode 48, so that a point defect or a line defect occurs on the GaAs surface at the end of the gate electrode 48 to increase the gate leakage current. The gate breakdown voltage does not deteriorate. Further, since the source / drain resistance is lowered, it is possible to form regions having high carrier concentration by self-alignment at both ends of the gate electrode 48.

[0025]

According to the method of manufacturing a compound semiconductor device of the present invention, stress is not applied to the end of the gate electrode during annealing, so that point defects or line defects occur on the GaAs surface at the end of the gate electrode, and the gate leakage current It is possible to prevent the increase and the deterioration of the gate breakdown voltage. Also, since the maximum carrier concentration does not decrease and the distribution does not broaden overall, the mutual conductance (g
m) and K value will not decrease.

[Brief description of drawings]

1A to 1D are cross-sectional views in order of the steps, showing a method for manufacturing a compound semiconductor device in a first embodiment of the invention.

2A to 2D are cross-sectional views in order of the steps, showing a method for manufacturing a compound semiconductor device in a second example.

3A to 3D are sectional views in order of the processes, showing the method for manufacturing the compound semiconductor device according to the third embodiment.

4A to 4C are cross-sectional views in order of the processes, showing the conventional method for manufacturing a compound semiconductor device.

FIG. 5 is a diagram showing a comparison of carrier profiles obtained by the CV method for WSi of different sizes.

[FIG. 6] By changing the film thickness of WSi left by etching,
It is a figure which shows the carrier density in the zero bias under the gate electrode calculated | required by CV method at the time of annealing.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 first n-type implantation region 3 WSi 4 Al 5 second n-type implantation region 6 n ⁺ type implantation region 7 gate electrode 8 source electrode 9 drain electrode 11 semi-insulating GaAs substrate 12 n-type Implantation region (1) 13 WSi 14 SiO ₂ 15 Al 16 Second n-type implantation region 17 n ⁺ type implantation region 18 Gate electrode 19 Source electrode 20 Drain electrode 41 Semi-insulating GaAs substrate 42 First n-type implantation region 43 WSi 44 Resist 45 W 46 Second n-type implantation region 47 n ⁺ type implantation region 48 Gate electrode 49 Source electrode 50 Drain electrode

Claims (4)

[Claims] 1. A step of forming an ion-implanted region to be an electrically active layer on a compound semiconductor substrate, and forming a refractory metal film on the entire surface to select the refractory metal film in a region other than a region to be a gate electrode. Etching and thinning, forming ion-implanted regions on both sides of the gate electrode, annealing for activating implanted ions, and etching the refractory metal film over the entire surface to form a gate electrode. And a step of exposing the surface of the compound semiconductor substrate other than the region to be formed. 2. The refractory metal film is a mixed crystal containing at least tungsten and silicon, and the thinned film is 20 nm or more in the step of selectively etching the refractory metal film to thin it. A method for manufacturing a compound semiconductor device. 3. A step of forming an ion-implanted region to be an electrically active layer on a compound semiconductor substrate, and a selective etching of the insulating film except a region to be a gate electrode by forming a refractory metal film and an insulating film on the entire surface. And a step of forming ion-implanted regions on both sides of the gate electrode, a step of annealing for activating the implanted ions, and a step of etching the refractory metal film using the insulating film as a mask to etch the gate electrode. And a step of forming a compound semiconductor device. 4. A step of forming an ion-implanted region to be an electrically active layer on a compound semiconductor substrate, a film made of a first refractory metal is formed on the entire surface, and a film made of a second refractory metal is formed thereon. Forming a gate electrode, forming ion-implanted regions on both sides of the gate electrode, annealing for activating the implanted ions, and using the second refractory metal as a mask And a step of etching the refractory metal film to form a gate electrode.