JPH06302621A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To form a predetermined asymmetrical impurity concentration gradient on opposite sides of a gate electrode by additionally providing a process where an insulating layer is formed only on one side of the gate electrode for impurity doping. CONSTITUTION:A photoresist 2 is applied on the surface of a semi-insulating GaAs substrate 1 and a window is formed in a predetermined region, and thereafter first impurity ion implantation is performed to form a low concentration impurity layer 3. A SiO2 film 4 is formed on the surface from which the photoresist 2 is removed and a photoresist 5 is formed on a drain electrode formation region located thereon. The SiO2 film 4 in a region where the photoresist 5 is not existent is removed by making use of anisotropic RIE. A high melting point metal 6 is vapor-deposited on opposite sides of a remaining SiO2 film 4 and second impurity ion implantation is performed to form an intermediate concentration impurity layer 8. Further, as SiN film is formed and third ion implantation is performed to form two stage and one stage impurity concentration gradients on the sides of the electrode formation regions of a drain and a source. Thus, concentration distribution is strictly controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a field effect transistor aiming at high performance.

[0002]

2. Description of the Related Art In recent years, field effect transistors have been improved and improved in various characteristics in order to speed up operation, reduce power consumption, reduce noise, and increase efficiency. Of these, the maximum drain current, transconductance, and reverse gate-drain withstand voltage are important for achieving high efficiency. By reducing the source resistance and ensuring a high drain voltage, high efficiency can be achieved. Trying to make it happen.

FIG. 6 is a sectional structural view showing a conventional method for manufacturing a semiconductor device, and a field effect transistor using a GaAs Schottky gate electrode is manufactured by a self-alignment process which is often used because alignment is unnecessary. The case will be described. First, the active layer is formed on the semi-insulating substrate 41.
After forming 42, a gate electrode 43 made of a heat resistant metal such as a W alloy is formed (FIG. 6A). Then, impurity ions are implanted into the source / drain regions using the gate electrode 43 as a mask, and further heat treatment is performed to form n ⁺ layers 44 and 45 (FIG. 6B). Next, the source electrode 46 and the drain electrode 47 are formed on the n ⁺ layers 44 and 45, respectively (FIG. 6C).

In the field effect transistor obtained by such a method, since the n ⁺ layer 45 and the gate electrode 43 are in contact with each other, the source resistance is reduced to some extent, but the reverse withstand voltage between the gate and the drain is low. There is a drawback that. Therefore, as shown in FIG. 7, a structure in which the n ⁺ layers 44 and 45 are separated from the gate electrode 43 by a predetermined distance is used. In this case, however, the reverse withstand voltage between the gate and the drain is opposite to that described above. Although a desired amount can be obtained, there is a drawback that the source resistance is large.

As described above, it has been very difficult to realize high efficiency in a field effect transistor in which the impurity layer structures on both sides of the gate electrode are symmetrical. Therefore, as described above, as a field effect transistor having a high reverse withstand voltage between the gate and the drain and a small source resistance, a field effect transistor having a different impurity layer structure on the drain electrode side and the source electrode side of the gate electrode has been proposed. The distance from the gate electrode to the n ⁺ layer below the source electrode,
In some cases, the distance to the n ⁺ layer under the drain electrode is different. As the manufacturing method, an oblique injection method has been proposed in which impurities are injected obliquely (Technical report of IEICE, Vol.86, No.46, ED86-9, pp23-28). In this oblique implantation method, a low-concentration impurity layer under the gate electrode is formed, a T-shaped gate electrode is further formed, and then ion implantation is performed from the source region side at a predetermined angle. Then, on the source electrode side, the n ⁺ layer is formed by injecting to a position close to the gate electrode, but on the drain electrode side, the n ⁺ layer is blocked and is injected only to a position far from the end of the inflated part. Is not done. Wherein the distance from the gate electrode to the n ⁺ layer under the source electrode, under the drain electrode n ⁺
The distance to the layer has a great influence on the above-described characteristics of the field-effect transistor, and thus must be strictly controlled.
When a field effect transistor having different impurity layer structures on both sides of the gate electrode is controlled by a method other than the oblique implantation method as described above, a large number of masks are required, and the number of manufacturing steps is reduced. It greatly increases and is inconvenient for practical use.

[0006]

However, when mass production is actually carried out by the oblique implantation method, since the implantation angle for each field effect transistor is different by swinging the injection port, the n ⁺ layer is formed in all field effect transistors. It is very difficult to strictly control the region, and there is a problem that the characteristics among the field effect transistors vary. The present invention has been made in view of such circumstances, and by adding a step of forming an insulating layer only on one side of a gate electrode and injecting impurities, both sides of the gate electrode can be manufactured with the least number of steps. Another object of the present invention is to provide a semiconductor device manufacturing method capable of forming a required asymmetric impurity concentration gradient.

[0007]

According to the method of manufacturing a semiconductor device of the present invention, impurities are implanted into a substrate to form a low-concentration impurity layer, a gate electrode is formed, and the gate electrode is used as a mask. In a method of manufacturing a semiconductor device, in which impurities are injected to form a high-concentration impurity layer, and then a source electrode and a drain electrode are formed, an insulating layer is formed in a source region after forming the low-concentration impurity layer. Formed,
A gate electrode is formed so as to be in contact with a side portion of the insulating layer, impurities are injected by using the insulating layer and the gate electrode as a mask to form an intermediate concentration impurity layer, and an impurity concentration gradient portion obtained by this and It is characterized in that an impurity is further injected into a region other than directly under the gate electrode to form a higher concentration impurity layer, and a source electrode and a drain electrode are formed in the source region and the drain region, respectively.

[0008]

According to the present invention, the impurity concentration distribution on both sides of the gate electrode can be controlled separately by adding a step of forming an insulating layer only on one side of the gate electrode and implanting impurities. Becomes The concentration distribution can be strictly controlled by making the thickness of the insulating layer, the number of times of formation, and the number of times of implantation of impurities different. Thereby, for example, it is possible to manufacture a field effect transistor having a low source resistance and a high drain breakdown voltage, and it is possible to improve the performance of a semiconductor device.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. 1, FIG. 2 and FIG. 3 are sectional structural views showing a first embodiment of the method for manufacturing a semiconductor device according to the present invention. First, a photoresist (for example, OEBR manufactured by Tokyo Ohka Co., Ltd.) 2 is coated on the surface of a semi-insulating GaAs substrate 1, and a window is opened in a required area, and then ₂₈ S which is an impurity is applied.
The first ion implantation of i ⁺ is performed to perform the low concentration impurity layer 3
Are formed (FIG. 1 (a)). This injection condition is acceleration voltage 40K
The eV and dose amount are 5 × 10 ¹² cm ^-2 .

Thereafter, a SiO ₂ (silicon oxide) film 4 is formed on the surface from which the remaining photoresist 2 has been removed by a plasma CVD method in an amount of about 4000 Å, and a photoresist 5 is formed in a required region thereon. Then, the SiO ₂ film 4 in the region where the photoresist 5 does not exist is removed by anisotropic reactive ion etching (RIE) (FIG. 1B).

Then, on the surface from which the photoresist 5 has been removed, the Schottky junction with the GaAs substrate is possible, WS
A refractory metal 6 such as iN (tungsten silicon nitride) or WN (tungsten nitride) is vapor-deposited by a sputtering method (FIG. 1C), and only the both sides of the SiO ₂ film 4 of the refractory metal 6 are left, The other part is removed by RIE (FIG. 1 (d)). Next, a photoresist 7 is formed on both outer side regions of the impurity layer 3, and then a second ion implantation is performed to form an intermediate concentration impurity layer 8 in a region between the photoresist 7 and the refractory metal 6 ( Figure 1 (e)). This injection condition is the acceleration voltage
It is 55 KeV and the dose amount is 2 × 10 ¹² cm ^-2 .

Further, the SiO ₂ film 4 and the photoresist 7
A SiN film 20 of about 2000 liters is formed on the surface from which the metal has been removed by the plasma CVD method (FIG. 2 (f)), and other portions are removed by RIE, leaving only the portion in contact with the outside of the refractory metal 6 (FIG. 2 (f)). (g)). Further, the SiO ₂ film 4 is removed to remove the impurity layer 8
After forming the photoresist 21 on both outer side regions of the substrate, a third ion implantation is performed to form a high concentration impurity layer in the region where the refractory metal 6, SiN film 20 and the photoresist 21 do not exist.
22 is formed (FIG. 2 (h)). This injection condition is 90 V
KeV, dose amount 5 × 10 ¹³ cm ^-2 . Then, after removing the photoresist 21, a SiN film 23 is formed on the entire surface by a plasma CVD method (FIG. 2 (i)), and heat treatment is performed at 850 ° C. for 5 seconds to activate the implanted impurities.

Then, a photoresist 24 is applied and formed on the entire surface, the SiN film 23 in the source / drain regions and the photoresist 24 are removed, and then an AuGe / Ni layer 25 is vapor-deposited (FIG. 3 (j)), followed by a lift-off method. Then, the photoresist 24 and the AuGe / Ni layer 25 formed thereon are removed. Then, heat treatment is performed at 450 ° C. for 120 seconds in an H ₂ atmosphere to form both ohmic electrodes of the source electrode 27 and the drain electrode 26 (FIG. 3 (k)). According to the method of the present invention as described above, a two-step concentration gradient is formed on the drain electrode 26 side of the gate electrode and a one-step concentration gradient is formed on the source electrode 27 side, so that the desired reverse gate-drain withstand voltage can be obtained, and A field effect transistor having a small source resistance can be manufactured.

FIGS. 4 and 5 are sectional structural views showing a second embodiment of the method of the present invention. Since the steps shown in FIGS. 1 (a) to 1 (e) are the same, impurities of medium concentration are formed. Only the steps after forming layer 8 are shown. After removing the photoresist 7 shown in FIG. 1 (e), the SiN film 30 is removed to about 4000 by plasma CVD.
Å Formed (FIG. 4 (f)), leaving only the portion in contact with the outside of the refractory metal 6 and removing the other portion by RIE (FIG. 4).
(g)). Further, the SiO ₂ film 4 is removed, and a photoresist 31 is formed on both outer regions of the impurity layer 8. After that, a third ion implantation is performed to remove the refractory metal 6, SiN film 30 and the photoresist 31 from the region. Second impurity layer of medium concentration
32 is formed (FIG. 4 (h)). This injection condition is the acceleration voltage 70
KeV, dose amount 4 × 10 ¹² cm ^-2 .

After removing the photoresist 31, a SiN film 33 is formed on the entire surface by plasma CVD to a thickness of about 3000 liters. Then, photoresist is applied to both outer regions of the impurity layer 32.
After forming the 34, the fourth ion implantation is performed to form the high-concentration impurity layer 35 in the refractory metal 6, the SiN film 30, both sides thereof and the region where the photoresist 34 does not exist (see FIG. i)). The implantation conditions are an acceleration voltage of 90 KeV and a dose amount of 5 × 10 ¹³ cm ^-2 . Then, after removing the photoresist 34, at 850 ° C. to activate the implanted impurities,
Heat treatment is performed for 5 seconds. Then, a photoresist 36 is applied and formed on the entire surface, and the SiN film 33 and the photoresist 36 in the source / drain regions are removed. Then AuGe / Ni
A layer 37 is vapor-deposited (FIG. 5 (j)), and the photoresist 36 and the AuGe / Ni layer 37 formed thereon are removed by a lift-off method. Then, by performing heat treatment at 450 ° C. for 120 seconds in an H ₂ atmosphere, the source electrode 39 and the drain electrode 38
Both ohmic electrodes are formed (FIG. 5 (k)). In this embodiment, a three-step concentration gradient is formed on the drain electrode 38 side of the gate electrode and a two-step concentration gradient is formed on the source electrode 39 side.
A desired amount of reverse withstand voltage between drains can be obtained, and a field effect transistor having a small source resistance can be manufactured.

[0016]

As described above, in the method of manufacturing a semiconductor device according to the present invention, by adding a step of forming an insulating layer only on one side of the gate electrode and implanting impurities, impurities on both sides of the gate electrode are added. The layers can easily be made to have the required asymmetric structure. By varying the thickness of the insulating layer, the number of times of formation, and the number of times of implantation of impurities,
Since the desired concentration distribution can be obtained, the reverse withstand voltage between the gate and the drain and the source resistance can be set to required values, and a high-performance semiconductor device can be manufactured with relatively few manufacturing steps. Etc., the present invention has excellent effects.

[Brief description of drawings]

FIG. 1 is a sectional structural view showing a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a sectional structural view showing a first embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is a sectional structural view showing a first embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 4 is a sectional structural view showing a second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 5 is a sectional structural view showing a second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 6 is a sectional structural view showing a conventional method for manufacturing a semiconductor device.

FIG. 7 is a cross-sectional structure diagram showing a conventional semiconductor device.

[Explanation of symbols]

1 substrate 2, 5, 7, 21, 24 photoresist 3, 8, 22, impurity layer 4 SiO ₂ film 6 refractory metal 20 SiN film 25 AuGe / Ni film 27 source electrode 26 drain electrode

Claims (1)

[Claims] 1. An impurity is implanted into a substrate to form a low-concentration impurity layer, a gate electrode is formed, and then the gate electrode is used as a mask to further implant impurities to form a high-concentration impurity layer. In a method of manufacturing a semiconductor device by forming a source electrode and a drain electrode, an insulating layer is formed in a source region after forming the low concentration impurity layer,
A gate electrode is formed so as to be in contact with a side portion of the insulating layer, impurities are injected by using the insulating layer and the gate electrode as a mask to form an intermediate concentration impurity layer, and an impurity concentration gradient portion obtained by this and A method of manufacturing a semiconductor device, comprising further implanting an impurity into a region except directly under the gate electrode to form a higher concentration impurity layer, and forming a source electrode and a drain electrode in the source region and the drain region, respectively.