JPH0360118A - Formation of contact electrode - Google Patents

Abstract

PURPOSE:To make the thickness of growth of a second conductive layer uniform and to improve the uniformity of element characteristics by a process for forming a first conductive layer on the surface of a semiconductor substrate, a process for growing the second conductive layer on the surface of the first conductive layer and a process, in which a defect is generated in the second conductive layer by ion- implanting selectively to make a high resistance for isolation. CONSTITUTION:Si<+> ions are implanted into surface of a semi-insulating GaAs semiconductor substrate 1 to provide a channel layer 11, a gate electrode 12 consisting of a heat-resisting gate metal, WSi, is formed, Si<+> ions are implanted using the electrode 12 as a mask to provide a first conductive layer 12 and a heat treatment is performed in an AsH2-containing atmosphere to recover the crystallizability of an ion-implanted layer. Then, an SiO2 film is grown, a vertical dry working is performed to provide sidewalls 14 and a second conductive layer 3 is grown. After that, by providing source and drain electrodes 16 and 17 consisting of an ohmic metal, AuGeNi, on the layer 3, a contact electrode is connected to an intrinsic FET region directly under the electrode 12 and a MESFET is completed. Accordingly, as the layer 3 is grown on almost the whole surface excluding part of the electrode 12, the thickness of the layer 3 becomes very uniform.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of forming an electrode using vapor phase growth in a semiconductor device.

[Conventional technology]

In semiconductor devices, it is necessary to lead out electrodes from the intrinsic element region. Although it may be a diode or a bipolar transistor, here, a GaAs junction gate field effect transistor (hereinafter referred to as MESFET) will be explained as an example.

As an example of this MESFET, JP-A-62-1237
The manufacturing method disclosed in Publication No. 75 will be explained. Second
Figures ω to (a) are diagrams for explaining this manufacturing method, and are cross-sectional views of the element in main steps. In FIG. 2(a), a channel layer 1 is formed by selectively implanting ions into a semi-insulating GaAs substrate (hereinafter referred to as a semiconductor substrate) l.
1, and a gate electrode 12 made of heat-resistant metal WSi is provided on the surface of the gate electrode 12.
A first conductive layer 2 is formed by selectively implanting ions using the gate electrode 12 as a mask and performing heat treatment. Next, as shown in FIG. 2(b), a coating film 13 of Sin is grown and selectively vertically dry etched to form openings. At this time, side walls 14 are formed beside the gate electrode 12. A second conductive layer 3 is selectively grown in this opening.

Thereafter, as shown in FIG. 2(Q), the Sin coating film 13 is removed. In FIG. 2(a), a source electrode 16 and a drain electrode made of ohmic metal AuGeNi are placed on the second conductive layer 3! 7 to complete the MESFET.

The feature of this MESFET is that there is a first conductive layer 2 with a low concentration in contact with the gate electrode 12, and by providing a second conductive layer 3 with a high concentration on top of this, the substrate leakage current flowing directly under the channel layer 11 is reduced. and the short channel effect is reduced.

For the growth of the highly concentrated second conductive layer 3, for example, trimethyl gallium (TMG), arsine (AsH, ) and H
Selective growth is used by an organometallic method using a mixed gas consisting of a raw material gas and HS gas as a dopant.

[Problems to be Solved by the Invention] According to the above manufacturing method, in the selective growth of the second conductive layer, if the ratio of openings due to the area and density of the openings is small, the growth thickness becomes thick. There is pattern dependence, and although variations in the growth thickness tend to decrease when the growth atmosphere is reduced in pressure, there is a limit because the growth rate decreases.

Furthermore, when the second conductive layer is thin in the MESFET, the source series resistance increases and the mutual conductance gm decreases. On the other hand, if the second conductive layer is thick, the electric field concentration at the end of the drain becomes strong and the drain withstand voltage decreases, so it is necessary to reduce the variation in the growth thickness of the second conductive layer.

An object of the present invention is to provide a method for forming a contact electrode that solves this problem.

[Means to solve the problem]

In order to achieve the above object, the method for forming a contact electrode according to the present invention includes the steps of forming a first conductive layer on the surface of a semiconductor substrate, and growing a second conductive layer on the surface of the first conductive layer. and a step of selectively implanting ions to cause defects in the second conductive layer to increase the resistance and separate the defects.

[Example 1] Hereinafter, a method for forming a contact electrode according to the present invention will be described with reference to the drawings as an example in the case of a junction gate field effect transistor.

FIGS. 1(a) to 1(d) are diagrams for explaining one embodiment of the present invention, and are sectional views of elements in main manufacturing steps.

In FIG. 1(a), Si1 ions are deposited on the surface of a semi-insulating GaAs substrate (semiconductor substrate) 1 at an accelerating voltage of 30 KeV.
A channel layer 11 is formed by ion implantation over the entire surface with an implantation dose of 3.6×10"CII'l-", and a heat-resistant gate metal WS is formed.
A gate electrode 12 (thickness: 0.5 pm) of i is formed, and St+ ions are heated at 40 KeV using the gate electrode 12 as a mask.
5. The first conductive layer 2 was formed by ion implantation at OX 10'am-' and then heated at 830° C. for 15 min in an AsH atmosphere.
A heat treatment is performed for a minute to restore the crystallinity of the ion-implanted layer.

Next, as shown in FIG. 1(b), a SiO film is grown, vertical dry processing is performed to form side walls 14 (thickness: 0.3 pm), and second conductive layer 3 is grown to a thickness of 20 nm. The growth conditions at this time are trimethyl gallium (TMG): AsH.
,: l(, with a gas ratio of S=7:l:0.04, toot.

The reaction was carried out at a temperature of 620° C. under reduced pressure to 620° C. At this time, the second conductive layer 3 is not grown on the gate electrode 12 or the sidewalls 14. In FIG. 1(c), the device region is covered with a photoresist 15 (thickness: 3 lIm), and B+ is set at 1oOKeV.
, 5.times.10"an-" ion implantation is performed to generate defects and increase the resistance, thereby performing element isolation. After that, as shown in FIG. 1(a), the second conductive layer 3 remained as an element.
By providing a source electrode 16 and a drain electrode 17 made of ohmic metal AuGeNi on the top, the contact electrode is connected to the intrinsic FET region directly under the gate electrode, and the MESFE
Complete T.

According to the method of the present invention, since the second conductive layer 3 is grown over almost the entire surface except for a part of the gate electrode 12, the thickness of the second conductive layer 3 is extremely uniform, and the thickness is 200±20 nm (±10%) within the substrate. It was within range. However, when it was selectively provided using the conventional method, it varied greatly by about twice as much, from 170 to 320 nm.

The source resistance in the MESFET is 0.7 to 0.8Ω in the method of the present invention, whereas it is 0.6 to 0.8Ω in the conventional method.
The fluctuation range was large at 8Ω. On the other hand, the drain breakdown voltage is 6~
7V, but in the conventional method, the drain breakdown voltage sometimes dropped significantly to 4 to 7V.

Further, the second conductive layer 3 can be made to have a high resistance as long as defects occur;
In addition to B+, ions such as H", O", and N+ can be used.

[Effects of the Invention] As explained above, according to the method of forming a contact electrode of the present invention, the second conductive layer is grown almost over the entire surface, so that the growth thickness becomes uniform and the uniformity of device characteristics is improved. can be done.

[Brief explanation of drawings]

FIGS. 1(a) to 2 are cross-sectional views of the device in each main process for explaining the method of forming a contact electrode of the present invention, and FIG. 2(a)
) to (a) are device cross-sectional views of each main process for explaining a conventional method of forming a contact electrode.

Claims (1)

[Claims] (1) A step of forming a first conductive layer on the surface of the semiconductor substrate, a step of growing a second conductive layer on the surface of the first conductive layer, and a step of selectively implanting the second conductive layer. 1. A method for forming a contact electrode, comprising the steps of: creating a defect in a conductive layer, increasing the resistance, and separating the defect.