JPH0212875A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having a good surface protection insulating film by a method wherein a process in which ions are made to penetrate an AlxGa1-xAs film provided on an InP operating layer or a contact layer and are implanted in an InP substrate is provided. CONSTITUTION:When a semiconductor device using an InP layer as an operating layer or a contact layer is manufactured, a process in which ions are made to penetrate an AlxGa1-xAs film (provided that: 0<=x<=1) provided on the InP layer or the contact layer and are implanted in an InP substrate 1 is provided. For example, an ion implanted layer 2 is formed in an InP substrate 1 as an operating layer by ion-implanting Si in the substrate 1 and an AlGaAs film is grown as an insulating protective film 3. Then, a heat-resistance gate electrode 4 consisting of a WSi film is formed, and moreover, Si is made to penetrate the AlGaAs film 3 and are ion-implanted for forming ionimplanted layers 5 as contact layers. Then, an annealed protective film 6 consisting of PSG or the like is formed to perform an annealing, the film 6 is removed, and thereafter, lastly, source and drain electrodes 7 and 8 are formed to obtain a FET in a depletion mode.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a compound semiconductor device using InP as an active layer or a contact layer, and more specifically, to a method for manufacturing a compound semiconductor device using InP as an active layer or a contact layer. Regarding the manufacturing method.

(Prior art) MIS field effect transistor (F
As shown in FIG. 5, the basic structure of the ET) is that in the enhancement mode, an n-type contact layer 5 is formed by ion implantation into an InP substrate 1, and in the depletion mode, an n-type channel layer 2 is provided on this. , for example, itotsu (T
, Itoh) et al. at the International Electron Device Meeting (InternationalEle
ctron Device Meeting 1986
-P771), the current flowing between the source electrode 7 and the gate electrode 8 is controlled by the voltage applied to the gate electrode 33.

Conventionally, the active layer 2 is formed by ion implantation into a semi-insulating InP substrate.
The formation of the contact layer 5 consists of two steps: forming an ion implantation mask such as a photoresist with an opening at a predetermined position on the InP substrate, and then implanting desired ions; The process includes a step of covering the insulating film 53 and performing heat treatment at 700 to 800 DEG C. to form an active layer and a contact layer, or a step of implanting ions through the PSG film and performing heat treatment. Here, the insulating film such as PSG is coated on the InP substrate surface to prevent evaporation of P and In due to high temperature treatment.

(Problem to be Solved by the Invention) If ions are not implanted through the surface protection insulating film, impurities attached to the InP substrate surface will simultaneously enter the channel layer as impurities and affect the activation rate. Problems such as negative effects may arise. Even when ion implantation is performed through the surface protection insulating film, in the conventional structure, there are still many interface states at the interface between the insulating film such as PSG and InP, which are caused by P loss due to high-temperature annealing. When a high concentration of P is introduced to suppress the interface state, problems such as a decrease in the resistivity of the insulating film arise.

Furthermore, even when a PSG film is used, the InP surface deteriorates due to P loss when heat treated at temperatures exceeding 750°C. moreover,
Problems such as stress on the element arise due to the large difference in thermal expansion coefficient between the insulating film and InP.

An object of the present invention is to provide a compound semiconductor device using InP as an active layer, and to provide a semiconductor device having a particularly good surface protection insulating film and a method for manufacturing the same.

(Means for Solving the Problems) The present invention provides: (1) In a method of manufacturing a semiconductor device using InP as an active layer or a contact layer, AlXGa1-XAs provided on the InP active layer or contact layer is provided. film(
However, a method for manufacturing a semiconductor device (2) includes a step of implanting ions into InP through O≦X≦1.
) In a method of manufacturing a semiconductor device using InP as an active layer or a contact layer, a step of implanting ions into a portion that will become the active layer or a contact layer, and
This is a method for manufacturing a semiconductor device characterized by including a step of covering the P surface with an AlXGa1-XAs film (0≦X≦1) and heat-treating it.

(Function) In the present invention, the operation layer and contact layer of a FET having InP as an operation layer are formed by a step of ion-implanting n-type or p-type impurities through AlGaAs or GaAs as a surface protection insulating film, or It is characterized in that it is formed by performing a step of forming AlGaAs or GaAs as a surface protection insulating film after ion implantation, and then performing heat treatment to activate the ion implantation layer.

By using AlGaAs or GaAs as a surface protection insulating film and implanting desired impurities by penetrating it, it is possible to avoid contamination with impurities attached to the InP surface. Furthermore, it is possible to implant ions into the channel layer etc. with a shallow profile, and the process It is also simplified.

In addition, since AlGaAs or GaAs films are compounds of IILV group elements like InP, by growing AlGaAs or GaAs immediately after surface treatment of InP, a good interface can be obtained although the lattice constant is different, and by heat treatment, Also, In and P from the InP surface
The diffusion of the elements can be suppressed and a good channel layer or contact layer can be obtained. The surface is not InP
Since it is AlGaAs or GaAs, heat treatment at higher temperatures is also possible. Regarding the difference in thermal expansion coefficient, In
P and AlGaAs or GaAs are InP and PSG
much smaller than.

Another advantage is that InP and AlGaAs or GaAs can be easily selectively etched using a phosphoric acid etching solution.

(Example) Examples of the present invention will be described below with reference to FIGS. 1 to 4.

<Example 1> Figures 1(a) to (0) briefly show the manufacturing process of one of the embodiments according to the present invention. As shown in (a), ions are applied to a cleaned InP substrate 1 as an active layer. Injection return 2 to Si,
Dose amount 4X101 with implant energy 301ceV
It was formed by ion implantation of 2 cm-2. This was then coated with an insulating film and protective film 3 using the MBE method.
Ga1- Etch leaving the desired part.

Furthermore, as shown in (d), in order to form the ion implantation layer 5 as a contact layer, the gate metal is used as a mask and the implantation energy is 1001ceV and the dose [5X 1013c
m-2 Si ions are implanted through the AlGaAs. Next, a protective film 6 such as PSG is formed on this, and annealing is performed to form a structure as shown in (e). Since ion implantation is performed through the AlGaAs insulating film, impurities attached to the surface of the InP substrate do not simultaneously enter the channel layer as impurities and affect the activation rate. Here, AlGaAs and InP have good interfacial properties, and it is possible to perform high-temperature annealing while avoiding surface deterioration due to P removal from InP, etc.
No surface deterioration was observed even after annealing at temperatures exceeding °C. Since the difference in thermal expansion coefficients between AlGaAs and InP is small, problems such as stress on the element can also be solved. After removing the protective film 6, a window is finally opened to establish ohmic contact, and a source 7 and drain electrode 8 are formed to obtain a depletion mode FET as shown in (O).

<Example 2> Figures 1 (2a) to (2b) and (C) to (D) briefly show the manufacturing process of one of the embodiments according to the present invention. MBE as protective film 3
100 OA of GaAs is grown by the method to form a structure as shown in 2a). Next, in order to form an ion-implanted layer 2 as an operating color, the GaAs layer is penetrated from above as shown in (2b), and ions are implanted at an implantation energy of 30 keV.
Si is implanted at a dose of 4×1012 crrr2.

Since ion implantation is performed through the GaAs insulating film, the In
The impurities attached to the surface of the P substrate enter the channel layer as impurities at the same time as the ion implantation, and do not affect the activation rate. It was possible to obtain a good interface between GaAs and InP, and it was possible to suppress interface states caused by P loss due to high-temperature annealing, and no surface deterioration was observed even with annealing exceeding soo'c.

Since the difference in coefficient of thermal expansion between GaAs and InP is small, problems such as stress on the element can also be solved. Thereafter, the same steps as in Example 1 are performed to obtain a depletion mode FET.

<Example 3> FIGS. 2(a) to 2(e) briefly show one manufacturing process of an example according to the present invention. First cleaned InP substrate 1
As an insulating protective film 3 on top, Al
XAs (X=0.3) is grown to 100 OA and has a structure as shown in a). In addition, heat-resistant metal 4 as shown in (b)
3000A of WSi is formed, and etched by dry etching or the like, leaving a desired portion. Further, as shown in (e), in order to form the contact layer 5, Si ions are implanted through the AlGaAs at a dose of 5.times.10.sup.13 cm.sup.-2 at an implantation energy of 1001 ceV using the gate metal as a mask. Next, a protective film 6 such as PSG is formed on this, and annealing is performed as shown in (d). AlG
Since ion implantation is performed through the aAs insulating film, InP
Impurities adhering to the substrate surface no longer enter the channel layer as impurities during ion implantation and affect the activation rate. In addition, it is possible to obtain a good interface between AlGaAs and InP, and it is possible to suppress the interface states caused by P loss due to high-temperature annealing.
No surface deterioration was observed even after annealing at temperatures exceeding 0°C. Since the difference in thermal expansion coefficients between AlGaAs and InP is small, problems such as stress on the element can also be solved. After removing the protective film 6, a window is finally opened to establish ohmic contact, and a source 7 and drain electrode 8 are formed to obtain an enhanced mode FET as shown in FIG.

<Example 4> One manufacturing process of an example according to the present invention is briefly shown in FIGS. 3(a) to 3(d). As shown in (a), Si was implanted as the operating color 2 into a cleaned InP substrate 1 using the photoresist 31 as a mask, and the energy was 301 ceV.
Ion implantation is performed at a dose of i4×10 12 cm −2 . Furthermore, this photoresist is removed and a new photoresist is formed, and as shown in (b), using this as a mask, the implantation energy is 100 keV and the dose of i5×1013 am−2 is S.
A contact layer 5 is formed by ion-implanting i. Next, this photoresist is removed and MBE is used as an insulating protective film 3.
AlXGat −XAsCX = 0.3) by the method
After 00OA growth, a PSG film or the like is formed thereon as a surface protection film, and annealing is performed to form a structure as shown in C). Here, we were able to obtain a good interface between AlGaAs and InP, and it was possible to suppress the interface states caused by P loss due to high-temperature annealing, and no surface deterioration was observed even after annealing at temperatures exceeding 800°C. . AlGaAs and I
Since the difference in coefficient of thermal expansion between nP and nP is small, problems such as stress on the element can also be solved. After removing the protective film 6, a gate electrode 33 is formed, and finally a window is opened to make ohmic contact, a source 7 and a drain electrode 8 are formed (to form a depletion mode FET as shown in O). obtain.

<Example 5> FIGS. 4(a) to 4(d) briefly show one manufacturing process of an example according to the present invention. As shown in (a), a photoresist 32 is used as a mask on the cleaned InP substrate 1, and the implantation energy is 100 keV and the dose is 5 x 1013c.
An ion-implanted layer 5 for a contact layer is formed by ion-implanting m-2 Si. Next, this photoresist is removed, a 100 OA layer of AlXGa1-XAs (X=0.3) is grown as an insulating protective film 3 by the MBE method, and a PSG film or the like is formed on this as a surface protective film.
) is annealed. AlGaAs and I
It was possible to obtain a good interface with nP, and it was possible to suppress interface states caused by P loss due to high-temperature annealing, and no surface deterioration was observed even after annealing at temperatures exceeding 800°C. Since the difference in thermal expansion coefficients between AlGaAs and InP is small, problems such as stress on the element can also be solved. After removing the protective film 6, a gate electrode 33 is formed, and finally a window is opened to make ohmic contact, and a source 7 and drain electrode 8 are formed (to obtain an enhanced mode FET as shown in 0). .

In the embodiments of the present invention, the insulating protective film 3 is made of AlXGa.
1-XAs (X = 0.3) and GaAs were used, but the composition X is not limited to this and can be changed.
It may be As. Furthermore, although the thickness was set to 100 OA in the embodiment, this is not limited to this either. However, since there is a slight difference in the coefficient of thermal expansion from InP, the thickness is preferably 3000 Å or less in order to obtain highly uniform results within the substrate surface. Further, the present invention is not limited to MIS type semiconductor devices, but can also be applied to, for example, MES type semiconductor devices. Furthermore, the ion implantation element can also be changed, making it possible to implant p-type impurities and apply it to elements using holes as conductors.

(Effects of the Invention) According to the present invention, since ion implantation is performed through the insulating film, impurities attached to the InP substrate surface simultaneously enter the channel layer as impurities due to ion implantation and affect the activation rate. is gone. Furthermore, even when ion implantation is not performed through the insulating film, AlGaA
It was possible to obtain a good interface between S or GaAs and InP, and it became possible to suppress interface states caused by P loss due to high-temperature annealing, and surface deterioration could be prevented even by high-temperature annealing. AlGaAs or GaA
Since the difference in thermal expansion coefficient between S and InP is small, problems such as stress on the element can also be solved. As described above, a semiconductor device using InP having a good insulating protective film as an operating material can be obtained, and it will greatly contribute to communication and logic circuits as high-frequency, high-speed integrated circuits and high-frequency, high-speed, high-output devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the manufacturing process of depletion mode InP MIS field effect transistors manufactured according to the first and second embodiments of the present invention, and FIG. Fabricated enhanced mode InP MI
FIG. 3 is a diagram showing the manufacturing process of an S field effect transistor, and FIG. 4 is a diagram showing the manufacturing process of a depletion mode InP MIS field effect transistor manufactured in the fourth embodiment of the present invention. A diagram showing the manufacturing process of an enhancement mode InPMIS field effect transistor manufactured in the fifth embodiment of the invention, FIG. It is a figure which shows the manufacturing process of an IE field effect transistor. In the figure, 1, , , , , , , , . 2,15 , , , , , , . 3,,,,,,,,,,. 4 , , , , , , , , . 6 , , , , , , . 0. . 7 , , , , , , , , . 8 , , , , , , , , . 31 , , , , , . 00. . 32 , , , , , , , . 33,,,. 0. ．． 1. ,. 53 , , , , , , , . It is. InP substrate ion implantation layer AlXGax XAs (0≦X≦1) Heat-resistant gate metal annealing protective film Source electrode drain electrode Photoresist Photoresist Gate metal annealing protective film

Claims (2)

[Claims] (1) In a method for manufacturing a semiconductor device using InP as an active layer or contact layer, Al_XGa_1_-_XA provided on the InP active layer or contact layer
1. A method for manufacturing a semiconductor device, comprising the step of implanting ions into InP through an S film (0≦X≦1). (2) In a method for manufacturing a semiconductor device using InP as an active layer or a contact layer, there is a step of implanting ions into a portion that will become the active layer or contact layer, and a step of forming an ion-implanted InP surface into an Al_XGa_1_-_XAs film (however, 0
1. A method for manufacturing a semiconductor device, comprising the step of activating the film by coating and heat-treating.