JPH0358483A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0358483A
JPH0358483A JP19374289A JP19374289A JPH0358483A JP H0358483 A JPH0358483 A JP H0358483A JP 19374289 A JP19374289 A JP 19374289A JP 19374289 A JP19374289 A JP 19374289A JP H0358483 A JPH0358483 A JP H0358483A
Authority
JP
Japan
Prior art keywords
layer
compound semiconductor
semiconductor device
xas
alxga1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19374289A
Other languages
Japanese (ja)
Inventor
Takemoto Kasahara
健資 笠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19374289A priority Critical patent/JPH0358483A/en
Publication of JPH0358483A publication Critical patent/JPH0358483A/en
Pending legal-status Critical Current

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  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To obtain a semiconductor device excellent in interfacial characteristic and high in breakdown strength by a method wherein a first AlxGa1-xAs layer is provided onto a compound semiconductor operating layer which contains In, which is thermally treated at a temperature of 650-800 deg.C, and a second AlxGa1-xAs layer is provided thereon. CONSTITUTION:A compound semiconductor operating layer 2 which contains In and a contact layer 3 are formed on a semi-insulating InP substrate 1. In this case, a first AlxGa1-xAs layer 4 is formed on the In-containing compound semiconductor operating layer 2, which is thermally treated at a temperature of 650-800 deg.C, and a second AlxGa1-xAs layer 6 is provided thereon. A source electrode 7 and a drain electrode 9 are formed, and furthermore a gate electrode 8 is built. That is, a thin AlGaAs is provided onto an In-containing compound semiconductor operating layer, which is thermally treated to form an interface level lessened layer, and then an AlGaAs is provided again, whereby an insulating film can be formed without making impurity diffuse into the whole insulating film or increase in the through transition. By this setup, a semiconductor device excellent in interfacial characteristic and high in breakdown strength can be obtained.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明はInを含む化合物半導体を動作層とする半導体
装置の製造方法にかかり、特に良好な界面特性を有する
半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device having an active layer made of a compound semiconductor containing In, and particularly to a method for manufacturing a semiconductor device having good interface characteristics.

〔従来の技術〕[Conventional technology]

Inを含む化合物半導体を動作層とする金属一絶縁体一
半導体(MIS)?li界効果トランジスタ(FET)
を例にとると、インターナショナル エレクトロンデバ
イス ミーティング(International E
lekutoran Device Meeting)
1986−P77tに伊東(T, Itoh)らの発表
によるrnPを動作層とした例がある。従来は、第2図
0に示すように半絶縁性InP基板1上にイオン注入お
よびアニールを施し、あるいはVPE法等により第2図
(ロ)のように動作層2及びコンタクト層3を形成し、
次いで第2図(ロ)のようにこれにゲート絶縁膜6とし
てA(lGaAs層をMBE法により成長した後、第2
図■のようにゲート電極8、ソース電極7、ドレイン電
極9を形威して電界効果トランジスタを実現してきた。
Metal-insulator-semiconductor (MIS) whose active layer is a compound semiconductor containing In? li field effect transistor (FET)
For example, the International Electron Device Meeting (International E
(Lekutoran Device Meeting)
In 1986-P77t, there is an example in which rnP is used as an operating layer, as announced by Itoh et al. Conventionally, an active layer 2 and a contact layer 3 are formed by ion implantation and annealing on a semi-insulating InP substrate 1 as shown in FIG. 20, or by VPE method, etc. as shown in FIG. 2(b). ,
Next, as shown in FIG. 2(b), after growing an A (lGaAs layer) as a gate insulating film 6 by the MBE method, a second
A field effect transistor has been realized by forming a gate electrode 8, a source electrode 7, and a drain electrode 9 as shown in FIG.

[発明が解決しようとする課題] しかしながら、従来の製造方法で作成したMISFET
について、例えばInPを動作層とし、AI2GaAs
層をゲート絶縁膜とした構造のMISFETでは、成長
後の界面には低減されてはいるものの未だに界面準位が
存在し、これが容量電圧特性において蓄積領域での周波
数分散やヒステリシスを生じさせるなどの問題が生じて
いる。また、デイブレッションモードのFET特性にお
いて、トランスコンダクタンスの上づまりやエンハンス
メント動作がしにくいといった形で悪影響をおよぼし、
大振幅動作での高周波特性に大きな影響があった。これ
らの現象は、成長後の熱処理によって改善されることが
判明したが、一方で熱処理によりゲート耐圧が劣化する
という現象が見られた。
[Problems to be solved by the invention] However, MISFETs manufactured using conventional manufacturing methods
For example, with InP as the active layer and AI2GaAs as the active layer,
In MISFETs with a structure in which the layer is a gate insulating film, interface states still exist at the interface after growth, although they have been reduced, and this causes problems such as frequency dispersion and hysteresis in the storage region in the capacitance voltage characteristics. A problem has arisen. In addition, it has an adverse effect on the FET characteristics in dableation mode, such as an increase in transconductance and difficulty in enhancement operation.
There was a significant effect on high frequency characteristics in large amplitude operation. It was found that these phenomena could be improved by heat treatment after growth, but on the other hand, a phenomenon was observed in which the gate breakdown voltage deteriorated due to heat treatment.

本発明の目的はInを含む化合物半導体を動作層とする
半導体の製造方法にかかり、特に良好な界面特性を有す
る半導体装置の製造方法に関する。
The present invention relates to a method for manufacturing a semiconductor using a compound semiconductor containing In as an active layer, and particularly to a method for manufacturing a semiconductor device having good interface characteristics.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するため、本発明はInを含む化合物半
導体を動作層とし、該Inを含む化合物半導体動作上に
ARxGa,−xAs層(但し0≦x≦1)を設けた半
導体装置の製造方法において、該Inを含む化合物半導
体動作層上に第1のAI2xGa,−xAs層を設けた
後、650〜800℃で熱処理し、さらに第2のlxG
a,、As層を設けるものである。
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device in which a compound semiconductor containing In is used as an active layer, and an ARxGa, -xAs layer (0≦x≦1) is provided on the active layer of the compound semiconductor containing In. After providing a first AI2xGa, -xAs layer on the In-containing compound semiconductor operating layer, heat treatment is performed at 650 to 800°C, and a second lxG
a, an As layer is provided.

〔作用〕[Effect]

Inを含む化合物半導体を動作層とするFETを作或す
る場合、Inを含む化合物半導体はショットキーバリア
の高さが低いため適当な絶縁膜を形威する必要がある。
When manufacturing an FET using a compound semiconductor containing In as an active layer, it is necessary to form an appropriate insulating film because the compound semiconductor containing In has a low Schottky barrier height.

この絶縁膜として格子不整系ではあるものの動作層と同
じ■一■化合物半導体であるAQGaAsが有用である
ことが判明している。しかしながら、動作層上に絶縁膜
であるAI20aAsを成長した構造でも、界面におい
て、格子不整により結晶欠陥が生じてこれが界面準位を
形成したり、残留不純物により界面準位が形成される。
It has been found that AQGaAs, which is the same compound semiconductor as the active layer, is useful as this insulating film, although it has a lattice mismatch. However, even in a structure in which an insulating film of AI20aAs is grown on the active layer, crystal defects occur at the interface due to lattice misalignment and form interface states, or interface states are formed due to residual impurities.

これらの界面準位が半導体装置の特性の劣化の原因とな
っていた。ところが、これらの界面準位が熱処理により
減少し、界面特性の向上が図られることが判明した。ま
た、一方で、熱処理によりゲート耐圧が悪くなる現象が
見られ、良好な界面特性と高いゲート耐圧の両立が必要
となる。そこで、Inを含む化合物半導体動作層上に薄
いAQGaAsを設け、これを熱処理して界面準位の低
減層を形成した後、再びlGaAsを設ければ、これに
より絶縁膜全体に不純物が拡散したり貫通転移の増加を
見ずに絶縁膜が形成できるため、界面特性が良好で高い
耐圧のゲート絶縁膜が得られる。さらに、この製造方法
を用いることは、例えばMBE法でInP基板上にA2
GaAsを成長する場合などでは、薄いAQGaAsを
成長しそのままAs雰囲気で熱処理を行い、続けて成長
を行えるので、熱処理のために保護膜を付けたり外部に
出して再成長するなどの工程が不必要となる。
These interface states have been a cause of deterioration in the characteristics of semiconductor devices. However, it has been found that these interface states are reduced by heat treatment and the interface properties are improved. On the other hand, there is a phenomenon in which the gate breakdown voltage deteriorates due to heat treatment, and it is necessary to achieve both good interface characteristics and high gate breakdown voltage. Therefore, if a thin AQGaAs layer is provided on a compound semiconductor active layer containing In, this is heat-treated to form an interface state reduction layer, and then lGaAs is provided again, this will prevent impurities from diffusing throughout the insulating film. Since an insulating film can be formed without increasing threading dislocation, a gate insulating film with good interface characteristics and high breakdown voltage can be obtained. Furthermore, using this manufacturing method means that A2
When growing GaAs, it is possible to grow thin AQGaAs, heat-treat it in an As atmosphere, and continue growing, so there is no need to apply a protective film for heat treatment or take it outside to re-grow it. becomes.

[実施例] 以下本発明の一実施例を第1図を用いて説明する。[Example] An embodiment of the present invention will be described below with reference to FIG.

第1図(a)に示す半絶縁性1nP基板(半絶縁性基板
)l上にVPE法により、あるいはイオン注入により第
1図(ロ)のようにInを含む化合物半導体動作層2と
してn−1nP動作層と、コンタクト層3としてn+−
InPコンタクト層とを形成する。次いでこの上に、第
1図(Q)のように例えばMBE法によりARGaAs
層4としてAQ,,,Ga,,xAsを基板温度500
℃で300人成長する。成長に当たり超高真空中でIn
P表面のクリニングを行い直ちに戒長を行う。その後連
続的にAs分子を照射しながら温度を750℃まで上げ
10分間保持する。MBEチャンバー内でAs照射のも
とで行うことで表面保護膜なしで表面劣化を防ぐことが
でき、熱処理により界面に生じた欠陥などが緩和されて
、界面準位の低減を図ることができる。
An n- 1nP active layer and n+- as contact layer 3
An InP contact layer is formed. Then, as shown in FIG. 1(Q), ARGaAs
Layer 4 is AQ, , Ga, , xAs at a substrate temperature of 500
Grows by 300 people at ℃. During growth, In
Clean the P surface and immediately perform the precept. Thereafter, the temperature was raised to 750° C. and held for 10 minutes while continuously irradiating As molecules. By carrying out the MBE process under As irradiation in an MBE chamber, surface deterioration can be prevented without the need for a surface protective film, and defects generated at the interface due to the heat treatment can be alleviated, thereby reducing the interface state.

第1図■において、5は熱処理をされたAffiGaA
s層を示している。さらにこの後、基板温度を600℃
に下げてAQ..,Ga.,xAsを400 A成長し
、第1図(e)のようにlGaAs層6を形成すること
で高耐圧のゲート絶縁膜を得ることができる。
In Figure 1 ■, 5 is heat-treated AffiGaA
The s-layer is shown. Furthermore, after this, the substrate temperature was increased to 600℃.
Lower it to AQ. .. , Ga. , xAs to a thickness of 400 A and forming an lGaAs layer 6 as shown in FIG. 1(e), a gate insulating film having a high breakdown voltage can be obtained.

得られた結晶を用いて通常の方法によりオーミック部分
の窓明けを行い、第lrl!U(イ)のようにソース電
極7及びドレイン電極9を形威し、さらにゲート電極8
を形成して電界効果トランジスタを得る。
Using the obtained crystal, the ohmic part was opened using the usual method, and the lrl! As shown in U (a), the source electrode 7 and the drain electrode 9 are formed, and the gate electrode 8 is formed.
to obtain a field effect transistor.

以上実施例では動作層をInPとしたがAI2GaAs
層などInを含む半導体層を用い゛ることが可能である
In the above embodiments, the active layer was InP, but AI2GaAs was used as the active layer.
It is possible to use a semiconductor layer containing In such as a semiconductor layer.

また、AffiGaAsの組成比をX=0.3としたが
この限りではない。さらに、膜厚に関してもこの限りで
はない。
Further, although the composition ratio of AffiGaAs was set to X=0.3, it is not limited to this. Furthermore, the film thickness is not limited to this.

第3図に従来の熱処理をしない製造方法及び構造でのF
ETのソース・ゲート間の容量電圧特性を示す。図に示
されるように熱処理しない場合蓄積領域において周波数
分散がみられ、トランスコンダクタンスgmも上詰まり
が見られる。また、第4図に成長後に熱処理した構造で
のFETのソース・ゲート間の電流電圧特性を示す。容
量電圧特性は改善されるが、逆方向耐圧の低下が見られ
る。これに対して本発明の製造方法及び構造のFETで
は、第5図に示されるように、容量電圧特性が良好で界
面準位が低減でき、第6図に見られるように逆方向耐圧
の低下も見られない。
Figure 3 shows F with the conventional manufacturing method and structure without heat treatment.
The capacitance voltage characteristics between the source and gate of ET are shown. As shown in the figure, without heat treatment, frequency dispersion is observed in the accumulation region, and transconductance gm is also observed to be overcrowded. Further, FIG. 4 shows the current-voltage characteristics between the source and gate of the FET in a structure that has been heat-treated after growth. Although the capacitance voltage characteristics are improved, there is a decrease in reverse breakdown voltage. On the other hand, in the FET manufactured by the manufacturing method and structure of the present invention, as shown in FIG. 5, the capacitance-voltage characteristics are good and interface states can be reduced, and as shown in FIG. 6, the reverse breakdown voltage is reduced. I can't even see it.

[発明の効果〕 以上本発明により良好な界面特性及び絶縁特性を有する
Inを含む化合物半導体を動作層とする半導体装置が得
られ、高周波の高速な集積回路や、高周波高出力デバイ
スとして通信や論理回路などへの寄与は大きい。
[Effects of the Invention] As described above, according to the present invention, a semiconductor device having an active layer made of a compound semiconductor containing In, which has good interface characteristics and insulation properties, can be obtained, and can be used as a high-speed high-frequency integrated circuit or a high-frequency, high-output device for communication or logic. Its contribution to circuits and other fields is significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜ωは本発明の製造方法を説明する半導体
装置の構造断面図、第2図(a)〜(自)は従来の製造
方法を説明する半導体装置の構造断面図、第3図は従来
の熱処理をしない製造方法により作成された半導体装置
のゲート・ソース電極間の容量電圧特性を示す図、第4
図は成長後熱処理を行った従来の半導体装置のゲート・
ソース1!1極間の電流電圧特性を示す図、第5図は本
発明による製造方法を用いた半導体装置の容量電圧特性
を示す図、第6図は本発明による製造方法を用いた半導
体装置の電流電圧特性を示す図である。 l・・・半絶縁性基板
1(a) to ω are structural cross-sectional views of a semiconductor device for explaining the manufacturing method of the present invention, and FIGS. 2(a) to ω are structural cross-sectional views of a semiconductor device for explaining the conventional manufacturing method. Figure 3 is a diagram showing the capacitance voltage characteristics between the gate and source electrodes of a semiconductor device manufactured by the conventional manufacturing method without heat treatment.
The figure shows the gate and
Source 1!A diagram showing current-voltage characteristics between one pole, FIG. 5 is a diagram showing capacitance-voltage characteristics of a semiconductor device using the manufacturing method according to the present invention, and FIG. 6 is a diagram showing a semiconductor device using the manufacturing method according to the present invention. FIG. 2 is a diagram showing the current-voltage characteristics of l...Semi-insulating substrate

Claims (1)

【特許請求の範囲】[Claims] (1)Inを含む化合物半導体を動作層とし、該Inを
含む化合物半導体動作上にAlxGa_1_−_xAs
層(但し0≦x≦1)を設けた半導体装置の製造方法に
おいて、該Inを含む化合物半導体動作層上に第1のA
lxGa_1_−_xAs層を設けた後、650〜80
0℃で熱処理し、さらに第2のAlxGa_1_−_x
As層を設けることを特徴とする半導体装置の製造方法
(1) A compound semiconductor containing In is used as an active layer, and AlxGa_1_-_xAs is formed on the compound semiconductor containing In.
In the method for manufacturing a semiconductor device in which a layer (0≦x≦1) is provided, a first A layer is formed on the compound semiconductor operating layer containing In.
After providing lxGa_1_-_xAs layer, 650-80
After heat treatment at 0°C, a second AlxGa_1_-_x
A method for manufacturing a semiconductor device, comprising providing an As layer.
JP19374289A 1989-07-26 1989-07-26 Manufacture of semiconductor device Pending JPH0358483A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19374289A JPH0358483A (en) 1989-07-26 1989-07-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19374289A JPH0358483A (en) 1989-07-26 1989-07-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0358483A true JPH0358483A (en) 1991-03-13

Family

ID=16313056

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19374289A Pending JPH0358483A (en) 1989-07-26 1989-07-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0358483A (en)

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