JPH0491435A - Formation method of mis structure electrode - Google Patents
Formation method of mis structure electrodeInfo
- Publication number
- JPH0491435A JPH0491435A JP2204529A JP20452990A JPH0491435A JP H0491435 A JPH0491435 A JP H0491435A JP 2204529 A JP2204529 A JP 2204529A JP 20452990 A JP20452990 A JP 20452990A JP H0491435 A JPH0491435 A JP H0491435A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- electrode
- substrate
- type gaas
- executed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000015572 biosynthetic process Effects 0.000 title description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims abstract description 29
- 238000011282 treatment Methods 0.000 claims abstract description 24
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052717 sulfur Inorganic materials 0.000 claims abstract description 18
- 239000011593 sulfur Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 150000001875 compounds Chemical class 0.000 claims abstract description 9
- 239000007772 electrode material Substances 0.000 claims abstract description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 24
- 238000000137 annealing Methods 0.000 abstract description 7
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 19
- 235000011007 phosphoric acid Nutrition 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910020489 SiO3 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000010926 purge Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＩＳ（金属−絶縁物一半導体）構造電極の形
成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming an MIS (metal-insulator-semiconductor) structured electrode.
ＭＩＳ構造電極は電界効果トランジスタなどに不可欠の
要素であり、この特性の改善のため、例えば特開昭６２
−３１１７０号、同６２−９４９４４号公報などの技術
が提案されている。このようなＭＩＳ構造電極では、半
導体と絶縁膜の界面準位密度が低いのが不可欠であるが
、Ｇａ Ａｓ系半導体では界面のダングリングボンドの
再構成が難しいため、一般に１０１３ａｍ−２ｅ Ｖ−
１オーダーの界面準位密度をもっている。これは、ＮＨ
８−ＦＥＴにおけるシリコンと二酸化シリコンの間の界
面準位密度に比べて、３桁程度も高い。MIS structure electrodes are essential elements for field effect transistors, etc., and in order to improve this characteristic, for example, Japanese Patent Laid-Open No. 62
Techniques such as No. 31170 and No. 62-94944 have been proposed. In such a MIS structure electrode, it is essential that the interface state density between the semiconductor and the insulating film is low, but in GaAs-based semiconductors, it is difficult to reconfigure the dangling bonds at the interface, so generally 1013 am-2e V-
It has an interface state density of 1 order. This is NH
This is about three orders of magnitude higher than the interface state density between silicon and silicon dioxide in an 8-FET.
ところが、最近になって（ＮＨ４）２Ｓｘを用いた硫黄
パッシベーション処理が注目され、例えば下記の文献
ｒ ’Ｎａｋｅｄ Ｒｅｄｕｃｔｉｏｎ ｔｈｅ ５ｕ
ｒｆ’ａｃｅ／Ｌｎｔｅｒｆ’ａｃｅＳｔａｔｅｓ ｏ
［’ ＧａＡｓ ｂｙ（ＮＨ４）２ｓｘＴｒｅａｔａ＋
ｅｎｔ ’（ＪＡＰＡＮＥＳＥ ＪＯＵＲＮＡＬ ＯＦ
ＡＰＰＬＩＥＤ ＰＨＹＳＩＣ８Ｖｏｌ、２８Ｎｏ、
１２． （１９８９年１２月） ｐｐ、Ｌ２２５５〜
Ｌ２２５７ ）Ｊでは、Ｇ ａ Ａ ｓ ／ Ｓ １０
２で界面準位密度が１ 、 ２ Ｘ １０ ”ｃｍ−２
ｅ Ｖ−’まで減少すルコとが確認されている。However, recently, sulfur passivation treatment using (NH4)2Sx has attracted attention, and for example, the following document r'Naked Reduction the 5u
rf'ace/Lnterf'aceStates o
['GaAs by (NH4)2sxTreat+
ent '(JAPANESE JOURNAL OF
APPLIED PHYSIC8Vol, 28No,
12. (December 1989) pp, L2255~
L2257) In J, G a A s / S 10
2, the interface state density is 1, 2 x 10”cm-2
It has been confirmed that the value decreases to V-'.
しかし、これによっても界面準位密度はＳｉ系のＭＯＳ
に比べ一桁近く高く、良好な特性のＭＩＳ構造ＦＥＴは
得られない。本発明者は、上記の諸点に鑑み、鋭意研究
を重ねた結果として、界面準位密度の大幅な低減を可能
にしたＭＩＳ構造電極の形成方法を見出した。However, even with this, the interface state density is
It is nearly an order of magnitude higher than that, and a MIS structure FET with good characteristics cannot be obtained. In view of the above points, as a result of extensive research, the present inventors have discovered a method for forming an MIS structure electrode that makes it possible to significantly reduce the interface state density.
本発明者は、硫黄パッシベーション処理の前段階におい
て、■−Ｖ族化合物半導体からなる基板表面を、種々の
エッチャントで処理して結果を検討する中で、本発明を
完成するに至った。The present inventor completed the present invention while treating the surface of a substrate made of a ■-V group compound semiconductor with various etchants in a pre-sulfur passivation process and studying the results.
すなわち本発明は、■−Ｖ族化合物半導体からなる基板
上に、絶縁膜を形成した後、電極材料を付着してＭＩＳ
構造電極を形成する方法において、絶縁膜の形成に先立
ち、基板表面をリン酸系エッチャントで処理して硫黄パ
ッジベージジン処理することを特徴とする。That is, in the present invention, an insulating film is formed on a substrate made of a -V group compound semiconductor, and then an electrode material is attached to the MIS.
The method for forming a structural electrode is characterized in that, prior to forming an insulating film, the surface of the substrate is treated with a phosphoric acid-based etchant to perform a sulfur purge treatment.
ここで、■−ｖ族化合物半導体は、ガリウムまたは砒素
の少なくともいずれか一方を含むようにしてもよい。Here, the ■-v group compound semiconductor may contain at least one of gallium and arsenic.
本発明では、硫黄パッシベーション処理に先立ち、リン
酸系エッチャントのような順メサエッチャントで基板の
表面層を除去しているので、■−■族化合物半導体と絶
縁膜の界面は、ダングリングボンドを減らすように再構
成され、界面準位密度の低減が可能になる。In the present invention, the surface layer of the substrate is removed using a normal mesa etchant such as a phosphoric acid-based etchant prior to sulfur passivation treatment, so that the interface between the ■-■ group compound semiconductor and the insulating film reduces dangling bonds. As a result, the interface state density can be reduced.
以下、添付図面を参照して本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
第１図は本発明の方法が適用され得るＭＩ ５ＦＥＴの
構造を示し、同図（ａ）はエピタキシャル成長方法を用
いて■−ｖ族化合物半導体基板を形成した場合、同図（
ｂ）はイオン注入法を用いて■−Ｖ族化合物半導体基板
を形成した場合に対応している。まず、同図（ａ）のＦ
ＥＴでは、ｐ型Ｇａ Ａｓ基板１１が用意され、ＯＭＶ
ＰＥ法などによりｎ型Ｇａ Ａｓ層１２およびｎ＋型Ｇ
ａＡｓ層１３が順次に形成される。次に、チャネル領域
のｎ＋型Ｇａ Ａｓ層１３が選択エツチングされてｎ型
Ｇａ Ａｓ層１２が露出される。しかる後、本発明の特
徴に係るリン酸系エッチャントによる処理がされ、ｎ型
Ｇａ Ａｓ層１２が表面が薄くエツチングされる。この
とき、ｎ 型Ｇａ Ａｓ層１３も軽くエツチングされる
が、特に問題はない。FIG. 1 shows the structure of an MI 5FET to which the method of the present invention can be applied, and FIG.
b) corresponds to the case where a ■-V group compound semiconductor substrate is formed using the ion implantation method. First, F in figure (a)
In ET, a p-type GaAs substrate 11 is prepared, and OMV
The n-type GaAs layer 12 and the n+-type G are formed by PE method etc.
The aAs layers 13 are sequentially formed. Next, the n+ type GaAs layer 13 in the channel region is selectively etched to expose the n type GaAs layer 12. Thereafter, the surface of the n-type GaAs layer 12 is etched thinly by treatment with a phosphoric acid etchant according to a feature of the present invention. At this time, the n-type GaAs layer 13 is also lightly etched, but there is no particular problem.
次に、（ＮＨ４）２Ｓ、溶液などを用いて硫黄パッシベ
ーション処理が施され、しかる後に絶縁膜１４が形成さ
れる。アニールののち、ゲート電極１５、ソース電極１
６およびドレイン電極１７が形成されると、第１図（ａ
）のＭＩＳＦＥＴが完成する。Next, a sulfur passivation process is performed using (NH4)2S, a solution, etc., and then an insulating film 14 is formed. After annealing, gate electrode 15, source electrode 1
6 and the drain electrode 17 are formed, as shown in FIG.
) MISFET is completed.
同図（ｂ）（ＱＭＩ ５ＦＥＴでは、ｐ−型ＧａＡｓ基
板１１が用意され、イオン注入法により活性層としての
ｎ型Ｇａ Ａｓ層１８と、コンタクト層としてのｎ 型
Ｇａ Ａｓ層１９が形成される。(b) (In the QMI 5FET, a p-type GaAs substrate 11 is prepared, and an n-type GaAs layer 18 as an active layer and an n-type GaAs layer 19 as a contact layer are formed by ion implantation. .
次に、必要に応じてチャネル領域をエツチングしてリセ
ス構造とした後に、本発明の特徴に係るリン酸系エッチ
ャントによる処理と、硫黄パッシベーション処理が施さ
れる。これについては、同図（ａ）の場合と同様である
。次に、絶縁膜１４が形成され、アニールの後にゲート
電極１５、ソース電極１６およびドレイン電極１７が形
成されると、第１図（ｂ）のＭＩＳＦＥＴが完成する。Next, after etching the channel region to form a recessed structure as necessary, treatment with a phosphoric acid-based etchant and sulfur passivation treatment according to the features of the present invention are performed. This is the same as in the case shown in FIG. Next, an insulating film 14 is formed, and after annealing, a gate electrode 15, a source electrode 16, and a drain electrode 17 are formed, thereby completing the MISFET shown in FIG. 1(b).
本発明者は、硫黄パッシベーション処理に先立つ各種エ
ッチャントによる処理の効果をＰＬ（螢光）強度で比較
した。The present inventor compared the effects of treatments with various etchants prior to sulfur passivation treatment in terms of PL (fluorescence) intensity.
その結果を第２図に示す。図示の通り、Ｈ３ＰＯ４を含
むエッチャントで軽くエツチングしたときには、バンド
端に対応する波長でＰＬ強度が高くなっている。これに
対し、アンモニア系あるいは硫酸系エッチャントのよう
な、いわゆる逆メサエッチャントで処理したときには、
大きな改善がされていないのが理解できる。ここで、逆
メサエッチャントとはエツチング面が逆メサ状及び順メ
サ状となるものを指し、リン酸系エッチャントではエツ
チング面が全方向で順メサ状となるので、ここでは順メ
サエッチャントと呼ぶ。The results are shown in FIG. As shown in the figure, when lightly etched with an etchant containing H3PO4, the PL intensity becomes high at the wavelength corresponding to the band edge. On the other hand, when treated with a so-called reverse mesa etchant such as an ammonia-based or sulfuric acid-based etchant,
I can understand that no major improvements have been made. Here, the term "reverse mesa etchant" refers to one in which the etched surface has an inverted mesa shape or a forward mesa shape, and in the case of a phosphoric acid-based etchant, the etched surface has a forward mesa shape in all directions, so it is referred to here as a forward mesa etchant.
次に、本発明者はＭＩＳＦＥＴを試作して本発明の効果
を確認した。Next, the inventor manufactured a prototype MISFET and confirmed the effects of the present invention.
実施例１
ｐ−型Ｇａ Ａｓ基板を用意し、ＯＭＶＰＥ法でｎ型Ｇ
ａ Ａｓ層を１００ＯＡの厚さ、ｎ 型ＧａＡｓ層を７
００Ａの厚さに成長させた。そして、ゲート開口部のｎ
＋型Ｇａ Ａｓ層を除去し、マスク除去後に
ＨＰＯ：ＨＯ：Ｈ０
−４：１：１００
のリン酸系エッチャントで全体を軽く処理した。Example 1 A p-type GaAs substrate was prepared, and an n-type G was formed using the OMVPE method.
a The As layer has a thickness of 100 OA, and the n-type GaAs layer has a thickness of 7
It was grown to a thickness of 00A. And n of the gate opening
After removing the + type GaAs layer and removing the mask, the entire structure was lightly treated with a phosphoric acid etchant of HPO:HO:H0 -4:1:100.
その後、（ＮＨ４）２ Ｓｘ溶液に１０分間浸漬し、２
０秒間水洗して窒素ガスブローで除水した。次イテ、Ｅ
ＣＲ−ＣＶＤ法ニヨリＳｉＮ膜を形成し、４５０℃で３
０分間の熱処理をした。その後、ゲート電極、ソース電
極及びドレイン電極を形成した。このＭＩＳＦＥＴにつ
いて、高周波Ｃ−Ｖ法で界面準位密度を測定したところ
、３Ｘ１０”ｃｎＩ−２ｅｖテあツタ。After that, it was immersed in (NH4)2Sx solution for 10 minutes, and
It was washed with water for 0 seconds and water was removed by nitrogen gas blowing. Next item, E
A SiN film is formed using the CR-CVD method and heated at 450°C for 30 minutes.
Heat treatment was performed for 0 minutes. After that, a gate electrode, a source electrode, and a drain electrode were formed. When the interface state density of this MISFET was measured using the high frequency CV method, it was found to be 3X10"cnI-2ev.
実施例２
ｐ−型Ｇａ Ａｓ基板を用意し、イオン注入によりｎ型
Ｇａ Ａｓ層およびｎ＋型Ｇａ Ａｓ層を形成した。し
かる後、実施例１と同様に、リン酸系エッチャントによ
る処理と硫黄バッジベージジン処理を行い、ＭＩＳＦＥ
Ｔを得た。このＭＩＳＦＥＴについて、高周波Ｃ−Ｖ法
で界面準位密度を測定したところ、９ Ｘ １０ ”ｃ
ｍ−２ｅ Ｖであった。実施例１に比べて界面準位密度
が高いのは、エピタキシャル成長法によれば結晶性が高
くなるためであると考えられる。Example 2 A p-type GaAs substrate was prepared, and an n-type GaAs layer and an n+-type GaAs layer were formed by ion implantation. Thereafter, in the same manner as in Example 1, treatment with a phosphoric acid etchant and sulfur badge treatment were performed, and MISFE
I got a T. When the interface state density of this MISFET was measured using the high frequency C-V method, it was found to be 9 x 10"c
m-2eV. The reason why the interface state density is higher than that in Example 1 is considered to be because the epitaxial growth method increases crystallinity.
比較例１
リン酸系エッチャントによる処理に代えてＮＨ４ＯＨ系
エッチャントでの処理を行い、絶縁膜は抵抗加熱による
ＳｉＯ３で形成した。他の条件は実施例１と同様にした
。このＭＩＳＦＥＴについて、高周波Ｃ−■法で界面準
位密度を測定したとコロ、１．２×１０１１ｍ−２ｅｖ
であった。Comparative Example 1 A treatment with an NH4OH-based etchant was performed instead of a treatment with a phosphoric acid-based etchant, and an insulating film was formed of SiO3 by resistance heating. Other conditions were the same as in Example 1. Regarding this MISFET, the interface state density was measured using the high frequency C-■ method and was found to be 1.2 x 1011 m-2ev.
Met.
なお、本発明者は参考のため、各成膜法によるＰＬ（蛍
光）強度の比較を行なった。For reference, the inventors compared the PL (fluorescence) intensity of each film forming method.
この結果を第３図に示す。図中の曲線（ａ）は硫黄パッ
シベーション処理の後にＥＣＲ−ＣＶＤで絶縁膜を形成
した結果であり、バンド端において高いＰＬ強度が得ら
れている。図中の曲線（ｂ）は、硫黄パッシベーション
処理を施したが絶縁膜は形成しなかった場合のものであ
る。これらに・より、ＥＣＲ−ＣＶＤ法を用いると、硫
黄パッシベーション処理の効果が全く劣化しないのがわ
かる。The results are shown in FIG. Curve (a) in the figure is the result of forming an insulating film by ECR-CVD after sulfur passivation treatment, and high PL intensity is obtained at the band edge. The curve (b) in the figure shows the case where the sulfur passivation treatment was performed but no insulating film was formed. These results show that the effect of sulfur passivation treatment does not deteriorate at all when the ECR-CVD method is used.
これは、ＥＣＲ−ＣＶＤ装置ではプラズマ発生室と成膜
室が異なるため、プラズマシャワーがＧａＡｓ系半導体
にダメージを与えないためと考えられる。This is thought to be because in the ECR-CVD apparatus, the plasma generation chamber and the film formation chamber are different, so that the plasma shower does not damage the GaAs-based semiconductor.
曲線（Ｃ）はスパッタ法、（ｄ）は熱ＣＶＤ法による成
膜をしたときのものである。硫黄パッシベーション処理
の効果が、ＥＣＲ−ＣＶＤ法に比べて劣化しているのが
わかる。曲線（ｅ）はＲＦ＝１３．５６ＭＨｚでのブラ
ズｖＣＶＤ法、曲線（ｇ）はＲＦ ＝ ５０ Ｋ Ｈｚ
でのブラズｖＣＶＤ法で絶縁膜を形成したときのもので
ある。硫黄パッシベーション処理の効果が、大きく劣化
しているのがわかる。なお、曲線（ｆ）は何らの処理も
してなかった場合である。The curve (C) shows the film formed by the sputtering method, and the curve (d) shows the film formed by the thermal CVD method. It can be seen that the effect of the sulfur passivation treatment is degraded compared to the ECR-CVD method. Curve (e) is Braz vCVD method at RF = 13.56 MHz, curve (g) is RF = 50 K Hz
This is when an insulating film was formed using the plasma CVD method. It can be seen that the effect of the sulfur passivation treatment has significantly deteriorated. Note that curve (f) is the case where no processing was performed.
次に、本発明者は、参考のため絶縁膜１４形成後のアニ
ールの影響を調べた。Next, the inventor investigated the influence of annealing after forming the insulating film 14 for reference.
その結果を第４図に示す。ＥＣＲ−ＣＶＤ法で形成した
ＳＩＮ膜は、３８０〜５２０℃特に４００〜５００℃で
アニールしたときに、ＰＬ強度が改善されている。これ
に対し、ＥＣＲ−ＣＶＤ法を用いた場合でもＳｉＯ２膜
のときには、アニールによって改善が見られない。なお
、上記のアニールは窒素ガス雰囲気中で、３０分間おこ
なった。The results are shown in FIG. The SIN film formed by the ECR-CVD method has improved PL strength when annealed at 380 to 520°C, particularly 400 to 500°C. On the other hand, even when ECR-CVD is used, no improvement is seen in the case of SiO2 film by annealing. Note that the above-mentioned annealing was performed for 30 minutes in a nitrogen gas atmosphere.
以上、詳細に説明した通り本発明では、硫黄パッシベー
ション処理に先立ち、リン酸系エッチャントのような順
メサエッチャントで基板の表面層を除去しているので、
■−Ｖ族化合物半導体と絶縁膜の界面は、ダングリング
ボンドを減らすように再構成され、界面準位密度の低減
が可能になる。As explained in detail above, in the present invention, the surface layer of the substrate is removed using a normal mesa etchant such as a phosphoric acid etchant prior to the sulfur passivation treatment.
(2) The interface between the V group compound semiconductor and the insulating film is reconfigured to reduce dangling bonds, making it possible to reduce the interface state density.
このため、特性の優れたＭＩＳ構造電極が得られる。Therefore, an MIS structure electrode with excellent characteristics can be obtained.
第１図は本発明方法が適用可能なＭＩＳＦＥＴの断面図
、第２図はリン酸系エッチャントによる処理の効果を示
す図、第３図は各成膜法によるＰＬ強度の差を示す図、
第４図はアニールの効果を示す図である。
１１−１）−型Ｇａ Ａｓ基板１．１２−ｎ ｍ Ｇ
ａＡｓ層、１３−ｎ＋型Ｇａ Ａｓ層、１４−・・絶縁
膜、１５・・・ゲート電極、１６・・・ソース電極、１
７・・・ドレイン電極、１８・・・ｎ型Ｇａ Ａｓ層、
１９・・・ｎ＋型Ｇａ Ａｓ層。
代理人弁理士 長谷用 芳 樹に’）ＣＪ
ニール温度の効果FIG. 1 is a cross-sectional view of a MISFET to which the method of the present invention can be applied, FIG. 2 is a diagram showing the effect of treatment with a phosphoric acid etchant, and FIG. 3 is a diagram showing the difference in PL intensity due to each film formation method.
FIG. 4 is a diagram showing the effect of annealing. 11-1)-type GaAs substrate 1.12-nm G
aAs layer, 13-n+ type GaAs layer, 14-... insulating film, 15... gate electrode, 16... source electrode, 1
7...Drain electrode, 18...n-type GaAs layer,
19...n+ type Ga As layer. Agent Patent Attorney Yoshiki Hase') CJ Effect of Neil Temperature
Claims (1)
を形成した後、電極材料を付着してＭＩＳ構造電極を形
成する方法において、 前記絶縁膜の形成に先立ち、前記基板表面をリン酸系エ
ッチャントで処理して硫黄パッシベーション処理するこ
とを特徴とするＭＩＳ構造電極の形成方法。 ２、前記III−Ｖ族化合物半導体は、ガリウムまたは砒
素の少なくともいずれか一方を含む請求項１記載のＭＩ
Ｓ構造電極の形成方法。[Claims] 1. In a method of forming an insulating film on a substrate made of a III-V compound semiconductor and then depositing an electrode material to form an MIS structure electrode, prior to forming the insulating film, A method for forming an MIS structure electrode, characterized in that the surface of the substrate is treated with a phosphoric acid-based etchant to perform sulfur passivation treatment. 2. The MI according to claim 1, wherein the III-V compound semiconductor contains at least one of gallium and arsenic.
Method for forming an S-structure electrode.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2204529A JPH0491435A (en) | 1990-08-01 | 1990-08-01 | Formation method of mis structure electrode |
| US07/736,967 US5393680A (en) | 1990-08-01 | 1991-07-30 | MIS electrode forming process |
| KR1019910013194A KR950007956B1 (en) | 1990-08-01 | 1991-07-31 | Electrode forming method of mis structure |
| CA002048206A CA2048206A1 (en) | 1990-08-01 | 1991-07-31 | Mis electrodes forming process |
| EP19910112950 EP0469604A2 (en) | 1990-08-01 | 1991-08-01 | MIS electrode forming process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2204529A JPH0491435A (en) | 1990-08-01 | 1990-08-01 | Formation method of mis structure electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0491435A true JPH0491435A (en) | 1992-03-24 |
Family
ID=16492050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2204529A Pending JPH0491435A (en) | 1990-08-01 | 1990-08-01 | Formation method of mis structure electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0491435A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009260325A (en) * | 2008-03-26 | 2009-11-05 | Univ Of Tokyo | Semiconductor substrate, method for manufacturing semiconductor substrate and semiconductor device |
| WO2011027871A1 (en) * | 2009-09-04 | 2011-03-10 | 住友化学株式会社 | Semiconductor substrate, field effect transistor, integrated circuit, and method for producing semiconductor substrate |
| CN103578957A (en) * | 2013-11-01 | 2014-02-12 | 清华大学 | Substrate surface passivating method and semiconductor structure forming method |
-
1990
- 1990-08-01 JP JP2204529A patent/JPH0491435A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009260325A (en) * | 2008-03-26 | 2009-11-05 | Univ Of Tokyo | Semiconductor substrate, method for manufacturing semiconductor substrate and semiconductor device |
| CN101978503A (en) * | 2008-03-26 | 2011-02-16 | 国立大学法人东京大学 | Semiconductor wafer, method of manufacturing a semiconductor wafer, and semiconductor device |
| WO2011027871A1 (en) * | 2009-09-04 | 2011-03-10 | 住友化学株式会社 | Semiconductor substrate, field effect transistor, integrated circuit, and method for producing semiconductor substrate |
| JP2012023326A (en) * | 2009-09-04 | 2012-02-02 | Sumitomo Chemical Co Ltd | Semiconductor substrate, field effect transistor, integrated circuit and method for manufacturing semiconductor substrate |
| US9112035B2 (en) | 2009-09-04 | 2015-08-18 | Sumitomo Chemical Company, Limited | Semiconductor substrate, field-effect transistor, integrated circuit, and method for fabricating semiconductor substrate |
| CN103578957A (en) * | 2013-11-01 | 2014-02-12 | 清华大学 | Substrate surface passivating method and semiconductor structure forming method |
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