JPH0491436A - Formation method of mis structure electrode - Google Patents
Formation method of mis structure electrodeInfo
- Publication number
- JPH0491436A JPH0491436A JP2204531A JP20453190A JPH0491436A JP H0491436 A JPH0491436 A JP H0491436A JP 2204531 A JP2204531 A JP 2204531A JP 20453190 A JP20453190 A JP 20453190A JP H0491436 A JPH0491436 A JP H0491436A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- ecr
- substrate
- electrode
- mis structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 238000011282 treatment Methods 0.000 claims abstract description 19
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052717 sulfur Inorganic materials 0.000 claims abstract description 18
- 239000011593 sulfur Substances 0.000 claims abstract description 18
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 150000001875 compounds Chemical class 0.000 claims abstract description 7
- 239000007772 electrode material Substances 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims 1
- 229910052785 arsenic Inorganic materials 0.000 claims 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 1
- 229910052733 gallium Inorganic materials 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 23
- 238000000137 annealing Methods 0.000 abstract description 6
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 11
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 5
- 235000011007 phosphoric acid Nutrition 0.000 description 5
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＩＳ（金属−絶縁物一半導体）構造電極の形
成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming an MIS (metal-insulator-semiconductor) structured electrode.
ＭＩＳ構造電極は絶縁ゲート型電界効果トランジスタな
どに不可欠の要素であり、この特性の改善のため、例え
ば特開昭６２−３１１７０号、同６２−９４９４４号公
報などの技術が提案されている。このようなＭＩＳ構造
電極では、半導体と絶縁膜の界面準位密度が低いのが不
可欠であるが、Ｇａ Ａｓ系半導体では界面のダングリ
ングボンドの再構成が難しいため、一般に１０ ’ａｍ
−２ｅ Ｖ −’オーダーの界面準位密度をもっている
。これは、ＭＯＳ−ＦＥＴにおけるシリコンと二酸化シ
リコンの間の界面準位密度に比べて、３桁程度も高い。The MIS structure electrode is an essential element for insulated gate field effect transistors, etc., and techniques such as Japanese Patent Application Laid-open Nos. 62-31170 and 62-94944 have been proposed to improve its characteristics. In such a MIS structure electrode, it is essential that the interface state density between the semiconductor and the insulating film is low, but in the case of GaAs-based semiconductors, it is difficult to reconfigure the dangling bonds at the interface, so it is generally
It has an interface state density on the order of −2e V −′. This is about three orders of magnitude higher than the interface state density between silicon and silicon dioxide in a MOS-FET.
そこで、最近になって（ＮＨ４）２Ｓｘを用いた硫黄パ
ッシベーション処理が注目され、例えば下記の文献
「“Ｎａｋｅｄ Ｒｅｄｕｃｔｉｏｎ ｔｈｅ ５ｕｒ
ｆ’ａｃｅ／Ｉｎｔｅｒｆ’ａｃｅＳｔａｔｅｓ ｏｊ
ＧａＡｓ ｂＦ（ＮＨ４）２ ＳｘＴｒｅａｔｍｅｎ
ｔ ”（ＪＡＰＡＮＥＳＥ ＪＯＵＲＮＡＬ ＯＦ Ａ
ＰＰＬＩＥＤ ＰＩＩＹ８１Ｃ８Ｖｏ＋、２Ｂ。Therefore, recently, sulfur passivation treatment using (NH4)2Sx has attracted attention.
f'ace/Interf'ace States oj
GaAs bF(NH4)2 SxTreatmen
t”(JAPANESE JOURNAL OF A
PPLIED PIIY81C8Vo+, 2B.
Ｎｏ、１２． （１９８９年１２月） ｐｐ、Ｌ２２５
５〜Ｌ２２５７ ） Ｊでは、Ｇａ Ａｓ ／Ｓｉ Ｏ
２で界面準位密度が１．２Ｘ１０”■−２ｅｖ−１まで
減少することが確認されている。No, 12. (December 1989) pp, L225
5~L2257) In J, GaAs/SiO
2, it has been confirmed that the interface state density decreases to 1.2×10”−2ev−1.
しかし、これによっても界面準位密度はＳｉ系のＭＯ８
構造に比べ一桁近く高く、良好な特性のＭＩＳ構造ＦＥ
Ｔは得られない。本発明者は、上記の諸点に鑑み、鋭意
研究を重ねた結果とし工、界面準位密度の大幅な低減を
可能にしたＭＩＳ構造電極の形成方法を見出した。However, even with this, the interface state density is
MIS structure FE with good characteristics and nearly an order of magnitude higher than the structure
T cannot be obtained. In view of the above points, the inventors of the present invention have conducted extensive research and have discovered a method for forming an MIS structure electrode that makes it possible to significantly reduce the interface state density.
本発明者は、硫黄バッジベージラン処理後の絶縁膜形成
において、種々の成膜法を採用して結果を検討する中で
、本発明を完成するに至った。The present inventor has completed the present invention while employing various film forming methods and studying the results in forming an insulating film after a sulfur badge run process.
すなわち本発明は、■−Ｖ族化合物半導体からなる基板
上に、絶縁膜を形成した後、電極材料を付着してＭＩＳ
構造電極を形成する方法において、絶縁−゛の形成に先
立ち、基板表面に対して硫黄パッジベージジン処理し、
絶縁膜はＥＣＲ−ＣＶＤにより形成することを特徴とす
る。That is, in the present invention, an insulating film is formed on a substrate made of a -V group compound semiconductor, and then an electrode material is attached to the MIS.
In a method for forming a structural electrode, prior to forming an insulator, the surface of the substrate is treated with a sulfur pad,
The insulating film is characterized by being formed by ECR-CVD.
ここで、形成される絶縁膜はＳｉＮ膜とし、形成後に３
８０〜５２０℃の熱処□理するようにしてもよい。Here, the insulating film to be formed is a SiN film, and after formation, 3
Heat treatment at 80 to 520°C may also be performed.
本発明では、硫黄パッシベーション処理の後に、基板へ
のダメージが少ないＥＣＲ−ＣＶＤで絶縁膜を堆積して
いるので、■−ｖ族化合物半導体と絶縁膜の界面におけ
るダングリングボンド低減の効果は維持され、界面準位
密度の低減が可能になる。In the present invention, after the sulfur passivation treatment, the insulating film is deposited by ECR-CVD, which causes less damage to the substrate, so the effect of reducing dangling bonds at the interface between the ■-V group compound semiconductor and the insulating film is maintained. , it becomes possible to reduce the interface state density.
以下、添付図面を参照して本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
第１図は本発明の方法が適用され得るＭＩ ５ＦＥＴの
構造を示し、同図（ａ）はエピタキシャル成長方法を用
いて■−ｖ族化合物半導体基板を形成した場合、同図（
ｂ）はイオン注入法を用いて■−ｖ族化合物半導体基板
を形成した場合に対応している。まず、同図（ａ）のＦ
ＥＴでは、ｐ型Ｇａ Ａｓ基板１１が用意され、ＯＭＶ
ＰＥ法などによりｎ型Ｇａ Ａｓ層１２およびｎ 型Ｇ
ａ。FIG. 1 shows the structure of an MI 5FET to which the method of the present invention can be applied, and FIG.
b) corresponds to the case where a ■-v group compound semiconductor substrate is formed using the ion implantation method. First, F in figure (a)
In ET, a p-type GaAs substrate 11 is prepared, and OMV
The n-type GaAs layer 12 and the n-type G
a.
Ａｓ層１３が順次に形成される。次に、チャネル領域の
ｎ 型Ｇａ Ａｓ層１３が選択エツチングされてｎ型Ｇ
ａ Ａｓ層１２が露出される。しかる後、必要に応じて
リン酸系エッチャントによる処理がされ、ｎ型Ｇａ Ａ
ｓ層１２が表面が薄くエツチングされる。次に、（ＮＨ
４）２Ｓｘ溶液などを用いて硫黄パッシベーション処理
が施され、しかる後にＳｉｎ、ＳｉＮのような絶縁膜１
４が形成される。この絶縁膜１４の形成はＥＣＲ−ＣＶ
Ｄ法により行なわれ、次いで３８０〜５２０℃のアニー
ルがされる。このような本発明の特徴に係る処理を経た
のち、ゲート電極１５、ソース電極１６およびドレイン
電極１７が形成されると、第１図（ａ）のＭＩＳＦＥＴ
が完成する。As layers 13 are sequentially formed. Next, the n-type GaAs layer 13 in the channel region is selectively etched to form an n-type GaAs layer 13.
a The As layer 12 is exposed. Thereafter, treatment with a phosphoric acid-based etchant is performed as necessary, and n-type Ga A
The surface of the s-layer 12 is etched thinly. Next, (NH
4) A sulfur passivation process is performed using a 2Sx solution, and then an insulating film 1 such as Sin or SiN is formed.
4 is formed. This insulating film 14 is formed by ECR-CV.
D method is used, followed by annealing at 380 to 520°C. After the process according to the features of the present invention, the gate electrode 15, source electrode 16, and drain electrode 17 are formed, and the MISFET shown in FIG.
is completed.
同図（ｂ）のＭＩ ５ＦＥＴでは、ｐ−型ＧａＡｓ基板
１１が用意され、イオン注入法により活性層としてのｎ
型Ｇａ Ａｓ層１８と、コシタクト層としてのｎ＋型Ｇ
ａ Ａｓ層１９が形成される。In the MI 5FET shown in FIG. 6(b), a p-type GaAs substrate 11 is prepared, and an n-type active layer is formed by ion implantation.
type GaAs layer 18 and n+ type G as a cositact layer
a As layer 19 is formed.
次に、必要に応じてチャネル領域をエツチングしてリセ
ス構造とした後に、硫黄バッシベ〒ジョン処理が施され
る。これについては、同図（ａ）の場合と同様である。Next, after etching the channel region to form a recessed structure as required, a sulfur bashing process is performed. This is the same as in the case shown in FIG.
次に、ＳＩＯ，ＳｉＮのような絶縁膜１４がＥＣＲ−Ｃ
ＶＤ法で形成され、３８０〜５２０℃でのアニールの後
にゲート電極１５、ソース電極１６およびドレイン電極
１７が形成されると、第１図（ｂ）のＭＩＳＦＥＴが完
成する。Next, an insulating film 14 such as SIO or SiN is applied to the ECR-C.
When the gate electrode 15, source electrode 16 and drain electrode 17 are formed after being formed by the VD method and annealed at 380 to 520° C., the MISFET shown in FIG. 1(b) is completed.
まず、本発明者は、各成膜法によるＰＬ（蛍光）強度の
比較を行なった。First, the inventors compared the PL (fluorescence) intensity of each film forming method.
この結果を第２図に示す。図中の曲線（ａ）は硫黄パッ
シベーション処・理の後にＥＣＲ−ＣＶＤで絶縁膜を形
成した結果であり、バンド端発光において高い強度が得
られている。図中の曲線（ｂ）は、硫黄パッシベーショ
ン処理を施したが絶縁膜は形成しなかった場合のもので
ある。これらにより、ＥＣＲ−ＣＶＤ法を用いると、硫
黄パッシベーション処理の効果が全く劣化しないのがわ
かる。The results are shown in FIG. Curve (a) in the figure is the result of forming an insulating film by ECR-CVD after sulfur passivation treatment, and high intensity is obtained in band edge emission. The curve (b) in the figure shows the case where the sulfur passivation treatment was performed but no insulating film was formed. These results show that the effect of sulfur passivation treatment does not deteriorate at all when the ECR-CVD method is used.
これは、ＥＣＲ−ＣＶＤ装置ではプラズマ発生室と成膜
室が異なるため、プラズマシャワーがＧａＡｓ系半導体
にダメージを与えないためと考えられる。This is thought to be because in the ECR-CVD apparatus, the plasma generation chamber and the film formation chamber are different, so that the plasma shower does not damage the GaAs-based semiconductor.
曲線（Ｃ）はスパッタ法、（ｄ）は熱ＣＶＤ法による成
膜をしたときのものである。硫黄パッシベーション処理
の効果が、ＥＣＲ−ＣＶＤ法に比べて劣化しているのが
わかる。曲線（ｅ）はＲＦ＝１３．５６ＭＨｚでのプラ
ズｖＣＶＤ法、曲線（ｇ）はＲＦ＝５０ＫＨｚでのブラ
ズｖＣＶＤ法で絶縁膜を形成したときのものである。硫
黄パッシベーション処理の効果が、大きく劣化している
のがわかる。なお、曲線（ｆ）は何らの処理もしてなか
った場合である。The curve (C) shows the film formed by the sputtering method, and the curve (d) shows the film formed by the thermal CVD method. It can be seen that the effect of the sulfur passivation treatment is degraded compared to the ECR-CVD method. The curve (e) shows the insulating film formed by the plasma vCVD method at RF=13.56 MHz, and the curve (g) shows the insulating film formed by the plasma vCVD method at RF=50 kHz. It can be seen that the effect of the sulfur passivation treatment has significantly deteriorated. Note that curve (f) is the case where no processing was performed.
次に、本発明者は、絶縁膜１４形成後のアニルの影響を
調べた。Next, the inventor investigated the influence of anil after forming the insulating film 14.
その結果を第３図に示す。ＥＣＲ−ＣＶＤ法で形成した
ＳｉＮ膜は、３８０〜５２０℃の温度範囲、特に４００
〜５００℃でアニールしたときに、ＰＬ強度が改善され
ている。これに対し、ＥＣＲ−ＣＶＤ法を用いた場合で
もＳｔ、、膜のときには、アニールによって改善が見ら
れない。なお、上記のアニールは窒素ガス雰囲気中で、
３０分間おこなった。The results are shown in FIG. The SiN film formed by the ECR-CVD method can be heated in the temperature range of 380 to 520°C, especially at 400°C.
PL strength is improved when annealed at ~500°C. On the other hand, even when the ECR-CVD method is used, no improvement is seen in the case of the St film by annealing. The above annealing was performed in a nitrogen gas atmosphere.
This was done for 30 minutes.
次に、本発明者はＭＩＳＦＥＴを試作して本発明の効果
を確認した。Next, the inventor manufactured a prototype MISFET and confirmed the effects of the present invention.
実施例１
ｐ−型Ｇａ Ａｓ基板を用意し、ＯＭＶＰＥ法でｎ型Ｇ
ａ Ａｓ層を１００ＯＡの厚さ、ｎ 型ＧａＡｓ層を７
０ＯＡの厚さに成長させた。そして、レジストマスクを
形成してゲート開口部のｎ 型Ｇａ Ａｓ層を除去し、
マスク除去後にリン酸系エッチャントで全体を軽く処理
した。その後、（ＮＨ４）２Ｓｘ溶液に１０分間浸漬し
、２０秒間水洗して窒素ガスブローで除水した。次いで
、ＥＣＲ−ＣＶＤ法によりＳｉＮ膜を形成し、４５０℃
で３０分間の熱処理をした。その後、ゲート電極、ソー
ス電極及びドレイン電極を形成した。このＭＩＳＦＥＴ
について、高周波Ｃ−ｖ法で界面準位密度を測定したと
ころ、３×１０１０ｃＩＩｌ−２ｅｖテあった。Example 1 A p-type GaAs substrate was prepared, and an n-type G was formed using the OMVPE method.
a The As layer has a thickness of 100 OA, and the n-type GaAs layer has a thickness of 7
It was grown to a thickness of 0OA. Then, a resist mask is formed and the n-type GaAs layer in the gate opening is removed.
After removing the mask, the entire surface was lightly treated with a phosphoric acid etchant. Thereafter, it was immersed in a (NH4)2Sx solution for 10 minutes, washed with water for 20 seconds, and water was removed by nitrogen gas blowing. Next, a SiN film was formed by ECR-CVD method and heated at 450°C.
Heat treatment was performed for 30 minutes. After that, a gate electrode, a source electrode, and a drain electrode were formed. This MISFET
When the interface state density was measured using the high frequency CV method, it was found to be 3 x 1010cIIl-2evte.
実施例２
ｐ−型Ｇａ Ａｓ基板を用意し、イオン注入によりｎ型
Ｇａ Ａｓ層およびｎ 型Ｇａ Ａｓ層を形成した。し
かる後、実施例１と同様に硫黄パッシベーション処理を
し、ＥＣＲ−ＣＶＤ法でＳＩ Ｎ膜を形成し、次いで４
５０℃、３０分のアニールを行い、ＭＩＳＦＥＴを得た
。このＭＩＳＦＥＴについて、高周波Ｃ−Ｖ法で界面準
位密度を測定したところ、９×１０１ＯｃｌＴｌ−２ｅ
ｖテあツタ。実施例１に比べて界面準位密度が高いのは
、エピタキシャル成長法によれば結晶性が高く、イオン
注入法によれば注入イオンでダメージを受けるためであ
ると考えられる。Example 2 A p-type GaAs substrate was prepared, and an n-type GaAs layer and an n-type GaAs layer were formed by ion implantation. Thereafter, a sulfur passivation treatment was performed in the same manner as in Example 1, and an SI N film was formed using the ECR-CVD method.
Annealing was performed at 50° C. for 30 minutes to obtain a MISFET. When the interface state density of this MISFET was measured using the high frequency C-V method, it was found to be 9×101OclTl-2e.
Vte attuta. The reason why the interface state density is higher than that in Example 1 is considered to be that crystallinity is high in the epitaxial growth method, and damage is caused by implanted ions in the ion implantation method.
比較例ｌ
ＮＨ４ＯＨ系エッチャントでの処理を行い、硫黄処理の
後、絶縁膜を形成した。ここで、絶縁膜は抵抗加熱によ
るＳｉＯ□で形成した。他の条件は実施例１と同様にし
た。このＭＩＳＦＥＴについて、高周波Ｃ−ｖ法で界面
準位密度を測定したトコ口、１ 、 ２ Ｘ １０ ”
ｃｍ−２ｅ Ｖ テアッｔ：。Comparative Example 1 A treatment with an NH4OH-based etchant was performed, and after a sulfur treatment, an insulating film was formed. Here, the insulating film was formed of SiO□ by resistance heating. Other conditions were the same as in Example 1. For this MISFET, the interface state density was measured using the high frequency CV method.
cm-2e V teat:.
次に、本発明者は、参考のため硫黄パッシベーション処
理に先立つ各種エッチャントによる処理の効果をＰＬ強
度で比較した。Next, for reference, the inventors compared the effects of treatments with various etchants prior to sulfur passivation treatment in terms of PL intensity.
その結果を第４図に示す。図示の通り、Ｈ３ＰＯ４を含
むエッチャントで軽くエツチングしたときには、バンド
端に対応する波長でＰＬ強度が高くなっている。これに
対し、アンモニア系あるいは硫酸系エッチャントのよう
な、いわゆる逆メサエッチャントで処理したときには、
大きな改善がされていないのが理解できる。ここで、逆
メサエッチャントとはエツチング面が逆メサ状及び順メ
サ状となるものを指し、リン酸系エッチャントではエツ
チング面が全方位に於て順メサ状となるので、ここでは
順メサエッチャントと呼ぶ。The results are shown in FIG. As shown in the figure, when lightly etched with an etchant containing H3PO4, the PL intensity becomes high at the wavelength corresponding to the band edge. On the other hand, when treated with a so-called reverse mesa etchant such as an ammonia-based or sulfuric acid-based etchant,
I can understand that no major improvements have been made. Here, the term "reverse mesa etchant" refers to one in which the etching surface has an inverted mesa shape or a forward mesa shape.In the case of a phosphoric acid etchant, the etching surface has a forward mesa shape in all directions, so here it is referred to as a "forward mesa etchant". call.
以上、詳細に説明した通り本発明では、硫黄パッシベー
ション処理後に、基板の表面にダメージを与えにくいＥ
ＣＲ−ＣＶＤ法で絶縁膜を形成しているので、■−Ｖ族
化合物半導体と絶縁膜の界面におけるダングリングボン
ド低減の効果は維持され、界面準位密度の低減が可能に
なる。このため、特性の優れたＭＩＳ構造電極が得られ
る。As explained in detail above, in the present invention, after the sulfur passivation treatment, E
Since the insulating film is formed by the CR-CVD method, the effect of reducing dangling bonds at the interface between the ■-V group compound semiconductor and the insulating film is maintained, and the interface state density can be reduced. Therefore, an MIS structure electrode with excellent characteristics can be obtained.
第１図は本発明方法が適用可能なＭＩＳＦＥＴの断面図
、第２図は各成膜法によるＰＬ強度の差を示す図、第３
図はアニールの効果を示す図、第４図はリン酸系エッチ
ャントによる処理の効果を示す図である。
１１ ・ｆ）−型Ｇａ Ａｓ基板１．１２・・・ｎ型Ｇ
ａＡｓ層、１３−ｎ＋型Ｇａ Ａｓ層、１４ ・・・絶
縁膜、１５・・・ゲート電極、１６・・・ソース電極、
１７・・・ドレイン電極、１８・・・ｎ型Ｇａ Ａｓ層
、１９・・・ｎ＋型Ｇａ Ａｓ層。
代理人弁理士 長谷用 芳 樹「ＯＣＪFigure 1 is a cross-sectional view of a MISFET to which the method of the present invention can be applied, Figure 2 is a diagram showing the difference in PL intensity due to each film formation method, and Figure 3
The figure shows the effect of annealing, and FIG. 4 shows the effect of treatment with a phosphoric acid etchant. 11 ・f)-type Ga As substrate 1.12...n-type G
aAs layer, 13-n+ type GaAs layer, 14... insulating film, 15... gate electrode, 16... source electrode,
17...Drain electrode, 18...n-type GaAs layer, 19...n+-type GaAs layer. Representative Patent Attorney Yoshiki Hase “OCJ
Claims (1)
を形成した後、電極材料を付着してＭＩＳ構造電極を形
成する方法において、 前記絶縁膜の形成に先立ち、前記基板表面に対して硫黄
パッシベーション処理をし、 前記絶縁膜の形成は、ＥＣＲ−ＣＶＤ法により行なうこ
とを特徴とするＭＩＳ構造電極の形成方法。 ２、前記絶縁膜の形成は、ＥＣＲ−ＣＶＤ法でＳｉＮを
堆積することにより行い、次いで３８０〜５２０℃の熱
処理をする請求項１記載のＭＩＳ構造電極の形成方法。 ３、前記III−Ｖ族化合物半導体は、ガリウムまたは砒
素の少なくともいずれか一方を含む請求項１記載のＭＩ
Ｓ構造電極の形成方法。[Claims] 1. In a method of forming an insulating film on a substrate made of a III-V compound semiconductor and then depositing an electrode material to form an MIS structure electrode, prior to forming the insulating film, A method for forming an MIS structure electrode, characterized in that the substrate surface is subjected to sulfur passivation treatment, and the insulating film is formed by an ECR-CVD method. 2. The method for forming an MIS structure electrode according to claim 1, wherein the insulating film is formed by depositing SiN using an ECR-CVD method, and then subjected to heat treatment at 380 to 520°C. 3. The MI according to claim 1, wherein the III-V compound semiconductor contains at least one of gallium and arsenic.
Method for forming an S-structure electrode.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2204531A JPH0491436A (en) | 1990-08-01 | 1990-08-01 | Formation method of mis structure electrode |
| US07/736,967 US5393680A (en) | 1990-08-01 | 1991-07-30 | MIS electrode forming process |
| CA002048206A CA2048206A1 (en) | 1990-08-01 | 1991-07-31 | Mis electrodes forming process |
| KR1019910013194A KR950007956B1 (en) | 1990-08-01 | 1991-07-31 | Electrode forming method of mis structure |
| EP19910112950 EP0469604A2 (en) | 1990-08-01 | 1991-08-01 | MIS electrode forming process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2204531A JPH0491436A (en) | 1990-08-01 | 1990-08-01 | Formation method of mis structure electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0491436A true JPH0491436A (en) | 1992-03-24 |
Family
ID=16492084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2204531A Pending JPH0491436A (en) | 1990-08-01 | 1990-08-01 | Formation method of mis structure electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0491436A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014518449A (en) * | 2011-06-14 | 2014-07-28 | サントル・ナショナル・ドゥ・ラ・レシェルシュ・サイエンティフィーク−セ・エン・エール・エス− | Method of chemically passivating the surface of a product made of III-V semiconductor material and the product obtained by the method |
-
1990
- 1990-08-01 JP JP2204531A patent/JPH0491436A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014518449A (en) * | 2011-06-14 | 2014-07-28 | サントル・ナショナル・ドゥ・ラ・レシェルシュ・サイエンティフィーク−セ・エン・エール・エス− | Method of chemically passivating the surface of a product made of III-V semiconductor material and the product obtained by the method |
| US9514961B2 (en) | 2011-06-14 | 2016-12-06 | Centre National de la Recherche Scientifique—CNRS | Method for chemically passivating a surface of a product made of a III-V semiconductor material and the product obtained by such a method |
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