JP3228979B2 - Semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION The present invention relates generally to semiconductor devices, and more particularly to passivation of semiconductor devices.

As is known in the art, it is common to encapsulate a semiconductor device in an inert material to insulate the semiconductor device directly from the environment. If the semiconductor element is not insulated, the electrical characteristics of the semiconductor element may be degraded by an environment that can contain oxygen, water, and the like.

In particular, metal semiconductor field effect transistors (MESs) containing III-V materials such as gallium arsenide
For microwave semiconductor devices such as FETS),
Passivating materials such as silicon nitride, silicon monoxide, silicon dioxide, silicon oxynitride, or polymers are typically deposited on the surface of semiconductor devices to insulate the gallium arsenide exposed surface from the external environment. Is known.

[0004] Silicon nitride is one of the most widely used materials for the passivation layer on gallium arsenide because it is extremely chemically stable and has good barrier properties. In addition, silicon nitride can also provide dielectric properties, for example, for metal-insulator-metal (MIM) capacitors commonly used in microwave monolithic integrated circuits. Whether the MESFET is a discrete device or is incorporated as part of a microwave monolithic integrated circuit, the most common approach used to deposit silicon nitride for MESFET applications is at temperatures of about 150-300. This is a method using a plasma-enhanced reactant vapor deposition method that provides a plasma of a reactant gas containing silicon and nitrogen at ° C. In the method,
The gas is reacted within the aforementioned temperature range to deposit silicon nitride on the semiconductor substrate.

[0005] While silicon nitride films, as well as many other passivation films, have highly desirable properties as passivation, they also have some disadvantages. One of those drawbacks is that silicon nitride films generally change the threshold voltage of field effect transistors. That is, the voltage to "pinch off" the channel of the transistor can change after the deposition of silicon nitride. Also, it has been observed that the properties of the transistor are degraded by surface damage due to energy ion bombardment imparted during plasma enhanced deposition.

[0006] Further, after encapsulation with a passivating material including silicon nitride as described above, a problem observed in MESFETs is that the reverse breakdown voltage between the gate electrode and the drain electrode and between the drain electrode and the source electrode is undesirably low. That is, it will decrease. This effect is observed in all commonly used types of encapsulants. The amount of decrease in the reverse breakdown voltage varies widely from one wafer to the next wafer, greatly changing the final breakdown voltage characteristics. This change makes it difficult to provide standards for individual devices. Further, the reduction in reverse breakdown voltage also reduces power capacity. Occasionally, in addition to the aforementioned reduction in reverse breakdown voltage, other MESFET characteristics may be altered by passivating materials such as silicon nitride. One general property that changes with passivation is the leakage current between the gate and drain electrodes when operated under reverse bias conditions. This characteristic is often unstable and may change in magnitude with the operation of the transistor. In particular, the increase in leakage current often occurs several minutes after operating the device under high gate current conditions.

SUMMARY OF THE INVENTION In accordance with the present invention, a method for preparing a semiconductor surface for accepting a passivation layer on a semiconductor device comprises an electronegative species having a voltage potential bias greater than 0 volts between the plasma and the semiconductor device surface. (Selector
disposing the surface in a plasma containing o-negative species to introduce such electronegative species into the semiconductor surface, wherein the non-electronegative species has at least a surface portion of the semiconductor surface having electronegative species therein. Depositing a dynamic layer. By placing the surface in a plasma with a bias greater than 0 volts, the electronegative species are incorporated into the thick surface portion of the semiconductor surface that provides a relatively high negative surface potential on the exposed surface. It is believed that passivating a semiconductor surface, such as gallium arsenide, with materials such as silicon nitride, silicon monoxide, silicon dioxide, silicon oxynitride, polyimide, etc., removes negative charges from the surface. It is believed that removing the negative charge from the semiconductor surface has the effect of reducing the reverse breakdown voltage characteristics between the electrodes of the device when incorporating the passivation layer. By incorporating the electronegative species into the semiconductor surface, the negative charge on the surface can be maintained after passivation to minimize the reduction in reverse breakdown voltage.

In accordance with a further aspect of the present invention, a field effect transistor is provided between a source electrode and a drain electrode disposed on a doped semiconductor layer, and between the source electrode and the drain electrode. And a support for supporting an active layer comprising a III-V semiconductor material having a doped semiconductor layer and having a gate electrode disposed on the Schottky barrier in contact with the layer. The surface portion of the active layer located between the source and drain electrodes contains electronegative species incorporated into the surface to a thickness greater than 35 °. Next, a passivating material layer is disposed over at least a surface portion of the active layer to passivate the active layer. The above arrangement stabilizes the surface potential of the exposed III-V material by providing a relatively thick surface portion with which electron-negative species are incorporated, and disposes a passivation layer on the surface portion. In doing so, the passivation layer ensures that the surface potential of the exposed layer is not significantly more positive. Thus, a passive field effect transistor having a reverse breakdown voltage comparable to that of the transistor before receiving the passivation layer is provided.

The above detailed description of the invention as well as the present invention itself can be more completely understood from the following detailed description of the drawings, in which: FIGS. FIG. 4A is a series of cross-sectional views illustrating a step of providing a passivation layer on a metal semiconductor field effect transistor having a dielectric breakdown voltage measured for individual devices in each one of the lots. FIG. 4B is a plot of reverse breakdown voltage (in volts) versus lot number before and after surface treatment showing statistics; FIG. 4B is a plot of transistor lot numbers for the treated and control devices after passivation. 7 is a plot of the change in reverse breakdown voltage of the device depending on the device substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1-3, steps in the fabrication of a field effect transistor having a passivation layer thereon are described.

FIG. 1 shows gallium arsenide or other suitable I
A metal semiconductor field effect transistor 10 (MESFE) supported on a semi-insulating support 12 containing a II-V material
T) is shown. Although the invention described herein uses MESFETs as field effect transistors, it is clear that other semiconductor devices, such as, for example, heterojunction bipolar transistors, as well as electron mobility transistors and irregular Other field effect transistors such as (pseudomorphic) electron mobility transistors can also be used. Further, in the practice of the present invention, other II
Other semiconductor materials such as IV materials can be used.

Returning to the discussion regarding FIG. MESFET 10 supported on a support 12 containing semi-insulating gallium arsenide
It is shown. The MESFET 10 includes a dopant ion such as a silicon ion to which a voltage is applied.
s) into the surface of the support 12 and annealing the lattice damage caused by the implantation to activate the ions, i.e., the implants used in the art. An active layer comprising doped gallium arsenide.

The active layer 14 is generally 1 × 10 ^{16 to} 5
Dope to a concentration of x10 ¹⁷ atoms / cc. Alternatively,
The active layer 14 may be provided using other techniques, such as molecular beam epitaxy, metal organic reactant vapor deposition epitaxy, and etched epitaxial growth layers provided by other methods. Arranged on layer 14 is an optional pair of contact layers 16a, 16b, typically comprising a highly doped semiconductor material doped to a concentration of 2 × 10 ¹⁷ atoms / cc and above. When the layers 16a and 16b are omitted, the source electrode and the drain electrode 22 and 20 are formed on any of the contact layers 16a and 16b or the active layer 14, respectively.
Place. The source and drain electrodes 22, 20 may be of any type that, when disposed on the optimal contact layer 16a, 16b or the active layer 14, provide a low resistivity ohmic contact thereto as known in the art. Includes any conventional metallization method according to conventional methods. In the present invention, the contact layers 16a, 16b are formed by pocket implants into the portion of the active layer 14, as is also known as one of ordinary skill in the art. Also, although not shown in the figure, a layer 16 disposed away from the active region of the field effect transistor
An isolation zone using unused portions of a, 16b and the underlying 14 semi-insulator is also provided with the circuit. The area is
For example, it can be provided by implanting a species such as boron or oxygen, as is known in the art. Layer 14 provides a buried channel 15. M
As is commonly used for ESFET transistors,
The channel 15 is selectively etched to form the source electrode 2
2 controls the pinch-off voltage of the channel 15 existing between the drain electrode 2 and the drain electrode 20. A gate electrode 24 is also arranged in the buried channel portion 15. Gate electrode 24 includes a Schottky barrier forming metal and provides a Schottky barrier contact to active layer 14. Therefore, after the formation of the source, drain and gate electrodes, the portion 14 'of the active layer 14 is exposed or uncovered. It is important to passivate the part, and it is in this region that the passivation generally has a negative effect on transistor characteristics.

What has been described above is a general description of a metal semiconductor field effect transistor having a single gate finger disposed between a pair of source and drain regions. Obviously, it is contemplated that many other cells as described above could be used for other applications.

See FIG. A transistor 10 supported on a support 12 is placed in a plasma flux 30 containing a highly electronegative species, here O ₂ . Generally, in these temperatures, the device, at least about 15 minutes, generally at least 30 to 45 minutes, kept in O ₂ plasma. High electron-negative species that can be used alternatively include fluorine, chlorine, nitrogen, and sulfur. O
_{2 In} the presence of the plasma, the exposed surface portion 14 'of the exposed active area 14 is
To be converted to Thus, in the described example, gallium and arsenic oxide (s) are generated during the plasma treatment on the semiconductor material, here on all exposed portions 14 ', including GaAs.

Preferably, prior to placing the FET 10 in the plasma, the exposed active layer portion 14 'of the FET 10 is cleaned, particularly using an ammonium hydroxide treatment, to reduce the processing time associated with conventional processing steps. Eliminate any residual contamination. For example, one of the final steps performed when the transistor 10 is subjected to the secondary processing is a step of forming the gate electrode 24. At some point in the processing performed after forming the gate electrode 24, a resist layer (not shown) of the resist layer support 10 used to mold the area for the gate electrode 24. From the surface, specifically from the surface of the exposed portion 14 ′ of the active area 14. Typically, these exposed portions are removed using an oxygen plasma treatment that places the device in an oxygen plasma apparatus (not shown) for up to 3 or 4 minutes. Small irregular oxides may form as a result of exposure to the aforementioned plasma. Generally, this layer, if present, will have a somewhat irregular thickness, with a thickness of 15 ° or less. Preferably, before depositing the passivation layer, it is desirable to remove the above oxides to provide a uniform thickness oxide of greater than about 25 °, as follows. Therefore, the above-mentioned cleaning step is performed before placing the field-effect transistor in the oxygen plasma.
It is preferred to do so.

The transistor 10, whether clean or not, is allowed to operate for at least about 15 minutes, preferably 35 minutes.
~ 45 minutes or more, in the present invention for 45 minutes,
Processed by exposure to a pure oxygen plasma environment,
Grow an oxide having a uniform thickness, typically 25-100 °, as estimated from measurement of the surface reflection angle (Δ) with an ellipsometer. An ellipsometer is used to measure the phase difference of the light beam as indicated by the reflection of the light beam from the wafer surface. For the present invention, the phase angle Δ for a gallium arsenide surface completely free of oxide is considered to be about 168 °. For a device according to the invention, its phase angle Δ will generally be less than about 162 °.

The oxygen plasma is provided in a conventional barrel plasma reactor (ie, an etching system). Typical conditions are: 1.7 Torr internal pressure of the reactor, 50 S oxygen flow rate.
CCM, RF power at 13.56 MHz
Give 00 watts. It is generally desirable to have a slow growing oxide layer 36 that is thicker than can be provided by growing the oxide layer over several minutes. After the formation of the gate electrode 24, the slow-growth oxide film 36 changes the photoresist layer from the active layer 14 to O.
_{2 It} is generated by accident when it is removed using plasma. Generally, the plasma deposition is for at least 20 minutes, preferably up to 45 minutes or longer, and generally preferably from 35 to
Should take 45 minutes. It is believed that the above time provides an oxide that includes a region about 25-35 ° thick.

An alternative to incorporating electron-negative species into the surface portion 14 'is to use a reactive ion etcher containing a plasma of the selected electron-negative species.
There is a method of disposing the transistor 10 therein. In particular, it is believed that using the above method provides a thick layer with a highly uniform thickness of the oxide-containing surface and a thickness greater than about 40-100 ° and more. Typical growth conditions for the O ₂ species are 100 mTorr internal pressure, 200 input power.
Self-bias between the O ₂ flow rate 95 sccm, the plasma and the support surface in watts is greater than 0 volts, and preferably from 50 to 80 volts, and the support surface,
It is more negative than plasma. The time is generally 30 minutes. The method, as described in Example, electronegative species such as O ₂ is grown thick layer being mixed. In general, oxide-containing films 34 having a thickness of 35-100 ° or more are expected under the above general conditions. Generally, the preferred thickness is 75 °.

In the first method described above, in a conventional barrel plasma reactor, a relatively high pressure plasma is provided in the barrel to reach a maximum depth of about 30-35 ° with GaAs.
oxidizes the surface. No bias potential can be applied between the plasma and the support surface.

In a reactive ion etching system, a relatively low pressure planar plasma discharge is provided between a pair of planar electrodes having a GaAs support disposed therein. A bias potential is provided between the upper electrode of the pair of electrodes and the support. Due to this bias potential, compared to the oxidation reaction driving force that is possible in the barrel plasma method,
It provides an electric field gradient that produces a greater oxidation driving force. In the latter method, the thickness of the oxide region is about 75 °
And more are possible. Also, in reactive ion reactor systems, the placement of the wafer between a pair of spaced parallel electrodes provides a more uniform thickness with respect to the oxidized surface.

See FIG. After O ₂ treatment, the treatment portion 36 of the active layer 14, is encapsulated with a passivation material layer 36. Passive layer 3
In the present invention, 6 extends over the source electrode 20 and the drain electrode 22 as shown in the figure. In particular, the interface region between active layer 14 and passivation layer 36 (i.e., processing region 34) includes a thin oxide-containing surface portion. The layer is layer 34, which comprises GaAs and oxides of Ga and As. The presence of oxygen in the thin oxide film 34 between the source electrode and the gate electrode, and between the drain electrode and the gate electrode,
It is considered that the reverse breakdown voltage characteristics between the drain / gate and between the drain / source are improved. Exposed GaAs
Breaking bonds at the surface of s provides a surface with a negative surface potential. The negative surface potential of GaAs before passivation is responsible for the reverse breakdown voltage. In general, after passivation, the negative charge present on the surface of the passivation active layer is reduced, while at the same time the reverse breakdown voltage is reduced. The presence of oxygen or a strong electronegative element as used in the present invention maintains a relatively high negative surface potential in region 34 even after passivation. Thus, compared to a passivated FET without surface 34, FET1
0 'has a relatively high reverse breakdown voltage characteristic.

The present invention provides a passivation layer 36 on the wafer of the field effect transistor 10 of FIG. 2 by placing the wafer in a plasma deposition system (not shown). Under the general conditions for a plasma deposition system, the system is 13.5
Operating at 6 megahertz, a mixture of silane, nitrogen, and ammonia is introduced into the system. The reference conditions during the plasma deposition of silicon nitride were: at a pressure of 0.65 Torr: the initial flow was a mixed vapor flow of 5% silane and 95% nitrogen at a flow rate of 220 SCCM; At 3.0 SCCM; and the tertiary stream is a pure oxygen vapor stream at a flow rate of 200 SCCM. A typical deposition temperature for a plasma system is 25 watts at a deposition power of 35 watts.
0 ° C. Generally, the thickness of the deposition layer 36 is 2000
Å (ie, 200 nanometers). At the time of vapor deposition, a stress of about 1 × 10 ⁹ dynes / cm ² is applied to silicon nitride, and the silicon nitride is appropriately compressed.

See FIGS. 4, 4A and 4B. The figure shows the drain / drain measured at a channel current of 1 amp / mm.
Set statistics of reverse breakdown voltage for gate connection (set
statistics) are shown for two sets of field effect transistors before and after passivation. For example, referring to the set statistic 40 as an example, the plot shows a maximum 42 and a minimum 4 for reverse breakdown voltage.
4, median 46, upper quadrant 47 and lower quadrant 48
Is shown. The above respective values are those obtained for a set of field effect transistors of the present invention before passivation and surface treatment. The first set 40 shows a breakdown voltage of about 17.5 to 22.5 volts before passivation. FE fabricated secondarily from the same wafer as FET set 40 to be processed
The statistical set 50 of the control set of Ts is about 18-21.
7 shows a breakdown voltage characteristic of 7 volts. The wafer uses the FE used to obtain the set statistic 40 data.
Prior to O ₂ treatment and passivation for Ts, and before passivation without O ₂ plasma treatment for FETs used to obtain set statistics 50 data, aqueous ammonium hydroxide (NH ₃ OH) Washed in. NH ₃₀
The value measured by the ellipsometer after washing with H was 1
65.3 °, a value indicating a surface with residual oxide of about 10 ° thick. FET set 42 has been treated with O ₂ plasma for 35 minutes in a barrel plasma reactor and has an oxide-containing layer approximately 30 ° thick. The phase angle Δ measured by the ellipsometer was 159 °. After passivation with 2,000Å silicon nitride,
The set statistics 40 'of the oxygen plasma treated device are:
It shows a breakdown voltage characteristic of about 17 to 21 volts.
The set statistic 50 'indicates that after cleaning in NH ₃ 0H as described above, the O ₂ plasma
i in ₂ N ₃ illustrates a passivated characteristics of the control FETs. The set statistic 50 'of the control FETs after passivation is:
It shows a very low reverse breakdown voltage of about 12.5 to 15 volts. FIG. 4B shows the difference between the two breakdown voltage ranges.
Shown in FIG. 4B shows the range of variation of the reverse breakdown voltage for the device with the device substrate as measured before and after passivation. O ₂ plasma-treated FETs
Had a variation in reverse breakdown voltage from about +0.5 to -2.5 volts as shown in the set statistic 40 ". Control FETs not subjected to oxygen plasma treatment
s is the set statistic 50 ″ for the reverse breakdown voltage characteristic.
Had a variation range of about -4.5 to -7 volts, as shown in FIG. Therefore, comparing FIGS. 4A and 4B, it can be seen from FIG. 4B that the breakdown voltage after passivation is at least on average about 4 volts when the oxygen plasma treatment is performed compared to the case without the treatment. Is found to increase.

Although the use of O ₂ as an electronegative species has been mainly described, other electronegative species are also suitable. For example, electronegativity of fluorine (e _n) = 4.0, the
It is more electronegative than O ₂ (en = 3.5) and is considered to be a suitable alternative. In gallium arsenide,
Arsenic, high electron negativity is in its two elements (e _n =
2.0). Therefore, any suitable species having an electronegativity of e _n > 2.0 should be used to provide some improvement. Carbon with electronegativity e _n = 2.5 is another alternative. In GaAs,
Carbon is a shallow donor dopant
It is. However, when defining the doping concentration of the channel layer, it seems necessary to take the above fact into consideration.

[0026] Examples of another electronegative species than those described above, chlorine (Cl) e _n = 3.0, sulfur e _n = 2.5,
And nitrogen (N) e _n = 3.0 and the like.

While the preferred embodiment of the invention has been described, it will be apparent to those skilled in the art that other embodiments incorporating the concepts of the invention may be used. Accordingly, these embodiments are not to be limited by the disclosed embodiments, but rather are to be limited only by the spirit and scope of the appended claims.

[Brief description of the drawings]

FIG.

FIG. 2

FIG. 3 is a series of cross-sectional views illustrating the steps of providing a passivation layer on a metal semiconductor field effect transistor having an exposed surface portion prepared according to the present invention.

FIG. 4A is a plot of reverse breakdown voltage (in volts) versus lot number, showing the breakdown voltage measured before and after surface treatment for individual devices in each one of the lots. Shows statistics. Also,
FIG. 4B is a diagram plotting the change in the reverse breakdown voltage of the device depending on the device substrate with respect to the transistor lot numbers of the processing device and the control device after passivation.

Continued on the front page (72) Inventor Barratt Patel, New Hampshire, USA 03063, Chatham Street, Nashua, 12 (72) Inventor Herman Stats, USA 01778, Massachusetts, USA Weyland, Barney Hill Road 10 (56) References JP-A-2-27725 (JP, A) JP-A-61-129833 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/337 H01L 21/338 H01L 27 / 095 H01L 29/778 H01L 29/80-29/812

Claims (28)

(57) [Claims] 1. The method according to claim 1, wherein a gap between the plasma and the surface of the semiconductor support is zero.
III-V self-biasing at potentials exceeding volts
The support of the semiconductor material of the group III is an electronegative species selected from the group consisting of fluorine, nitrogen, chlorine, and sulfur (electro-neg
placing the electron-negative species into a surface portion of the semiconductor substrate by placing the electron-negative species in a plasma that includes the electron-negative species; and optionally on the surface portion of the semiconductor support having the electron-negative species. Depositing a passivation layer consisting of a non-III-V semiconductor oxide of claim III, comprising: preparing a III-V semiconductor surface receiving the passivation layer. 2. The method of claim 1, wherein during the positioning step, the self-bias between the plasma and the semiconductor support is between 50 and 80 volts, and the support is negative for the plasma. 3. The method of claim 1, wherein said passivation layer is selected from the group consisting of silicon nitride, silicon dioxide, silicon monoxide, silicon oxynitride, and polyimide. 4. The method of claim 2, wherein the passivation layer is silicon nitride,
The method of claim 1, wherein the group IV material is GaAs. 5. The method according to claim 1, wherein the distance between the plasma and the surface of the semiconductor support is zero.
III-V self-biasing at potentials exceeding volts
Placing a support of a semiconductor material of group III in a plasma containing an electron-negative species selected from the group consisting of fluorine, nitrogen, chlorine and sulfur, and introducing the electron-negative species to a surface portion of the semiconductor support And e. Depositing a passivation layer on said surface portion of the semiconductor support having electronegative species. A method of preparing a III-V semiconductor surface receiving a passivation layer. 6. The method of claim 5, wherein said III-V material is GaAs. 7. The method according to claim 5, wherein the electronegative species is fluorine. 8. The method of claim 7, wherein said III-V material is GaAs. 9. An active layer including a group III-V material having a dopant concentration, comprising: a source electrode and a drain electrode disposed on the active layer; and an active layer formed between the source electrode and the drain electrode. A support for supporting with a gate electrode disposed in Schottky barrier contact with the layer; the III-V material having a thickness greater than 35 ° disposed between the drain electrode and the gate electrode; ,
A field effect transistor comprising: a surface portion of the active layer including an electronegative species selected from the group consisting of chlorine, nitrogen, and sulfur; and a layer of a passivating material disposed on at least the surface portion of the active layer. . 10. The field effect transistor according to claim 9, wherein said surface portion has a substantially uniform thickness. 11. The field effect transistor according to claim 9, wherein said surface portion has a uniform thickness of 35 to 100 °. 12. The field effect transistor of claim 9, wherein said surface portion has a uniform thickness of about 75 °. 13. The field effect transistor of claim 9, wherein said passivation layer is selected from the group consisting of silicon nitride, silicon dioxide, silicon monoxide, silicon oxynitride, and polyimide. 14. An active layer containing a group III-V material having a dopant concentration, comprising: a source electrode and a drain electrode disposed on the active layer; and an active layer formed between the source electrode and the drain electrode. A support for supporting with a gate electrode disposed in contact with a Schottky barrier; said group III-V material; and an electronegative species selected from the group consisting of fluorine, chlorine, nitrogen and sulfur. A field effect transistor comprising: a surface portion of the active layer disposed between the drain electrode and the gate electrode; and a passivation material layer disposed on at least the surface portion of the active layer. 15. The field effect transistor according to claim 14, wherein said surface portion has a substantially uniform thickness. 16. The field effect transistor according to claim 14, wherein said surface portion has a uniform thickness of 25 to 100 °. 17. The field effect transistor according to claim 14, wherein said surface portion has a uniform thickness of about 75 °. 18. The field effect transistor according to claim 16, wherein said electronegative species is fluorine. 19. The field effect transistor of claim 18, wherein said passivation layer is selected from the group consisting of silicon nitride, silicon dioxide, silicon monoxide, silicon oxynitride, and polyimide. 20. The field effect transistor according to claim 18, wherein said passivation layer is silicon nitride. 21. A method of fabricating a metal semiconductor field effect transistor having a semiconductor surface receiving a passivation layer, comprising: arranging an active layer comprising a group III-V material having a dopant concentration on the active layer. And a gate electrode disposed between the source electrode and the drain electrode and in contact with the active layer in Schottky barrier contact between the source electrode and the drain electrode, the active layer including at least the gate electrode and the drain electrode. Having a semiconductor surface exposed between
A support was prepared; exposed to a plasma containing an electronegative species selected from the group consisting of fluorine, nitrogen, chlorine, and sulfur, having a self-bias potential greater than 0 volts between the plasma and the surface. Arranging a semiconductor surface to contain an electronegative species III
Providing a surface layer portion of the exposed surface of the Group V material; depositing a passivation layer over the surface layer portion of the semiconductor and the electronegative species. 22. The method of claim 21, wherein during the disposing step, the self-bias between the plasma and the semiconductor support is between 50 and 80 volts, and the support is negative for the plasma. 23. The method of claim 21, wherein said passivation layer is selected from the group consisting of silicon nitride, silicon dioxide, silicon monoxide, silicon oxynitride, and polyimide. 24. The method of claim 26, wherein said passivation layer is silicon nitride. 25. The method of claim 23, wherein said III-V material is gallium arsenide. 26. The method of claim 25, wherein said passivation layer is selected from the group consisting of silicon nitride, silicon dioxide, silicon monoxide, silicon oxynitride, and polyimide. 27. The method of claim 26, wherein said passivation layer is silicon nitride. 28. A method of manufacturing a metal semiconductor field effect transistor having a semiconductor surface receiving a passivation layer, comprising: an active layer comprising a group III-V material having a dopant;
A source electrode and a drain electrode arranged in ohmic contact on the active layer, a gate electrode arranged between the source electrode and the drain electrode in Schottky barrier contact with the active layer, and the active layer has at least Preparing a support having a semiconductor surface exposed between a gate electrode and a drain electrode; removing at least a semiconductor oxide surface between the gate electrode and the drain electrode; 0 volts between the plasma and the surface The group consisting of fluorine, nitrogen, chlorine and sulfur having a self-bias potential greater than
Placing the exposed semiconductor surface in a plasma containing an electron-negative species selected from the group consisting of III-
Providing a surface layer portion of the exposed surface of the group V material; depositing a passivation layer over the semiconductor and electronegative species surface layer portion.