JPS6390124A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6390124A JPS6390124A JP23563286A JP23563286A JPS6390124A JP S6390124 A JPS6390124 A JP S6390124A JP 23563286 A JP23563286 A JP 23563286A JP 23563286 A JP23563286 A JP 23563286A JP S6390124 A JPS6390124 A JP S6390124A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- heat
- heat treatment
- type
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000010438 heat treatment Methods 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000005355 Hall effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003028 elevating effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000010979 ruby Substances 0.000 description 1
- 229910001750 ruby Inorganic materials 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子の製造方法、特に半導体の伝導形制
御方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for controlling conduction type of a semiconductor.
従来より、半導体結晶に不純物を注入し、その後該結晶
に熱処理を施すことにより能動層を形成するいわゆるイ
オン注入技術は広く半導体素子の製造に利用されている
。ところで、従来の技術による伝導形制御の方法におい
て、伝導形の異なる能動層を同一ウェハ上に形成する場
合は、その能動層の種類だけの不純物イオン注入プロセ
スを必要とした。Conventionally, so-called ion implantation technology, in which an active layer is formed by implanting impurities into a semiconductor crystal and then subjecting the crystal to heat treatment, has been widely used in the manufacture of semiconductor devices. By the way, in conventional conduction type control methods, when active layers of different conductivity types are formed on the same wafer, an impurity ion implantation process is required only for the type of active layer.
このため、実際の半導体素子製造工程は複雑になり、小
さな回路変更を行う場合でも膨大な労力を必要とした。For this reason, the actual semiconductor device manufacturing process has become complicated, and even when making small circuit changes, an enormous amount of labor is required.
本発明の目的は工数の大幅な削減に有効で、かつ新規・
な能動層の形成法を提供することにある。The purpose of the present invention is to be effective in significantly reducing man-hours, and to create new and
An object of the present invention is to provide a method for forming an active layer.
本発明は両性不純物をイオン注入したＧａＡｓ結晶を熱
処理することによりｎ形伝導層を形成する第１の工程と
、前記ｎ形伝導層の局所領域の温度を、禁制帯幅より大
きな光子エネルギーのレーザ光を照射することにより前
記熱処理温度以上に高め、その照射部にｐ形伝導領域を
形成する第２の工程とを有することを特徴とする半導体
素子の製造方法である。The present invention includes a first step of forming an n-type conductive layer by heat-treating a GaAs crystal into which amphoteric impurities are ion-implanted, and a laser beam with a photon energy larger than the forbidden band width to control the temperature of a local region of the n-type conductive layer. This method of manufacturing a semiconductor device is characterized by comprising a second step of elevating the temperature to the heat treatment temperature or higher by irradiating light and forming a p-type conductive region in the irradiated portion.
■−■化合物半導体結晶中で■族元素は両性不純物とし
て振る舞い、■族すイトを占めた場合に。■-■ Group ■ elements behave as amphoteric impurities in compound semiconductor crystals, and when they occupy group ■ atoms.
はｎ形不純物となり、また■族すイトを占めた場合には
ｐ形不純物となることが知られている。従って、■族元
素の占めるサイトが制御できれば、伝導形を制御するこ
とができるものである。It is known that it becomes an n-type impurity, and when it occupies the group II group, it becomes a p-type impurity. Therefore, if the sites occupied by the group Ⅰ elements can be controlled, the conductivity type can be controlled.
ＧａＡｓ中の両性不純物Ｓｉを例にとって本発明の概念
を示す。第１図（ａ）は絶縁性ＧａＡｓ基板１１にＳＬ
を注入しイオン注入層１１１ を形成し、その上にＧａ
Ａｓの熱分解を防ぐ熱処理保護膜１２を成膜したウェハ
の断面図である。そのウェハを２０分間程度、８５０℃
以下で熱処理を施すと、Ｓｉは■族すイトを占め。The concept of the present invention will be explained by taking as an example the amphoteric impurity Si in GaAs. FIG. 1(a) shows an SL on an insulating GaAs substrate 11.
An ion-implanted layer 111 is formed by implanting Ga.
FIG. 2 is a cross-sectional view of a wafer on which a heat treatment protective film 12 for preventing thermal decomposition of As has been formed. The wafer was heated to 850°C for about 20 minutes.
When heat treatment is performed below, Si occupies the group II group.
第１図（ｂ）に示すように、イオン注入層はｎ形伝導を
示しｎ形伝導層１１２が形成される。その後、第１図（
ｃ）に示すように、禁制帯幅より大きな光子エネルギー
のレーザ光りを照射することによりｎ形伝導層１１２の
局所領域の温度を前記熱処理温度より高い温度に加熱す
るｍ Ｓｉはこの熱処理によって■族すイトに移りｐ形
不純物となるため、第１図（，１）に示すように、レー
ザ光りを照射した部分にはｐ形伝導層１１３が形成され
る。このように、本発明は一度のイオン注入を行った半
導体に二度の熱処理を施すことにより、同一半導体上に
ｎ形及びｐ形の伝導層を形成するものである。As shown in FIG. 1(b), the ion implantation layer exhibits n-type conduction, and an n-type conduction layer 112 is formed. After that, see Figure 1 (
As shown in c), the temperature of the local region of the n-type conductive layer 112 is heated to a temperature higher than the heat treatment temperature by irradiating laser light with a photon energy larger than the forbidden band width. The p-type conductive layer 113 is formed in the portion irradiated with laser light, as shown in FIG. 1 (, 1). In this manner, the present invention forms n-type and p-type conductive layers on the same semiconductor by subjecting a semiconductor to which ions have been implanted once to heat treatment twice.
以下、本発明の実施例について図面を用いて詳細に説明
する。第２図は絶縁性ＧａＡｓ基板にＳｉを１００Ｋｅ
Ｖにて５Ｘ１０”ａｍ″″２イオン注入し、その上に６
００℃でＡＱＮを１０００人成膜したウェハを２０分間
、８００’Ｃ以上で熱処理したときに活性化した電子濃
度と熱処理温度の関係を示した図である。９５０℃以上
で熱処理すると、ｐ形伝導を示すことが分かった。Embodiments of the present invention will be described in detail below with reference to the drawings. Figure 2 shows 100Ke Si on an insulating GaAs substrate.
5X10"am""2 ion implantation at V, and 6
FIG. 3 is a diagram showing the relationship between the concentration of activated electrons and the heat treatment temperature when a wafer on which 1000 AQN films were formed at 00C was heat treated at 800'C or higher for 20 minutes. It was found that when heat treated at 950°C or higher, p-type conduction was exhibited.
この結果を基に、第３図（ａ）に示す構造の試料を作製
した。すなわち、絶縁性ＧａＡｓ基板３１にＳＬを１０
０ＫｅＶにて５ Ｘ ｔｏ” ｃｘｍ−”イオン注入し
、イオン注入層３１１を形成し、その上に６００℃でＡ
ＱＮ層３２を１０００人成膜した。まず、そのウェハを
２０分間、８５０’Ｃで熱処理することにより、第３図
（ｂ）に示した約３Ｘ１０”ａ１″″２の電子濃度を有
するｎ形伝導層３１２を形成しの一部に波長２９４３人
、出力４ｗのルビーレーザ光りを照射し熱処理した６レ
一ザ照射部の温度は９５ “０℃以上であることを確
認した。第３図（ｄ）に示したレーザ照射部３１３はｐ
形伝導を−示すことをホール効果測定によって確認した
。Based on this result, a sample having the structure shown in FIG. 3(a) was prepared. That is, 10 SLs are placed on the insulating GaAs substrate 31.
5X to"cxm-" ion implantation was performed at 0 KeV to form an ion implantation layer 311, and A
The QN layer 32 was deposited by 1000 people. First, by heat-treating the wafer at 850'C for 20 minutes, an n-type conductive layer 312 having an electron concentration of about 3 x 10"a1"2 as shown in FIG. 3(b) is formed in a part of the wafer. It was confirmed that the temperature of the 6-laser irradiation area, which was heat-treated by irradiating ruby laser light with a wavelength of 2943 and an output of 4 W, was 95°C or higher. The laser irradiation section 313 shown in FIG. 3(d) is
It was confirmed by Hall effect measurement that it exhibits shaped conduction.
以上、実施例においてはＧａＡｓ中の両性不純物Ｓｉを
例に挙げて示したが１本発明による半導体素子の製造方
法は、ＧａＡｓ中のその他の両性不純物、例えばＧｅな
どにも適用できるばかりではなく、他のｍ−■化合物半
導体材料、たとえばＩｎＰ系などにも適用できることは
明らかである。In the above embodiments, the amphoteric impurity Si in GaAs has been exemplified; however, the method for manufacturing a semiconductor device according to the present invention is not only applicable to other amphoteric impurities in GaAs, such as Ge, but also It is clear that the present invention can also be applied to other m-■ compound semiconductor materials, such as InP-based materials.
以上のように本発明によれば、−度のイオン注入を行っ
た半導体に二度の熱処理を施すことにより、同一半導体
上にｎ形及びｐ形の伝導層を形成するので、従来のよう
に複雑な工程が必要でないばかりではなく、回路変更な
どを行う場合でも膨大な労力を必要としないという効果
を有するものである。As described above, according to the present invention, an n-type and a p-type conductive layer are formed on the same semiconductor by performing heat treatment twice on a semiconductor that has been ion-implanted to a certain degree. Not only does it not require complicated processes, but it also has the effect of not requiring a huge amount of effort even when changing the circuit.
第１図（ａ） 、 （ｂ） 、 （ｃ） 、 （ｄ）は
本発明により半導体の伝導形を制御する方法の概念を示
す断面図、第２図はＡＱＮ層をＧａＡｓ基板の熱処理保
護膜として用いた場合の活性化電子濃度と熱処理温度の
関係を示す図、第３図（ａ） 、 （ｂ） 、 （ｃ）
、 （ｄ）は本発明の実施例を示す断面図である。
１１．３１・・・絶縁性ＧａＡｓ基板 １１１，３１１
・・・イオン注入層１１２．３１２・・・ｎ形伝導層
１１３・・・ｐ形伝導層１２・・・熱処理保護膜
３１３・・・レーザ照射部３２・・・ＡＱＮ層Figures 1 (a), (b), (c), and (d) are cross-sectional views showing the concept of the method of controlling the conductivity type of a semiconductor according to the present invention, and Figure 2 is a cross-sectional view showing the concept of the method for controlling the conductivity type of a semiconductor according to the present invention. Figures 3 (a), (b), (c) showing the relationship between activated electron concentration and heat treatment temperature when used as
, (d) is a sectional view showing an embodiment of the present invention. 11.31... Insulating GaAs substrate 111,311
...Ion implantation layer 112.312...N-type conduction layer
113...p-type conductive layer 12...heat treatment protective film
313... Laser irradiation part 32... AQN layer
Claims (1)
理することによりｎ形伝導層を形成する第１の工程と、
前記ｎ形伝導層の局所領域の温度を、禁制帯幅より大き
な光子エネルギーのレーザ光を照射することにより前記
熱処理温度以上に高め、その照射部にｐ形伝導領域を形
成する第２の工程とを有することを特徴とする半導体素
子の製造方法。(1) a first step of forming an n-type conductive layer by heat-treating a GaAs crystal into which amphoteric impurities have been ion-implanted;
a second step of increasing the temperature of the local region of the n-type conductive layer to a temperature higher than the heat treatment temperature by irradiating a laser beam with a photon energy larger than the forbidden band width, and forming a p-type conductive region in the irradiated area; A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23563286A JPS6390124A (en) | 1986-10-02 | 1986-10-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23563286A JPS6390124A (en) | 1986-10-02 | 1986-10-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6390124A true JPS6390124A (en) | 1988-04-21 |
Family
ID=16988892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23563286A Pending JPS6390124A (en) | 1986-10-02 | 1986-10-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6390124A (en) |
-
1986
- 1986-10-02 JP JP23563286A patent/JPS6390124A/en active Pending
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