JPS6119103B2 - - Google Patents

Info

Publication number
JPS6119103B2
JPS6119103B2 JP54140596A JP14059679A JPS6119103B2 JP S6119103 B2 JPS6119103 B2 JP S6119103B2 JP 54140596 A JP54140596 A JP 54140596A JP 14059679 A JP14059679 A JP 14059679A JP S6119103 B2 JPS6119103 B2 JP S6119103B2
Authority
JP
Japan
Prior art keywords
heat treatment
semiconductor substrate
sputtering
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54140596A
Other languages
Japanese (ja)
Other versions
JPS5664444A (en
Inventor
Toshio Sonobe
Yukio Tsuzuki
Kunihiko Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP14059679A priority Critical patent/JPS5664444A/en
Publication of JPS5664444A publication Critical patent/JPS5664444A/en
Publication of JPS6119103B2 publication Critical patent/JPS6119103B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/2636Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)

Description

【発明の詳細な説明】 本発明は電気特性の優れた半導体装置の製造方
法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device with excellent electrical characteristics.

一般に、半導体装置は、半導体基板中に選択的
に原子価の異なる元素を熱的または物理的にドー
プする工程と、所望の機能を構成するための配線
金属を作成する工程と、必要に応じて、半導体基
板表面を絶縁薄膜で覆うパツシベーシヨン工程と
を経て製造されるのは周知の通りである。上記の
各工程の詳細は、製造する半導体装置の種類によ
つてそれぞれ個別の条件を設定するのが一般的で
ある。その製造工程の技術として、半導体基板中
にドープする不純物元素の量を精密に制御する必
要から生まれたイオン注入技術が、また、配線金
属作成時の汚染を避けるためから電子ビーム蒸着
技術が、また特殊な合金配線薄膜作成の要求や機
械的性質の良好な薄膜を作成するための要求から
スパツタリング技術が、一般化してきた。また、
ごく最近では、サブミクロン加工の基本的技術と
しての電子線あるいはX線露光技術も生み出され
た。これらの個々の技術は、それぞれに半導体装
置の性能の再現性、信頼性、また単位素子の集積
化に不可決なものとなりつつある。
In general, semiconductor devices are manufactured through a process of selectively thermally or physically doping elements with different valences into a semiconductor substrate, a process of creating a wiring metal to configure a desired function, and a process of doping the semiconductor substrate with elements of different valences, as necessary. It is well known that semiconductor devices are manufactured through a passivation process in which the surface of a semiconductor substrate is covered with an insulating thin film. For details of each of the above steps, individual conditions are generally set depending on the type of semiconductor device to be manufactured. The manufacturing process technology includes ion implantation technology, which was born from the need to precisely control the amount of impurity elements doped into the semiconductor substrate, and electron beam evaporation technology, which was developed to avoid contamination during the production of wiring metal. Sputtering technology has become popular due to the demand for producing special alloy wiring thin films and the demand for producing thin films with good mechanical properties. Also,
More recently, electron beam or X-ray exposure technology has been developed as a basic technology for submicron processing. These individual technologies are becoming increasingly critical to the reproducibility and reliability of the performance of semiconductor devices, as well as to the integration of unit elements.

しかしながら、これらの技術の多くは半導体基
板あるいは半導体基板と絶縁膜との界面に、多く
の格子欠陥や準位を発生させ、例えばバイポーラ
型トランジスタの電流増幅率を低下させたり、
PN接合の漏れ電流を増大させたり、また電界効
果型トランジスタの閾値電圧を増大させたりす
る、いわゆる損傷と称する悪影響をもたらすもの
である。そのため、半導体素子製造の各過程で、
これらの損傷を回復するための熱処理の方法が、
従来にも増して半導体装置の性能を高めるために
重要なものとなつてきたが、例えばラテラル型バ
イポーラトランジスタやサブストレート型バイポ
ーラ型トランジスタの電流増幅率などは、例えば
スパツタリングによる損傷を極めてうけ易く、単
純な熱処理を施すのみでは、たとえ転位やスクー
ル等の結晶欠陥のない半導体基板を用いても十分
な値まで回復させることは困難であつた。
However, many of these technologies generate many lattice defects and levels in the semiconductor substrate or the interface between the semiconductor substrate and the insulating film, which may reduce the current amplification factor of bipolar transistors, for example.
This has the adverse effect of so-called damage, such as increasing the leakage current of the PN junction and increasing the threshold voltage of the field effect transistor. Therefore, in each process of semiconductor device manufacturing,
The heat treatment method to recover these damages is
Although it has become more important than ever before to improve the performance of semiconductor devices, current amplification factors of lateral type bipolar transistors and substrate type bipolar transistors are extremely susceptible to damage due to sputtering, for example. It has been difficult to recover to a sufficient value by simply performing heat treatment, even if a semiconductor substrate free of crystal defects such as dislocations and schools is used.

本発明は前記の欠点を克服するための新規な熱
処理の方法を提供するものである。本発明によれ
ば、少なくとも1個以上の能動素子領域を形成し
た半導体基板を設け、その能動素子領域を形成し
た側の基板表面上にスパツタ処理にて薄膜層を形
成した後、この半導体基板に400〜550℃の温度雰
囲気中において第1の熱処理を施し、その後この
半導体基板に荷電粒子線または電離放射線または
電磁波を所定量照射し、次いで300〜500℃の温度
雰囲気中において再びこの半導体基板に第2の熱
処理を行なうことを特徴とする半導体装置の製造
方法を提案するものである。
The present invention provides a novel heat treatment method to overcome the above-mentioned drawbacks. According to the present invention, a semiconductor substrate on which at least one active element region is formed is provided, a thin film layer is formed by sputtering on the surface of the substrate on the side where the active element region is formed, and then the semiconductor substrate is A first heat treatment is performed in an atmosphere at a temperature of 400 to 550°C, and then a predetermined amount of charged particle beams, ionizing radiation, or electromagnetic waves is irradiated to this semiconductor substrate, and then this semiconductor substrate is heated again in an atmosphere at a temperature of 300 to 500°C. This invention proposes a method for manufacturing a semiconductor device characterized by performing a second heat treatment.

それによつて、本発明では、各種処理工程、と
りわけスパツタ処理工程において与えられた半導
体基板中の結晶欠陥等を解消して一層安定した基
板回復状態を得ることができ、スパツタ処理後の
熱処理だけで得られるものに比べて、格段に優れ
た電気特性を有する半導体装置が得られるように
なる。
As a result, in the present invention, it is possible to eliminate crystal defects, etc., caused in the semiconductor substrate during various processing steps, especially the sputter processing step, and obtain a more stable substrate recovery state, and only by heat treatment after the sputter processing. It becomes possible to obtain a semiconductor device having significantly superior electrical characteristics compared to the previously obtained semiconductor device.

以下、一実施例に基いて本発明を詳細に説明す
る。本発明に適用できる半導体装置は、少なくと
も1個以上の能動素子領域を有する半導体基板か
らなる装置である。以下、ラテラル型バイポーラ
トランジスタを有する半導体装置をその代表例と
して説明する。第1図に示されるのは、ラテラル
型トランジスタを備えた半導体装置の断面図であ
る。1は半導体基板本体で、エピタキシヤル成長
させたN型シリコン層2を有するものである。3
はP+型の分離層、4はエミツタ領域及びコレク
タ領域形成用のP型層で、N型層2と共にPNP型
トランジスタを構成してある。5はシリコン熱酸
化膜、6はアルミニウムからなる配線用金属膜
で、この場合電子ビーム蒸着技術を用いて形成し
その後熱処理を行なつてオーミツク接触をとつて
ある。7は絶縁被膜で、この場合スパツタリング
によつて二酸化硅素の被膜が形成してある。8は
電極取り出し孔である。
Hereinafter, the present invention will be explained in detail based on one example. A semiconductor device applicable to the present invention is a device including a semiconductor substrate having at least one active element region. A semiconductor device having a lateral bipolar transistor will be described below as a representative example. What is shown in FIG. 1 is a cross-sectional view of a semiconductor device including a lateral transistor. Reference numeral 1 denotes a semiconductor substrate body, which has an N-type silicon layer 2 grown epitaxially. 3
4 is a P+ type separation layer, and 4 is a P type layer for forming an emitter region and a collector region, which together with the N type layer 2 constitute a PNP type transistor. Reference numeral 5 indicates a silicon thermal oxide film, and reference numeral 6 indicates a wiring metal film made of aluminum, which in this case is formed using electron beam evaporation technology and then heat treated to establish ohmic contact. 7 is an insulating film, in this case a silicon dioxide film is formed by sputtering. 8 is an electrode extraction hole.

上記のような構成のトランジスタは、本発明の
一実施例によれば次のような方法によつて製造さ
れる。すなわち、所定の不純物拡散操作を終了
後、ベース、エミツタ、及びコレクタ用の各配線
用金属6を電子ビーム蒸着方法を用いて形成し、
その後熱処理を行なつてオーミツク接触をとつた
後、スパツタリングによつて二酸化硅素の被膜7
を形成する。そして必要な箇所を周知のホトエツ
チング技術によつて開孔し、アルミニウムからな
る配線用金属を露出させ、電極取り出し孔8を形
成する。その後、400〜550℃の熱雰囲気中で5〜
60分間の熱処理を行ない、続いて、例えばタング
ステン管球を用いて集積線量として20〜200mrad
程度のX線を半導体基板表面に照射し、然る後、
300〜500℃の熱雰囲気中で10〜〜60分間熱処理を
行なう。
According to one embodiment of the present invention, the transistor having the above structure is manufactured by the following method. That is, after completing a predetermined impurity diffusion operation, each wiring metal 6 for the base, emitter, and collector is formed using an electron beam evaporation method,
After that, a heat treatment is performed to establish ohmic contact, and then a silicon dioxide coating 7 is formed by sputtering.
form. Then, holes are opened at necessary locations using a well-known photoetching technique to expose the wiring metal made of aluminum and form electrode extraction holes 8. After that, 5~
Heat treatment for 60 minutes, followed by an integrated dose of 20-200 mrad, e.g. using a tungsten tube.
The surface of the semiconductor substrate is irradiated with X-rays of about
Heat treatment is performed for 10 to 60 minutes in a thermal atmosphere of 300 to 500°C.

ところで、配線用金属成形工程まで終了した半
導体素子基板に残留する安定または不安定な形の
様々な広義の欠陥、たとえば不純物元素のドーピ
ング時に発生する格子歪や熱歪、或は金属蒸着時
に発生する界面準位や、オーミツク接触をとるた
めの金属・半導体化合物と基板との格子のミスフ
イツトに起因する準位等が存在し、さらにスパツ
タリング工程に於ても新たな半導体基板あるいは
半導体基板と絶縁膜との界面に格子欠陥や準位が
発生し、本来、理論上期待される電気特性は得ら
れない。
By the way, there are a variety of stable or unstable defects that remain on semiconductor element substrates that have completed the wiring metal forming process, such as lattice strain and thermal strain that occur during doping with impurity elements, or defects that occur during metal evaporation. There are interface levels and levels caused by lattice misfit between the metal/semiconductor compound and the substrate to establish ohmic contact, and furthermore, in the sputtering process, there are Lattice defects and levels occur at the interface, and the electrical properties expected theoretically cannot be obtained.

しかし、上記実施例に示した方法によれば、は
じめの熱処理によつて残留する不安定な欠陥を準
安定な形に変換して他の安定な欠陥に近い状態に
もつていき、次いでX線照射によつて安定または
準安定な欠陥を同時に均一に分散させ、その後熱
的誘起欠陥の発生しない程度の比較的低い温度で
熱処理することによつて、表面および界面の格子
の再配列を行なわせしめることができ、従来の熱
処理の方法では得られなかつた優れた電気特性の
改善、たとえば電流増幅率や漏れ電流等の著しい
改善効果が得られるものである。
However, according to the method shown in the above example, the unstable defects remaining through the initial heat treatment are converted into a metastable form and brought into a state similar to other stable defects, and then X-ray Stable or metastable defects are uniformly dispersed at the same time by irradiation, followed by heat treatment at a relatively low temperature that does not generate thermally induced defects, thereby rearranging the lattice at the surface and interface. This makes it possible to obtain excellent electrical properties that could not be obtained by conventional heat treatment methods, such as significant improvements in current amplification factor and leakage current.

ここで、第2図に示す特性図は上記実施例に示
した各処理工程毎のトランジスタの電流増幅率及
びコレクタ・エミツタ間の逆方向漏れ電流の変動
を示すものである。第2図中、電流増幅率の変動
は等差関係で、また漏れ電流の変動は対数関係で
示してある。これによれば、配線用金属6の形成
後の電流増幅率を100としたとき、スパツタリン
グ工程で絶縁膜を形成して基板表面の保護を行な
うと、電流増幅率は約72%まで減少する。その後
熱処理すると約80%まで回復するが、単なる熱処
理のみの場合はここで工程終了としていたため、
約80%までの回復が限界であつた。それに対し、
本発明のように引き続いてX線照射することによ
つて、それは約38%のレベルまで減少するが、そ
の後の熱処理によつて115%程度まで大幅に回復
させることができた。一方、配線用金属6の形成
後のコレクタ・エミツタ間の逆方向漏れ電流を1
としたとき、スパツタリング工程後に熱処理を施
すだけの場合に比して、一坦熱処理し、次いでX
線照射とそれに続く熱処理を施すことにより漏れ
電流を格段に低下させることができた。
Here, the characteristic diagram shown in FIG. 2 shows the fluctuation of the current amplification factor and the reverse leakage current between the collector and emitter of the transistor for each processing step shown in the above embodiment. In FIG. 2, fluctuations in current amplification factor are shown in an arithmetic relationship, and fluctuations in leakage current are shown in a logarithmic relationship. According to this, when the current amplification factor after the formation of the wiring metal 6 is 100, if the substrate surface is protected by forming an insulating film in the sputtering process, the current amplification factor decreases to about 72%. After that, heat treatment will restore the recovery to about 80%, but if it was just heat treatment, the process would have ended at this point.
Recovery was about 80%. For it,
By successively irradiating with X-rays as in the present invention, it was reduced to a level of about 38%, but by subsequent heat treatment it was possible to significantly recover it to about 115%. On the other hand, the reverse leakage current between the collector and emitter after the wiring metal 6 is formed is 1
Compared to the case where heat treatment is only performed after the sputtering process, a single heat treatment is performed and then X
By applying radiation and subsequent heat treatment, we were able to significantly reduce the leakage current.

また、第3図はスパツタリング工程後の熱処理
を施さない場合の各工程毎の、トランジスタの電
流増幅率の変動を示すもので、第2図と同様に配
線用金属6の形成後の電流増幅率を100としてあ
る。この場合の熱処理後の電流増幅率は92%のレ
ベルにとどまつている。これに比べて第2図に示
すように、スパツタリング工程後に一坦熱処理を
施すと、電流増幅率の回復をより大きくすること
ができた。
In addition, FIG. 3 shows the variation in the current amplification factor of the transistor for each step when no heat treatment is performed after the sputtering step, and similarly to FIG. 2, the current amplification factor after the formation of the wiring metal 6 is shown. is set as 100. In this case, the current amplification factor after heat treatment remains at a level of 92%. In contrast, as shown in FIG. 2, when uniform heat treatment was performed after the sputtering process, the current amplification factor could be recovered more greatly.

なお、上記の実施例では、ラテラル型PNPトラ
ンジスタについて説明したが、これに限らずPN
接合を機能部分として利用するダイオードや他の
構造のトランジスタ等でも、あるいは表面電界効
果を利用する電界効果型トランジスタ等でも若干
効果の差はあるが、充分適用できる。また、その
半導体装置は単一素子構造でも、また複数素子を
有する複合構造でも同様に適用できる。
In the above embodiment, a lateral type PNP transistor was explained, but the PN transistor is not limited to this.
The present invention can be sufficiently applied to diodes that use junctions as functional parts, transistors with other structures, or field effect transistors that use surface field effects, although there are slight differences in effectiveness. Further, the semiconductor device can be similarly applied to either a single element structure or a composite structure having a plurality of elements.

また、上述の実施例では、半導体装置の表面保
護膜として二酸化硅素膜をスパツタリング法等で
形成したものについて説明したが、本発明はこれ
に限定されるものではなく、それ以外の表面保護
膜の形成方法や表面保護の材料によつて形成して
もよい。また、表面保護膜に代えて必要とする薄
膜層を有する半導体装置に対しても同様に適用で
きる。
Further, in the above embodiment, a silicon dioxide film was formed by sputtering or the like as a surface protection film of a semiconductor device, but the present invention is not limited to this, and other surface protection films may be used. It may be formed depending on the forming method or surface protection material. Further, the present invention can be similarly applied to semiconductor devices having a thin film layer required in place of the surface protective film.

また、上述の実施例ではタングステンターゲツ
トのX線管球を使用してX線照射を行う場合につ
いて述べたが、本発明はX線の線質には大きく依
存せず、X線源の種類を問わない。また、X線に
限らずγ線、電子線、紫外線等の他の電離放射
線、荷電粒子線及び電磁波であつても適用できる
ことを確認している。
Further, in the above embodiment, a case was described in which X-ray irradiation was performed using an X-ray tube with a tungsten target, but the present invention does not depend greatly on the quality of X-rays, and the type of X-ray source No question. Furthermore, it has been confirmed that the method is applicable not only to X-rays but also to other ionizing radiations such as gamma rays, electron beams, and ultraviolet rays, charged particle beams, and electromagnetic waves.

以上述べたように本発明では、少なくとも1個
以上の能動素子領域を形成した半導体基板を設
け、その能動素子領域を形成した側の基板表面上
にスパツタ処理にて薄膜層を形成した後、この半
導体基板に400〜550℃の温度雰囲気中において第
1の熱処理を施し、その後この半導体基板に荷電
粒子線または電離放射線または電磁波を所定量照
射することにより、それまでの処理工程において
与えられてきた、とりわけスパツタ処理工程で与
えられた各種の欠陥のうち不安定状態にあるもの
を準安定化し、その後の照射により半導体基板に
残留する安定または準安定な欠陥を再び破壊して
欠陥状態を均一に分散させるようにし、その後、
300〜500℃の範囲の温度雰囲気中においてその半
導体基板に再び熱処理を施すことによつて、基板
表面および界面の格子の再配列を効果的に行なわ
せ安定した基板回復状態を得ることができ、これ
によつてスパツタ処理後に単なる熱処理だけで得
られるものに比べて漏れ電流特性や電流増幅率な
どの点で格段に優れた電気特性をもつ半導体装置
が得られるようになるという優れた効果がある。
As described above, in the present invention, a semiconductor substrate on which at least one active element region is formed is provided, and a thin film layer is formed by sputtering on the surface of the substrate on the side where the active element region is formed. The semiconductor substrate is subjected to a first heat treatment in an atmosphere at a temperature of 400 to 550°C, and then the semiconductor substrate is irradiated with a predetermined amount of charged particle beams, ionizing radiation, or electromagnetic waves. In particular, it metastabilizes the unstable defects among the various defects caused in the sputtering process, and then destroys the stable or metastable defects remaining on the semiconductor substrate again by subsequent irradiation, making the defect state uniform. Try to disperse it, and then
By subjecting the semiconductor substrate to heat treatment again in a temperature atmosphere in the range of 300 to 500°C, the lattice on the substrate surface and interface can be effectively rearranged and a stable substrate recovery state can be obtained. This has the excellent effect of making it possible to obtain a semiconductor device with far superior electrical properties in terms of leakage current characteristics and current amplification factor, compared to those obtained by mere heat treatment after sputtering. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方法を利用したラテラル型トラ
ンジスタの要部断面図、第2図および第3図は、
第1図に示すラテラル型トランジスタの電気特性
を示す特性図である。 1……半導体基板本体、2……N型層、3……
P+型層、4……P型層、5……シリコン熱酸化
膜、6……配線用金属、7……薄膜層の要部をな
す絶縁被膜。
FIG. 1 is a sectional view of the main parts of a lateral type transistor using the method of the present invention, and FIGS. 2 and 3 are
FIG. 2 is a characteristic diagram showing electrical characteristics of the lateral transistor shown in FIG. 1; 1... Semiconductor substrate body, 2... N-type layer, 3...
P+ type layer, 4... P type layer, 5... Silicon thermal oxide film, 6... Wiring metal, 7... Insulating coating forming the main part of the thin film layer.

Claims (1)

【特許請求の範囲】[Claims] 1 少なくとも1個以上の能動素子領域を形成し
た半導体基板を設け、その能動素子領域を形成し
た側の基板表面上にスパツタ処理にて薄膜層を形
成した後、この半導体基板に400〜550℃の温度雰
囲気中において第1の熱処理を施し、その後この
半導体基板に荷電粒子線または電離放射線または
電磁波を所定量照射し、次いで300〜500℃の温度
雰囲気中において再びこの半導体基板に第2の熱
処理を行なうことを特徴とする半導体装置の製造
方法。
1. A semiconductor substrate with at least one active element region formed thereon is provided, a thin film layer is formed by sputtering on the surface of the substrate on the side where the active element region is formed, and then this semiconductor substrate is heated at 400 to 550°C. A first heat treatment is performed in a temperature atmosphere, and then this semiconductor substrate is irradiated with a predetermined amount of charged particle beam, ionizing radiation, or electromagnetic waves, and then a second heat treatment is performed on this semiconductor substrate again in a temperature atmosphere of 300 to 500°C. 1. A method of manufacturing a semiconductor device, characterized in that:
JP14059679A 1979-10-31 1979-10-31 Manufacture of semiconductor device Granted JPS5664444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14059679A JPS5664444A (en) 1979-10-31 1979-10-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14059679A JPS5664444A (en) 1979-10-31 1979-10-31 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5664444A JPS5664444A (en) 1981-06-01
JPS6119103B2 true JPS6119103B2 (en) 1986-05-15

Family

ID=15272366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14059679A Granted JPS5664444A (en) 1979-10-31 1979-10-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5664444A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5433920A (en) * 1977-08-19 1979-03-13 Sharp Corp Carburetor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5433920A (en) * 1977-08-19 1979-03-13 Sharp Corp Carburetor

Also Published As

Publication number Publication date
JPS5664444A (en) 1981-06-01

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