JPH02232970A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make an interface excellent and a storage region small in frequency dispersion and hysteresis by a method wherein an AlGaAs layer is formed on an operating layer, which is thermally treated. CONSTITUTION:An N<+>-InP contact layer 3 is formed on a part of a semi- insulating InP substrate 1 where an N-InP operating layer 2 and a source and a gate electrode are to be formed. Then, an Al0.3Ga0.7As layer 4 serving as a gate insulating film is made to grow. Then, an SiO2 film 5 containing P is formed to serve as a surface protective film at a heat treatment. lastly, a gate electrode 6, a source electrode 7, and a drain electrode 8 are provided for the formation of a FET. By the above manufacturing method, an interface level decreases or moves in an energitic manner through a thermal treatment executed after the formation of the films, so that an excellent interface can be obtained and a storage region can be made small in frequency dispersion and hysteresis.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device having an active layer made of a compound semiconductor containing In, and particularly to a method of manufacturing a semiconductor device having good interface characteristics.

[Conventional technology]

Metal-insulator-semiconductor (Mis)'t1 field effect transistor (FET) whose active layer is a compound semiconductor containing In
The manufacturing method will be explained using InP as an example.

FIG. 2 is a diagram showing a method of manufacturing a depletion mode InPMIS field effect transistor using a conventional manufacturing method. International Electron Device Meeting
ectron Device Meeting 198
6-P771), conventionally, the active layer 2 and the contact layer 3 are formed on a semi-absolute Q 1 n P substrate 1 by ion implantation and annealing, or by VPE, etc. [Fig. 2 (al,
(b)), and this is the gate insulating film /l/! GaA
After growing the s layer by MBE or the like [FIG. 2(C)], a gate electrode 6, a source electrode 7. By forming the drain electrode 8 [FIG. 2(d)], a field effect transistor has been realized.

[Problem to be solved by the invention]

FIG. 3 shows the gate bias dependence characteristics and static characteristics of the gate-source capacitance of the depletion mode I n P M I S field effect transistor manufactured by the conventional manufacturing method described above. Frequency dispersion is observed in the storage region, and the voltage indicating flat capacitance is shifted to the negative bias side. In addition, in FETs, an increase in source/drain current is observed. In MISFETs manufactured using conventional manufacturing methods, interface states still exist at the interface after growth, although they have been reduced, and this causes frequency division in the storage region and hysteresis in the capacitance-voltage characteristics. In addition, problems such as a shift in the flat voltage of the capacitance arise due to fixed charges that are thought to exist at the interface or in the insulating film.
Further, depletion mode FET characteristics are adversely affected in the form of an increase in drain current and difficulty in enhancement, and have a large impact on high frequency characteristics during large amplitude operation.

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned problems. [Means for Solving the Problems] The present invention uses a compound semiconductor containing In as an active layer, and on this active layer, an AlxGa t-xA s layer (however, 0≦
A method for manufacturing a semiconductor device in which X≦1) is characterized in that heat treatment is performed after forming the A It XQ a , -XAS layer. According to the present invention, the temperature of the heat treatment is preferably 600 to 850°C. [Function] In the conventional manufacturing method, the interface between InP, which is the active layer, and AIGaAS, which is the insulating layer, can be cleaned in the MBE chamber, so it can be cleaned better than other methods. but,
This is a regrown interface, and interface states are formed due to residual interfacial impurities. Even if continuous growth is performed or the interface is completely cleaned, there are 3
．． There is a 7% lattice misalignment, which creates defects and causes deterioration of properties at the interface. However, due to the heat treatment after film formation, which is the manufacturing method of the present invention, the interface states are reduced or moved energetically, a good interface is obtained, and the frequency dispersion in the accumulation region and hysteresis are reduced in the capacitance voltage characteristics. It became clear that it was getting smaller. Furthermore, the voltage shift that was thought to be caused by fixed charges disappeared, and good capacitance-voltage characteristics were obtained. Also, in terms of FET characteristics, improvements in drain current blockage and improvements in enhancement characteristics were observed. If the temperature of the heat treatment is too low, the effect will be small, and if it is too high, the interface will deteriorate, so the optimum temperature is 600 to 850°C. Furthermore, in order to prevent deterioration due to detachment of group V elements from the surface due to this heat treatment, Si
O. Alternatively, protect the surface with a PSG film, etc. [Example] An example of the present invention will be described below with reference to FIG. FIG. 1 is a diagram showing a method for manufacturing a depression mode InPMIS field effect transistor subjected to heat treatment according to the present invention. First, Figure 1(a). As shown in (b), semi-insulating I
An n°-1nP contact layer 3 is formed on the nP substrate 1 by the VPE method at the portion where the n-InP active layer 2 and source/gate electrodes are to be formed. Next, as shown in FIG. 1(C), the gate insulating film A'o. sG a 11.
Grow TA S layer 4 by 1000 people.

Next, as shown in FIG. 1(d), a SiOt film (PSG film) 5 containing P is formed by CVD as a surface protection film for heat treatment. This was heated at 700℃ in H2 atmosphere for 1
Heat treatment for 5 minutes.

Finally, as shown in FIG. 1(e), the gate electrode 6. FE with source electrode 7 and drain electrode 8
Make T. FIG. 4 shows the gate bias dependence characteristics and static characteristics of the gate-source capacitance of the FET manufactured as described above. Due to the capacitance-voltage characteristics, there is no frequency dispersion in the storage region, and there is no shift on the negative bias side, forming a good interface. . In this way, the frequency dispersion in the storage region disappears, and the voltage that indicates flat capacitance also approaches the ideal one. Furthermore, in terms of FET characteristics, there is no drain current increase, and extension in enhancement mode occurs, resulting in good operation. Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment, and various embodiments are possible within the scope of the present invention.

For example, in the above embodiment, heat treatment is performed separately, but the Ajl! After forming GaAs, MBE
It is also possible to carry out in a chamber.

Furthermore, the heat treatment temperature can also be varied depending on the heat treatment time. Furthermore, although the PSG film was used as the heat treatment protective film in the above embodiments, the present invention is not limited to this. Regarding the atmospheric gas, hydrogen gas is used in the embodiment, but nitrogen gas, argon gas, or the like may also be used. Furthermore, in this example, a shrimp layer formed by the VPE method was used to form the active layer and the contact layer, but an ion-implanted layer may also be used.
The active layer is not limited to InP, but may be an InGaAs layer or the like. Regarding the insulating film Al zG a l-xA S,
In this example, the composition ratio is set to X=0.3, but this can also be changed.

In addition, as in the above example, good AfGaAs/I
In addition to FETs, methods for forming nP interfaces include, for example, Charge Coupled Devices (
It can also be applied to the production of C C D ).

〔Effect of the invention〕

According to the present invention, it has been revealed that by heat treatment after film formation, the interface states are reduced or moved energetically, a good interface is obtained, and frequency division in the accumulation region and hysteresis are reduced. . Furthermore, it was found that there was no voltage shift that was thought to be caused by fixed charges, and that good capacitance-voltage characteristics and FET characteristics were exhibited.

By the manufacturing method of the present invention, a semiconductor device having an InP active layer with a good insulating film can be obtained, and it will greatly contribute to communications, logic circuits, etc. as a high-frequency, high-speed integrated circuit and a high-frequency, high-speed, high-output device. .

Furthermore, application to high-speed transfer devices and the like is also possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a method for manufacturing a depletion mode rnPMIS field effect transistor subjected to heat treatment according to the present invention. FIG. 2 is a diagram showing a method for manufacturing a depletion mode InPMIS field effect transistor by a conventional manufacturing method. Figure 3 is a diagram showing the gate bias dependence characteristics and static characteristics of the gate-source capacitance of a depletion mode InPMIS field effect transistor manufactured by a conventional manufacturing method.
FIG. 3 is a diagram showing the gate bias dependence characteristics and static characteristics of the gate-source capacitance of a PMIS field effect transistor. 1... Semi-insulating InP substrate 2... Active layer 3... Contact layer 4... Gate insulating film 5... Annealing protective film 6... Gate electrode 7... Source electrode 8...・Drain electrode representative patent attorney Yoshiyuki Iwasa 1st ward 3rd ward fig.

Claims (1)

[Claims] (1) A compound semiconductor containing In is used as an active layer, and an Al_xGa_1_-_xAs layer is formed on this active layer (0≦X≦
1), in which the Al
A method for manufacturing a semiconductor device, characterized in that heat treatment is performed after forming a _xGa_1_-_xAs layer.