JPS6050066B2 - MOS semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to an insulated gate field effect transistor (hereinafter MO).
Regarding semiconductor integrated circuit devices (hereinafter referred to as MOSICs) using SFETs (hereinafter referred to as MOSICs), this article mainly deals with Dynamic M05 Memo January C.

For example, in an n-channel MOSIC, an n-channel MOSFET has an n-type source/drain region formed on one main surface of a p-type silicon substrate, and an n-type source/drain region formed on one main surface of a p-type silicon substrate. , 4A
YokP, small, 1,000: l11-F, /lt7 It is composed of a gate electrode formed on the main surface with a thin gate insulating film interposed therebetween. In the above MOSFET, electrons generated in the drain near the gate electrode or in the depletion layer between the drain silicon substrate are injected into the p-type silicon substrate due to a relatively large electric field applied depending on the potential of the gate electrode. .

These injected electrons, ie, minority carriers, diffuse into the silicon substrate and recombine in the drain or source depletion layers of other MOSFETs.

As a result, the operation of one MOSFET causes the other MOSFET to
Leakage current occurs between the drain region of the SFET and the silicon substrate. In a dynamically operated MOSIC in which data is held in a capacitive element in the form of stored charges, one electrode region of the capacitive element is composed of a region of the opposite conductivity type to the silicon substrate or an inverted region on the surface of the silicon substrate.

The other electrode regions are composed of a silicon substrate or a polysilicon layer formed on the one electrode region with an insulating film interposed therebetween. When the minority carriers in the silicon substrate as described above recombine in the depletion layer surrounding one electrode region of the capacitive element, the accumulated charge of this capacitive element leaks.

i Dynamic MOS Memo January C, a memory cell includes a capacitive element and a MOSFET as a switching element, and a plurality of them constitute a memory cell array.

Peripheral circuits such as a sense amplifier, an input/output buffer amplifier, and an address decoder circuit are provided for this memory cell. Normally, the operating level of the peripheral circuit is relatively high compared to the operating level of the memory cell, so the injection of the fractional carriers into the silicon substrate is
Primarily arises from OSFETs.

Minority carriers from this peripheral circuit recombine in the depletion layer below the memory cell. Therefore, data in the capacitive element is destroyed after a relatively long period of time.

One embodiment of the present invention was made by focusing on providing a semiconductor layer inside or on the back surface of a semiconductor substrate that absorbs minority carriers such as electrons in an n-channel MOSFET.

Therefore, one object of the present invention is to provide a MOS memory IC that is provided with a place that effectively absorbs minority carriers generated in the operating state of a MOS device, and another object is to provide a MOS memory IC that is provided with a place that effectively absorbs minority carriers generated in the operating state of a MOS device. A dynamic MOS in which stored information in memory cells is not destroyed by minority carriers.
Note I) In the provision of IC. The present invention will be explained below with reference to Examples.

Example 1 FIG. 1 shows a cross section of a dynamic MOS memory IC according to an example.

In the figure, 1 is an n-type silicon substrate, and 2 is a p-type silicon formed on the n-type silicon substrate! It is a layer.

A single conductivity type MOSFET on the p-type silicon layer 2
In other words, an n-channel MOSFET M1 constituting the peripheral circuit of the memory cell, an n-channel MOSFET M2 constituting the memory cell, and a capacitive element 5 element C1 are formed.

MOSFET Ml is an n-type MOSFET formed in a p-type silicon layer 2.
a gate electrode 10 made of n-type polysilicon formed on the surface of the p-type silicon layer 2 between the drain regions 8 and 9 with a thin silicon oxide film 4 interposed therebetween; It is composed of.

The MOSFET M2 for the memory cell includes an inversion layer that is continuous with an inversion layer 13 for the capacitive element C1 and an n-type region formed in the p-type silicon layer 2, and a p It consists of a gate electrode 15 made of n-type polysilicon formed on a type silicon layer 2 with a thin silicon oxide film 4 interposed therebetween.

Capacitive element C1 has an electrode 16 made of n-type polysilicon formed on p-type silicon layer 2 with a thin silicon oxide film 4 interposed therebetween.

A positive power supply voltage VDD is applied to the electrode 16, so that on the surface of the p-type silicon layer 2 under this electrode,
An inversion layer 13 is formed. This inversion layer 13 is formed by the MOSFET M2 because the electrode 16 extends through the silicon oxide film 5 to the gate electrode 15 of the MOSFET M2.
Continuing to ETM2. The capacitance of the capacitive element C1 is the same as that of the electrode 16.
and the inversion layer 13. The surface of the p-type silicon layer 2 other than the above-mentioned elements is covered with a thick silicon oxide film 3, and the entire surface including the electrodes 10, 15, and 16 is covered with the next thick silicon oxide film 6. There is.

Openings are provided in the silicon oxide film, and electrodes 7, 11, 12 are provided for the p-type silicon layer 2 and the n-type regions 8, 9, respectively.
is provided. In the dynamic MOS memory C described above, a p-type silicon layer 2 on an n-type silicon substrate 1
is formed by an epitaxial growth technique, although it is not particularly limited.

However, it may also be formed by converting the n-type silicon substrate surface to p-type using other techniques, such as ion implantation or diffusion of boron as a p-type impurity. The manufacturing process for the n-channel MOSFETl capacitive element for the p-type silicon layer 2 can be the same as before. In the above, electrode 7 is connected to the circuit ground or negative power supply VBB, and electrode 17 of substrate 1 is connected to positive power supply VDD.

Therefore, the Pn junction between the p-type silicon layer 2 and the n-type silicon substrate 1 is in a reverse bias state.

The above Pn junction is located near the n-type region of MOSFET (7). Minority carriers, that is, electrons, which are injected into the p-type silicon layer 2 from the drain region 9 and its depletion layer in the vicinity of the gate electrode 10 of the MOSFET M1 of the peripheral circuit and diffuse in this layer 2, are transferred to the nearby n-type silicon substrate. Absorbed.

As a result, these electrons do not flow into the memory cell.

The accumulated charges in the inversion layer 13 are retained for a relatively long time. Note that in the memory cell, if the potential of the gate electrode 15 is equal to or higher than its threshold voltage, the MOSFET M2 becomes conductive, and the inversion layer 13 and the n-type region 14 are electrically coupled.

In this state, the charges accumulated in the inversion layer 13 are read out to the n-type region 14, or data is written from the n-type region 14 to the inversion layer 13. If the potential of the gate electrode 15 is below the threshold voltage, the MOSFET M2 becomes non-conductive, and the inversion layer 13 stores and holds data. Example 2
FIG. 2 shows another embodiment of a MOSIC according to the invention.

In the figure, 20 is a p-type silicon substrate, 21 is an n+ type buried layer formed by selective diffusion using a diffusion mask or ion implantation using a photoresist mask on the substrate, 2
2 is a p-type silicon layer epitaxially grown on the substrate via the buried layer. 23 is a p-type silicon layer 22
This is a (+) power supply extraction cup-shaped layer which is selectively diffused so as to be in contact with the type-resistant buried layer 21 from the surface thereof.

In this case, the (+)
While applying a power source, for example, (VDD), the p-type silicon layer 8 is connected to BB or grounded. In this example,
A MOSFET and a capacitive element similar to those shown in FIG. 1 are formed on the p-type silicon layer 22 on the n+-type buried layer 21. According to the configuration described in the second embodiment, it is possible to prevent electrons from flowing into the memory cell for exactly the same reason as described in the first embodiment.

In the case of the dynamic MOS memory C, as shown in FIG. A peripheral circuit element of a memory cell may be formed in a portion 24 corresponding to the buried layer 21, and a MOS memory cell may be formed in a p-type silicon layer 25 corresponding to a portion where the rectangular buried layer is not formed. .

In this case, since the memory cell is formed on the p-type silicon layer 25 formed on the p-type silicon substrate with good crystallinity,
Better characteristics can be obtained. The present invention is not limited to the embodiments described above, and may take other forms.

For example, in the case of a p-channel MOSIC, holes are targeted as minority carriers generated from the drain, and the present invention is similarly applied to a structure that prevents write information in a memory cell from being destroyed by these holes. This invention is M
OS memory IC in general, especially dynamic operation MOSIC
It is effective when applied to

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a main part of a MOSIC showing one embodiment according to the present invention, FIG. 2 is a cross-sectional view of a main part of a MOSIC in one manufacturing process of another embodiment according to the present invention, and FIG. FIG. 3 is a perspective view showing the form after forming a Gi-shaped buried layer in the example. 1... N-type silicon substrate, 2... P-type epitaxial silicon layer, 3, 4, 5, 6...
Silicon oxide film, 8, 9, 14... n+ type source drain, 10, 15... gate electrode,
7, 11, 12, 16... electrode.

Claims (1)

[Scope of Claims] 1 A second conductive type semiconductor layer, a first conductive type semiconductor layer on the second conductive type semiconductor layer, a capacitive element on the surface of the first conductive type semiconductor layer, and at least a capacitive element stored in the capacitive element. a memory cell having a control electrode used for reading out information, the MOS semiconductor is characterized in that the pn junction between the second conductivity type semiconductor layer and the first conductivity type semiconductor layer is in a reverse bias state. Integrated circuit device. 2. The MOS semiconductor integrated circuit device according to claim 1, wherein the MOS semiconductor element constitutes a peripheral circuit of a dynamic MOS memory cell. 3. The MOS semiconductor integrated circuit device according to claim 2, wherein the second conductivity type buried layer is formed under the peripheral circuit.