JPS6242446A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent random inversion of memorized data and thereby to attain high reliability by a method wherein a P-type well region of a specified thickness is provided in a surface region of a substrate, a plurality of memory cells and their peripheral circuits are built therein, and a voltage not higher than a ground potential VSS is applied to the well region, and a voltage not lower than the ground potential VSS is applied to the substrate. CONSTITUTION:On an N-type Si substrate 30, N-type layers 2, 3, 4, 5, transfer gates 6, 8, and electric charge storage gates 10, 11 constitute a dynamic memory cell. Under this method, a P-type well 20 is so this as to be 4-5mum that the number of electron- and-hole pairs generated in a well under alpha-particle radiation is far smaller than under a conventional method. The number of electrons collected in a storage capacitor is so small as to be not more than one tenth of the number under the conventional method. Generally, the P-type well 20 is fixed at a ground potential VSS or at a voltage VBB that is not higher than the ground potential VSS. The N-type Si substrate 30 is fixed at the ground potential VSS or at a power source voltage VDD that is not lower than the ground potential VSS. With the number of electrons being smaller than that of the stored electric charges, inversion does not take place of the data stored in the memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Prior Art] Conventionally, memory ICs such as dynamic random access memories have had the configuration shown in FIG. In the figure, 1 is a p-type Si substrate, 2, 3
, 4.5 n-type layer and 6°8 transfer gate, 10.1
Due to the charge storage capacitor composed of the charge storage gate 1, 1 bit at 2,3°6.10, 4,5,8.11
This constitutes a so-called one-transistor type dynamic memory cell for one bit. 7 and 9 are data lines,
12.13 are used as word lines.

[Problem to be Solved by the Invention 1] When a memory IC and an LSI are configured with this configuration and sealed in a package, the most problematic point is that α-ray particles generated from impurities in the package material LSI
It illuminates the surface of the chip and inverts the information stored in the memory cells, creating random errors (T-C).

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'78. ΔpprH). Depending on the energy, these α-ray particles reach a depth of about 20 to 100 μm from the Si surface, and form pairs of electrons and holes almost uniformly in the depth direction with a certain spread. Holes are attracted to the substrate, but electrons are attracted by the storage capacitance of a memory cell, for example, a pavi' (state with no electrons), and the memory cell becomes ``0'' (a state with an I-electron). It reverses the state. The above-mentioned inversion of the information in the memory cell is related to the amount of charge stored in the product capacitor of the memory cell and the amount of electrons created by irradiation with α-ray particles collected in the storage capacitor. If the amount of electrons is less than the stored charge, no inversion of the information stored in the memory cell will occur.

The object of the present invention is to overcome the drawbacks of the above-mentioned conventional examples.

An object of the present invention is to provide a semiconductor device with high reliability.

〔Example〕

FIG. 2 shows a first embodiment of the invention. In the figure, 30 is an n-type Si substrate, and 20 is a p-type well. According to the invention.

The thickness of the P-type well 20 is as thin as 4 to 5 μm at most, and α
Even when ray particles are irradiated, the number of electron-hole pairs created within the well is much smaller than in the conventional example.

According to calculations using a simple model, in the case of the structure according to the present invention, the number of electrons collected in the storage capacitor is 1
It showed a significant decrease to less than /lO. Therefore, random inversion of memory information, which has been a problem in the past, does not occur in this structure, and a highly reliable semiconductor device can be provided.

In the embodiment, the present invention was explained in detail by surrounding only the memory cell section with a p-type well, but the p-type well may be used on the entire surface of the chip including the peripheral circuit section, and the peripheral circuit section and the Even if the memory cell portion is surrounded by separate P-type wells, the effects of the present invention can be exerted.

Normally, 20 is the ground potential v8B or lower voltage ■[
3B, and 30 is fixed at a voltage of 7g8 or higher, which is at the power supply voltage VDD level. On the other hand, in order to retain the information stored in the memory cell for a longer time, 30 is set to the storage voltage of the memory cell, e.g. Voo-Vt.
)l (Vth: threshold voltage of MOS transistor)
If the voltage is fixed at the same voltage as , the leakage current between 20 and 4 will be reduced, which is very effective.

Also, if 20 is fixed at about VBB + 0.5V, 20
This has the great effect of reducing leakage current by completely accumulating the Si surface on which is formed.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a conventional memory IC, and FIG. 2 is a sectional view showing a memory IC according to an embodiment of the present invention. 2.3, 4.5...n+ type diffusion layer, 20...p type wave@layer well, 30...n@Si substrate. 7th

Claims (1)

[Claims] 1. In a semiconductor memory device in which a plurality of memory cells and peripheral circuits are provided in a surface region of a semiconductor substrate, a p-type well region with a thickness of 5 μm or less is provided in the surface region of the substrate. The plurality of memory cells and the peripheral circuit are provided in the p-type well region, a ground potential V_S_S or a voltage lower than that is applied to the well region, and a voltage of V_S_S or higher is applied to the substrate. A semiconductor memory device with a voltage applied to it. 2. The semiconductor memory device according to item 1, wherein a voltage at the level of power supply voltage V_D_D is applied to the substrate. 3. In the semiconductor memory device according to item 2, the substrate has a memory cell storage voltage V_D_D-Vth (Vth
: A semiconductor memory device to which the same voltage as the threshold voltage of the MOS transistor of the memory cell is applied. 4. In a semiconductor memory device in which a plurality of memory cells and peripheral circuits are provided in a surface region of a semiconductor substrate, a p-type well region with a thickness of 5 μm or less is provided in the surface region of the substrate, and the p-type well region is provided in the surface region of the substrate. The plurality of memory cells are provided within the region, the peripheral circuit is provided outside the p-type well region, a ground potential V_S_S or a voltage lower than that is applied to the well region, and a voltage of V_S_S_ is applied to the substrate.
A semiconductor memory device to which a voltage of S or higher is applied. 5. The semiconductor memory device according to item 4, wherein a voltage at a power supply voltage V_D_D level is applied to the substrate. 6. In the semiconductor memory device according to item 5, the substrate has a memory cell storage voltage V_D_D-Vth (Vth
: A semiconductor memory device to which the same voltage as the threshold voltage of the MOS transistor of the memory cell is applied.