JPH0245341B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit using field effect transistors.

As patterning technology improves and transistor sizes decrease, the area of memory cells continues to decrease every year. In particular, in a static type memory circuit device using a flip-flop circuit as a memory cell, the memory cell area occupies a larger proportion of the entire chip than in a dynamic type memory circuit device, and the contribution of pattern miniaturization is greater in the former. However, the reduction in memory cell area naturally brings about a decrease in the capacitance value parasitic to the node on the drain side of the flip-flop transistor, and therefore the amount of stored charge decreases.

On the other hand, in order to reduce the power consumption of static memory circuit devices during standby, polysilicon resistors of several MΩ to several GΩ are now being used as loads for memory retention in memory cells. As described above, when the amount of charge stored in a static memory cell becomes small and the resistance of the load for replenishing the charge becomes large, soft errors become a problem.

What is a soft error? According to TCMay in 1978
International Reliability Physics Symposium
Destruction of stored data due to alpha rays, which was announced in 2013. In other words, when alpha rays, which are generated when naturally radioactive elements such as uranium and thorium that exist in ppm units in the package material decay, pass through the memory array area, electron-hole pairs are formed in the Si substrate, and these electrons Inversion of memory cell information occurs to lower the stored positive potential.

Immediately after writing to a static memory cell, any node is at a potential that is one step lower than the address potential, and if alpha rays hit it before the potential is raised to a higher potential by a load, if this accumulated charge is small, There is a possibility that the gate threshold voltage of the flip-flop transistor becomes smaller than that of the flip-flop transistor, causing the flip-flop circuit to be inverted. That is, if the load resistance is large, a static type memory can be considered in the same way as a dynamic type memory for a certain period of time.

Ionization in Si occurs both in the depletion layer formed under the diffusion layer and in the bulk, but in 1979 IEEE
Translation on Electron Devices Vol ED−
As stated in 26P10, the amount of charge generated by α rays increases in proportion to the width of the depletion amount, and the generated charge is absorbed into the diffusion layer within a short time. Therefore, one way to prevent soft errors caused by α rays is to reduce the width of this depletion layer.

The width of the depletion layer becomes smaller as the concentration of the Si substrate increases. However, if peripheral circuits other than memory cells are also formed in a highly doped substrate, junction capacitance and dependence on substrate bias will increase, preventing high-speed operation of the peripheral circuits.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a memory circuit device having memory cells that are resistant to alpha rays without preventing high-speed operation of peripheral circuits.

A feature of the present invention is that only the memory cell portion is formed in a well containing an impurity of the same conductivity type as the substrate and at a higher concentration than the substrate.

Next, in order to better understand the present invention, examples will be described using drawings.

FIG. 1 is a sectional view of a memory circuit device showing an embodiment of the present invention. Area A is the memory cell portion, and area B is the peripheral area other than the memory cells. Here, the memory cell section includes two transferred transistors,
2 flip-flop transistors, 2 load elements
This refers to a memory cell array section in which one memory cell consisting of column lines and row lines is arranged in a matrix. In order to enable high-speed operation, the board 101 has two
P-type Si with a low impurity concentration containing ×10 ₁₄ /cm ³ of boron was used. Region A is formed in the P well 102 containing boron of 1×10 ₁₅ to 1×10 ₁₆ /cm ³ .
This P-well has a Si oxide film 10 as shown in Figure 2a.
After ion implantation of 5×10 ₁₁ to 5×10 ₁₂ cm ² of boron into the Si substrate 101 through a Si substrate 101, heat treatment was performed at 1200° C. to form the silicon substrate. By this method, a P-well region 10 having a substantially uniform concentration over a thickness of 5 μm is obtained.
2 can be formed. The embodiment shown in FIG. 1 is obtained by using the substrate shown in FIG. 2b as a starting substrate and forming elements such as the transistor 103 through a subsequent patterning process.

In the case where the memory cell is formed on the same low concentration as the periphery and in the case where it is formed in a P-well of 1×10 ₁₆ /cm ³ , the depletion layer is There is a seven times difference in width.

As described above, by using the present invention, a memory cell that is resistant to alpha rays can be formed without sacrificing high-speed operation of peripheral circuits.

In this embodiment, the P well is formed before all the steps, but after forming the gate insulating film, boron ions can be implanted and further pushed in as described above.

Further, in this embodiment, a static memory has been described, but the present invention is also applicable to a dynamic memory composed of one transistor and one capacitor.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention. Figures 2a and 2b illustrate one method for forming a P-well. 101 is a P-type Si substrate, 102 is a P-well formed with a P-type impurity at a higher concentration than the substrate, and 103 is a transistor. In the figure, an area A is a memory storage means for storing information, a row line for selecting the information, a transistor formed below the row line, and a column line connected to the transistor. A memory cell portion in which cells are arranged in a matrix, and region B is a peripheral circuit portion other than the memory cell portion.

Claims (1)

[Claims] 1. In a semiconductor memory circuit device including a memory cell section in which a large number of memory cells each of which constitutes a storage means using field effect transistors are arranged, and a control circuit for the memory cells, only the memory cell section is of the same conductivity type as the substrate and of the same conductivity type as the substrate. 1. A semiconductor memory circuit device, characterized in that the control circuit is formed in a well having an impurity concentration higher than that of a substrate, and the control circuit is formed outside the well in a portion of the substrate having a lower impurity concentration than the well.