KR900002887B1 - Semiconductor memory device - Google Patents

Abstract

The semiconductor memory device with alpha ray prevention structure includes: a first conductive type semiconductor substrate; the first semiconductor region of a second conductive type for charge storage region; the second semiconductor region of a second type for source- drain regions; the third semiconductor region for bit line. The semiconductor substrate has the impurity concentration of 1x1015 - 1x1016 cm-3 and the first, second, third semiconductor region has the inpurity concentration of 1x1014 1x1018 cm-3.

Description

Semiconductor memory

1 is a cross-sectional view showing the structure of a memory cell portion of a semiconductor memory device according to an embodiment of the present invention.

2A to 2C are explanatory views for explaining a method of manufacturing a peripheral portion of a memory cell of a semiconductor memory device according to an embodiment of the present invention.

3 shows the relationship between the P-type impurity concentration in the P ⁺ -type region and the soft error occurrence rate.

4 is a cross-sectional view showing the structure of a memory cell section of a conventional 256K dynamic RAM.

5 is a cross-sectional view showing the structure of a memory cell portion of another conventional 256K dynamic RAM.

* Explanation of symbols for main parts of the drawings

1: P ^- type semiconductor substrate 2: First gate electrode

3: second gate electrode 4: first gate insulating film

5: second gate insulating film 6, 80, 81: N ⁺ type region

7, 10, 130, 131: P + type region 9: Separation insulating film

11, 12: depletion layer 14: resist film pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of eliminating soft errors caused by radiation such as? Rays.

This type of semiconductor memory device is conventionally shown in FIG. 4 is a cross-sectional view showing the structure of a memory cell periphery of a conventional 256K dynamic RAM. First, the structure of the peripheral portion of this memory cell will be described. In the drawing, a P ⁺ type region 10 is formed on the P ⁻ type semiconductor substrate 1 to prevent reverse parasitics, and a separation insulating film 9 is formed on the P ⁺ type region to separate the elements. It is. An N ⁺ type region 6 is formed on the P ⁻ type semiconductor substrate 1 to form a charge accumulation region for storing information, and a first gate insulating film 4 is formed on the n ⁺ type region. . The first gate electrode 2 connected to the power source is formed on the first gate insulating film 4 and the isolation insulating film 9 again.

The N ⁺ type region 6, the first gate insulating film 4, and the first gate electrode 2 form a memory cell. In addition, P ^-, and N ⁺ type region 6 and the continuous N ⁺ type region 80 is a source / drain region of one side is formed such that there is a N ⁺ type region 80 is again on the semiconductor substrate (1) N ⁺ type regions 81 are formed at intervals to serve as source / drain regions on the other side. This N ⁺ type region 81 is connected to a bit line (not shown). In addition, between the N ⁺ type regions 80 and 81. P ^- semiconductor substrate (1) a second gate insulating film 5 on the N ⁺ type region 80 a and the N ⁺ type region 81 is formed And a second gate electrode 3 serving as a word line on the second gate insulating film.

The P ⁻ semiconductor substrate 1, the N ⁺ type region 80, the N ⁺ type region 81, the second gate insulating film 5, and the second gate electrode 3 form a transfer gate transistor. 11 is a depletion layer formed between the N ⁺ type region 6 and the P ⁻ type semiconductor substrate 1, and 12 is a hole formed between the N ⁺ type region 80 and 81 and the P ⁻ type semiconductor substrate 1. The pip layer is displayed.

In addition, for convenience of description, an interlayer insulating film formed on the second gate electrode 3 on the N ⁺ type region 80 and on the N ⁻ type region 81, a wiring portion such as a bit line formed on the interlayer insulating film, these The protective film formed on the interlayer insulating film and the wiring portion is omitted. In addition, an N ⁺ type region 6, which is an impurity diffusion region, is formed, and instead, the potential is applied to the first gate electrode 2, and the N on the P ⁻ type semiconductor substrate 1 is interposed through the first gate insulating film 4. ^An N ⁺ type inversion layer may be maintained in an equivalent portion of the ⁺ type region 6 to accumulate charge in the inversion layer.

Next, the operation of this memory cell peripheral portion will be described. The state in which electrons are accumulated in the N ⁺ type region 6 which is the charge accumulation region of the memory cell is set to "0", and the state in which electrons are not accumulated is set to "1". The potential of the N ⁺ type region 81 connected to the bit line has been previously maintained at a certain intermediate potential by the action of a sense amplifier (not shown).

Here, when the potential of the word line rises and the potential of the second gate electrode 2 of the transfer gate transistor connected to the weed line becomes higher than the threshold voltage, the channel of the N ⁺ type inversion layer is directly under the second gate electrode. be formed in N ⁺ type region 6 is 80 and the N ⁺ type region 81 is simple conduction.

Thus, the N ⁺ type region, which now is the information stored in the memory cell "0", that is, the state in which electrons are accumulated is connected to the bit line and the N ⁺ type region 6, 80 is a N ⁺ type region 6 The electric potential of the N ⁺ type region 81 held at the intermediate potential until the conduction of (81) falls, or vice versa, the storage information of the memory cell is "1", that is, electrons are accumulated in the N ⁺ type region 6 In the absence of the state, the conduction raises the potential of the N ⁺ type region 81 at the intermediate potential.

The change in the potential of the bit line is sensed, amplified and taken out by the sense amplifier, and the same memory information is refreshed and written again into the memory cell in the same cycle.

The conventional memory cell unit operates as described above, but since the source / drain region and the charge accumulation region are formed of an N ⁺ type region or an N ^{+ type} inversion layer, electrons in the electron hole band generated by radiation such as? Is collected in the N ⁺ type regions 6 and 80 and the N ⁺ type region 81, thereby causing a malfunction (hereinafter referred to as software error) by inverting the original memory information.

In order to solve this drawback, as shown in FIG. 5, a P ⁺ type region 7 is formed in contact with the N ⁺ type region 6, which is a charge accumulation region, to increase the memory cell capacity to emit radiation such as? generating electrons are N ⁺ type region 6 is collected even if not malfunction threshold charge amount significantly to, but this means for preventing soft error N ⁺ type region N ⁺ type regions which are connected to 80, and the bit line to (81 is ) Is not protected against the collection of electrons, and additionally, when a P ⁺ type region is provided around the N ⁺ type regions 80 and 81, the narrow second gate electrode 3 of only 1 to 3 mu m is provided. There is a problem that it becomes difficult to operate the transfer gate transistor stably because a P ⁺ type region is formed under the bottom.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to obtain a semiconductor memory device capable of eliminating soft errors caused by radiation such as α rays as a simple structure without losing transistor characteristics even in a miniaturized structure. do.

The semiconductor memory device according to the present invention has a first impurity concentration higher than an impurity concentration of the substrate so as to be in contact with a second conductive type first semiconductor region which becomes a charge storage region for storing information on the first conductive semiconductor substrate. The first semiconductor layer is formed so as to be in contact with the second conductive second semiconductor region which forms a conductive first semiconductor region and is continuous with the second doped first semiconductor region on the first conductive semiconductor substrate and becomes a source / drain region on one side. The first conductive third semiconductor region having a higher impurity concentration than the impurity concentration of the substrate is formed so as to be continuous with the conductive first semiconductor region and not to enter the channel region under the second gate insulating film.

In the present invention, a first impurity concentration is higher than an impurity concentration of the first conductive semiconductor substrate so as to contact each of the second conductive first semiconductor region, the second conductive second semiconductor region, and the second conductive third semiconductor region. Conducting type 1 semiconductor region First conducting type 2 semiconductor region and 1st conducting type 3 semiconductor region are formed, so the second conducting type 2 semiconductor between the 1st conducting semiconductor region and 1st conducting type 1 semiconductor region The width of the depletion layer formed between each of the region and the first conductive second semiconductor region and between the second conductive third semiconductor region and the first conductive third semiconductor region is narrowed so that the second conductive first semiconductor region second The capacitance of the conductive second semiconductor region and the second conductive third semiconductor region is increased.

For this reason, the difference in the number of electrons corresponding to "0" and "1" accumulated in the second conductive type 1 semiconductor region, the second conductive type 2 semiconductor region, and the second conductive type 3 semiconductor region becomes large. The conductive first semiconductor region, the second conductive second semiconductor region, and the second conductive third semiconductor region may have a margin for electrons generated by the incidence of α-rays. In addition, the electrons diffused from the semiconductor substrate have a short lifespan in the first conductive type 1 semiconductor region, the first conductive type 2 semiconductor region, and the first conductive type 3 semiconductor region, and thus the second conductive type 1 semiconductor region and second conductive layer. It becomes difficult to reach the type second semiconductor region and the second conductive type third semiconductor region. In addition, since a potential barrier against electrons is formed at the interface between the semiconductor substrate and the first conductive type 1 semiconductor region, the first conductive type 2 semiconductor region, and the first conductive type 3 semiconductor region, Small energy cannot be passed by this barrier. In addition, since the first conductive second semiconductor region and the first conductive third semiconductor region are formed so as not to enter the channel region under the second gate insulating film, the threshold voltage of the transfer gate transistor does not become excessively high.

The following describes an embodiment of the present invention according to the drawings. In addition, in the description of this embodiment, the description of parts that overlap with the description of the prior art is omitted.

1 is a cross-sectional view showing the structure of a memory cell peripheral portion of a semiconductor memory device according to an embodiment of the present invention. The configuration of this embodiment differs from the configuration of the peripheral portion of the memory cell in FIG. 4 as follows. In other words, for example, the impurity concentration is in contact with the N ⁺ type region 6, which becomes a charge storage region for storing information on the P ⁻ type semiconductor substrate 1 having a concentration of 10 ¹³ to 10 ¹⁶ cm ⁻³ . A P ⁺ type region 7 having a concentration of 10 ¹⁴ to 18 cm ⁻³ is formed. In addition, the lower portion of the second gate insulating film 5 is disposed on the P ⁻ type semiconductor substrate 1 so as to be in contact with the N ⁺ type region 80 serving as a source / drain region on one side and to be continuous with the P ⁺ type region 7. For example, a P ⁺ type region 130 having an impurity concentration of 10 ¹⁴ to 10 ¹⁸ cm ⁻³ is formed so as not to enter the channel region.

Furthermore, the other source / drain regions on the P ⁻ type semiconductor substrate 1 are in contact with the N ⁺ type regions 81 connected to the bit lines or do not enter the channel regions under the second gate insulating film 5. For example, a P ⁺ type region 131 having an impurity concentration of 10 ¹⁴ to 10 ¹⁸ cm ⁻³ is formed.

Next, the manufacturing method of the memory cell peripheral portion will be described with reference to FIGS. 2A to 2C. First of P ^- type in the semiconductor substrate 2 by selectively ion-implanting P-type impurity to form an ion-implanted layer to form an ion implantation diffusion layer and the P ⁺ type region for a reverse parasitic anti-10 and after the P ⁺ An isolation insulating film 9 is formed on the mold region 10 to separate the devices. Continuously selectively implanting the N-type impurity in the P- type semiconductor substrate 1 is ion-implanted layer for forming and after forming a N ⁺ type region 6 to diffuse the ion-implanted layer is N ⁺ type region (6 ), P ^- type impurities are selectively implanted into the P ⁻ type semiconductor substrate 1 to form an ion implantation layer, and the ion implantation layer is diffused to form a P ⁺ type region 7. Subsequently, the first gate electrode 2, the second gate electrode 3, the first gate insulating film 4, and the second gate insulating film 5 are formed by a conventional manufacturing method. Subsequently, N ⁺ impurities are implanted into the P ⁻ type semiconductor substrate 1 using the first gate electrode 2 and the second gate electrode 3 as a mask to form N ⁺ type regions 80 and 81. (Figure 2a).

Next, the second gate electrode 3 is covered with a resist film pattern 14, and the N ⁺ type region 80 and the P ⁻ type are formed using the first gate electrode 2 and the resist film pattern 14 as masks. P-type impurities are implanted into the semiconductor substrate 1 and the P ⁻ -type semiconductor substrate 1 (FIG. 2B). Next, the formed ion implantation layer is diffused to form P ⁺ type regions 130 and 131 (FIG. 2C).

Here, the threshold voltage of the transfer gate transistor is set higher than the threshold voltage of the peripheral transistor in consideration of the stable operation of the device. However, the P ⁺ type regions 130 and 131 have a channel region below the second gate insulating film 5. If formed in the semiconductor substrate, the threshold voltage of the transfer gate transistor becomes too high, so that the P ⁺ type regions 130 and 131 formed by diffusion and ion implantation of P-type impurities using the resist film pattern 14 as a mask are second. The control is performed so as not to enter the channel region under the gate insulating film 5.

Next, the operation of this memory cell peripheral portion will be described. The soft error described above is caused by the collection of electrons in the N ⁺ type region 6 or the N ⁺ type region 80, 81 in the electron hole band generated when radiation such as α-rays enters the chip. That is, the α-rays incident on the chip generate a large number of electron hole bands depending on the specific state until energy stops and stops, and the electron hole bands generated in the depletion layers 11 and 12 are depleted layer 11 ( 12) Immediately separated by the internal electric field, electrons are collected in the N ⁺ type regions 6, 80 and 81 and holes flow through the P ⁻ type semiconductor substrate 1. In addition, since the electron holes generated inside the N ⁺ type regions 6, 80, 81 are recombined, they do not contribute to the increase or decrease of electrons, and the electron holes generated inside the P ⁻ type semiconductor substrate 1 diffuse. Only electrons that reach the depletion layer (11) (12) by the electrons are collected in the N ⁺ -type regions (6) (80) (81), causing a soft error, and others are recombined in the P ^- type semiconductor substrate (1). Will be.

Therefore, in this embodiment, the P ⁺ type regions 7 and 130 have a higher impurity concentration than the impurity concentration of the P ⁻ type semiconductor substrate 1 so as to be in contact with each of the N ⁺ type regions 6, 80 and 81. The width of the depletion layers 11 and 12 formed between the N ⁺ type regions 6, 80, 81 and the P ⁺ type regions 7, 130, and 131 is formed by forming 131. It becomes narrower and the capacity | capacitance of N <^+>- type area | regions 6, 80, 81 becomes large. In addition, electrons diffused from the P-type semiconductor substrate 1 are shortened in the P ⁺ type regions 7, 130, and 131 so that the N ⁺ type regions 6, 80, and 81 are shortened. It becomes difficult to reach. In addition, since a potential barrier for electrons is formed at the interface between the P ⁻ type semiconductor substrate 1 and the P ⁺ type regions 7, 130, and 131, the third type diffuses in the P ⁻ type semiconductor substrate 1. The smallest energy in the electrons cannot pass through this barrier. And first by the point N ⁺ type region 6, 80, 81 is "0", the difference between the number of electrons corresponding to the "1" larger and the N ⁺ type region 6 is stored in 80 of the ( 81 can have a margin with respect to electrons generated by incidence of α rays and the like, and can prevent electrons diffused into the N ⁺ -type regions 6, 80, 81 by the second and third points. In this way, the occurrence of the software error can be eliminated.

The relationship between the P-type impurity concentration in the third road P ⁺ type regions 7 (130) 131 and the soft error occurrence rate is shown. As shown in the figure, increasing the P-type impurity concentration significantly reduces the soft error occurrence rate. For example, when the impurity concentration is about 10 ¹⁷ cm ^{-3, the} lubrication occurrence of the soft error decreases to about 10 ^-4 as compared with the case where the impurity concentration is 10 ¹³ cm ^-3 .

However, as described above, when the P ⁺ type regions 130 and 131 enter the channel region under the second gate insulating film 5, the threshold voltage of the transfer gate transistor is significantly increased, and the amount of write charge Q _S = C _S (V _D- V _T ) becomes less and memory operation becomes unstable. Where V _D is the gate voltage of the transfer gate transistor, V _T is the threshold voltage of the transfer gate transistor, and C _S is the memory cell capacity. Therefore, the P ⁺ type regions 130 and 131 can be stably formed outside the channel region under the second gate insulating film 5 by ion implanting the P type impurities using the resist film pattern 14 as a mask. An appropriate threshold voltage V _T can be obtained. In this way, the P ⁺ type regions 130 and 131 can be formed without suppressing the soft error occurrence rate and affecting the threshold voltage of the transfer gate transistor.

In addition, as indicated in the above embodiment, since the N ⁺ type region 81 connected to the bit line is in contact with the P ⁺ type region 131, the depletion layer capacity of the junction increases and the stray capacitance C _B of the bit line becomes large. Since the signal voltage V detected by the sense amplifier becomes V = (V _D -V _T ) / (1 + C _B / C _S )}, when the stray capacitance C _B becomes large, the signal voltage becomes small and the operation as the storage device is unstable. Done. For this reason, it is necessary to suppress that the floating capacitance C _B becomes large, and in order to reduce the floating capacitance C _B , an insulating film between the lower layers of the bit lines or an upper protective film of the bit lines is formed of a silicon oxide film or phosphorus glass film having a low dielectric constant. It is especially good in this invention.

Furthermore, in the above embodiment, the P + type regions 7, 130 and 131 are formed to be in contact with the N ⁺ type regions 6, 80 and 81, but the N ⁺ type region and the peripheral circuit of the sense amplifier are illustrated. By forming the P ⁺ type region so as to be in contact with the N ⁺ type region, the soft error occurring in these portions can be reduced.

In addition, the above embodiment is applied to the dynamic RAM, but the present invention is equally applicable to the static RAM, and the present invention can be applied to the bipolar device instead of the MOS device when the N channel is the P channel.

As described above, according to the present invention, the first conductive layer having a higher impurity concentration than the impurity concentration of the substrate is in contact with the second conductive first semiconductor region, which is a charge accumulation region for storing information on the first conductive semiconductor substrate. Forming a first semiconductor region and contacting the second conductive semiconductor region which becomes a source / drain region on one side of the second conductive semiconductor substrate on the first conductive semiconductor substrate. In the conductive type, the first conductive region is formed to be continuous with the first semiconductor region and does not enter the channel region under the second gate insulating film, and the first conductive type second semiconductor region has a higher impurity concentration than the impurity concentration of the substrate. Being a source / drain region on the other side of the semiconductor substrate and coming into contact with the second conductive third semiconductor region connected to the bit line, and not entering the channel region under the second gate insulating film. Since the first conductive third semiconductor region is formed to have a higher impurity concentration than the impurity concentration of the substrate, a semiconductor having a simple structure can remove soft errors caused by radiation such as α rays without damaging transistor characteristics. Memory can be obtained.

In addition, since the soft error can be eliminated in this way, there is an effect that a semiconductor memory device can be produced without the usual resin coating for preventing α rays.

Claims (4)

The second conductive type first semiconductor region formed on the first conductive semiconductor substrate and the electric semiconductor substrate to be a charge accumulation region for storing information, and the second conductive type first semiconductor region on the electric semiconductor substrate. A second conductive semiconductor layer formed on one side and formed as a source / drain region on one side and a second semiconductor region formed on the electrical semiconductor substrate at intervals from the second conductive first semiconductor region to form a source / drain region on the other side. A first gate insulating film formed on the second conductive type third semiconductor region and an electrical second conductive type first semiconductor region connected to the first gate electrode and the second gate conductive film formed on the first gate insulating film; The second gate gate insulating film formed on the electric semiconductor substrate between the second semiconductor region and the third conductive semiconductor region, on the second conductive semiconductor region, and on the second conductive semiconductor region. My The first conductive type first semiconductor region is formed on the second gate electrode formed on the two-gate insulating film and in contact with the second conductive type first semiconductor region on the electric semiconductor substrate and has a higher impurity concentration than the impurity concentration of the electric semiconductor substrate. And the second conductive semiconductor layer on the electrical semiconductor substrate, the second conductive semiconductor layer is in contact with the first conductive semiconductor layer, and is not burnt in the channel region under the second gate insulating film. It is formed so as to be in contact with the first conductive second semiconductor region higher than the impurity concentration of the semiconductor substrate and the second conductive third semiconductor region on the electric semiconductor substrate and not to enter the channel region under the second gate insulating film. A semiconductor memory device comprising: a first conductive third semiconductor region having an impurity concentration higher than that of the semiconductor substrate. The impurity concentration of the electrical semiconductor substrate of claim 1 is 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^-3, and the first conductive type first semiconductor region, the first conductive type second semiconductor region, and the first conductive type are respectively. The semiconductor memory device of which the impurity concentration of the third semiconductor region is 1 × 10 ¹⁴ to 1 × 10 ¹⁸ cm ^-3 . The semiconductor memory device according to claim 1 or 2, further comprising a low dielectric constant interlayer insulating film made of a silicon oxide film or a phosphorus film between the second conductive third semiconductor region and the electric bit line. 4. The semiconductor memory device according to claim 3, comprising a protective film of low dielectric constant formed on an electric bit line and also made of a silicon oxide film or a phosphorus film.

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