JP2829034B2 - Semiconductor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a semiconductor circuit having an nMOS type transistor, for example, a dynamic RAM (DRAM) having a one-transistor / one-capacitor memory cell structure. In the word line driving circuit.

(Prior art) One transistor / 1 capacitor memory cell structure
In a DRAM, when the power supply potential Vcc is written to the cell capacitor, the gate of the switching MOS transistor has Vcc
It is necessary to apply a boosted potential equal to or higher than + Vth (Vth is the threshold voltage of the MOS transistor). This is because, when the gate potential of the MOS transistor is set to Vcc, when the source rises to Vcc-Vth, the MOS transistor is turned off, so that only the Vcc-Vth is written to the cell capacitor connected to the source.

In a DRAM, the gate electrode of this switching MOS transistor is shared by many memory cells to form a word line. For example, in a 4 Mbit DRAM, 2000 MOS transistors are connected to one word line. For this reason, the word line has a large capacity, and accounts for a large ratio of the time required to boost this word line to about 10% of the DRAM access time. Therefore, the design of a booster circuit that drives a word line is important in realizing a high-speed operation of a DRAM.

The configuration and operation of the conventional DRAM word line drive circuit are described in ninth
This will be described with reference to FIG. 10 and FIG. FIG. 9 shows only the minimum necessary circuit elements of the word line drive circuit. C is a boost capacitor, Q1 is a boost capacitor C
Is a transfer gate transistor for transferring the boosted potential to the output terminal OUT connected to the word line, and Q3 is a discharge MOS transistor for the output terminal OUT. Here, all the MOS transistors Q1 to Q3 use an n-channel.

FIG. 10 shows operation waveforms of this drive circuit. When the word line is not selected, the clocks φ1, φ2, φ3 are all at “L” level. Therefore, the MOS transistors Q2 and Q3 are off, and the node N of the capacitor C is charged to Vcc-Vth (Vth is the threshold voltage of the MOS transistor Q1) by the MOS transistor Q1. In some cases, the gate of the MOS transistor Q1 is controlled by the boosted potential independently of the drain to charge the node N2 to Vcc, but this is not considered now. Next, clocks φ1 and φ2 are “L”
The level changes from the level to the “H” level. As a result, the potential of the node N is boosted to Vcc or more by the function of the capacitor C, and the output terminal OU is output via the transfer gate MOS transistor Q2 which is turned on.
Supplied to T. At this time, the "H" level of the clock φ1 has been raised to Vcc or higher so that the boosted potential of the node N is supplied to the word line WL without being affected by the threshold voltage of the MOS transistor Q2. Shall be. In this way, the potential boosted to Vcc or higher is applied to the word line. By returning the clocks φ1 and φ2 to the “L” level and setting the clock φ3 to the “H” level, the transfer gate MOS transistor Q2 is turned off, the discharge MOS transistor Q3 is turned on, and the word line WL is discharged to “ L "level.

 There are two problems with this prior art.

First, since the capacity of the word line WL is large, the capacity of the boosting capacitor C must be sufficiently large to obtain a sufficient boosted potential. The required boosted potential is Vcc + α. The boosting capacitor C is charged in advance with a charge of C (Vcc-Vth) as described above,
The charge is pushed up by the clock φ2 = Vcc and distributed to the capacitance of the word line WL connected to the output terminal OUT via the transfer gate MOS transistor Q2.
The capacity and C _L, when comparing the distribution before and after the _{charge, Cα + C L (Vcc +} α) = C (Vcc-Vth) Therefore, C = (Vcc + α) C L / (Vcc-α-Vth) ... (1) . For example, if CL = 5 pF, Vcc = 4 V, α = 1 V, and Vth = 1 V, C = 12.5 pF. When a capacitor having this capacity is constituted by a MOS capacitor having a gate oxide film thickness of 150 °, the area needs to be 5500 μm ² . In order to obtain a clock φ2 for driving such a large capacitor, the driving circuit must be large.

The second problem is the size and transfer capability of the transfer gate MOS transistor Q2. To transfer the charge of C _L (Vcc + α) at a high speed, the gate width of the MOS transistor Q2 is required is very large. In addition, when the MOS transistor Q2 is an n-channel transistor, the gate-source voltage V _GS decreases as the output increases, and the threshold voltage increases due to the application of the back gate bias. Even so, the rising waveform of the output potential becomes dull. Further, the gate of the MOS transistor Q2 is connected to Vcc + α
Since the voltage must be boosted to + Vth or more, if the gate width is increased, the capacitor of the booster circuit is correspondingly increased.

(Problems to be Solved by the Invention) As described above, the conventional drive circuit for applying the boosted potential to the word line of the DRAM requires a very large area for the boosting capacitor in order to realize high-speed access. The gate MOS transistor needs to have a large charge transfer capability by increasing the gate width, and there is a problem that even if the gate width is increased, the output rise waveform becomes dull due to the back gate bias.

The present invention provides a semiconductor circuit applicable to a word line drive circuit or the like of a DRAM in which the gate width of a transfer gate MOS transistor is reduced or the area of a boosting capacitor of the gate is reduced and high-speed access is possible. The purpose is to do.

[Constitution of the Invention] (Means for Solving the Problems) The present invention relates to a circuit constituted by MOS transistors formed on a semiconductor substrate, wherein at least one circuit is provided.
a p-type semiconductor region below a channel of the nMOS transistor, which is electrically insulated from a p-type semiconductor region below a channel of all other nMOS-type transistors; and a gate electrode of the nMOS transistor. Is the first
The signal obtained by amplifying the first signal by the buffer circuit is supplied to the p-type semiconductor region below the channel of the transistor, so that the threshold value when the transistor is turned on is supplied. Is lower than the threshold value when the transistor is off.

(Operation) In the semiconductor circuit of the present invention, for example, a word line drive circuit, a positive potential is applied to the p-type well of the n-channel MOS transistor constituting the transfer gate when transferring the charge of the booster circuit. The threshold rise and the current decrease due to the bias effect are suppressed. Therefore, high-speed charge transfer becomes possible. For example, if the gate width of a transfer gate MOS transistor is the same as the conventional one, charge transfer can be performed at a higher speed than the conventional one. The area of the capacitor can be reduced.

When turning off the transfer gate, the potential of the p-type well is
By setting the voltage to 0 V or less, good cut-off characteristics are guaranteed.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 shows a main configuration of a word line driving circuit according to one embodiment. The booster circuit includes an n-channel MOS transistor Q1 having a drain and a gate connected to a power supply potential Vcc, and a boosting capacitor C having one end connected to the source of the MOS transistor Q1 and the other end receiving a boosting clock φ3. It is configured. The output node N of the booster circuit is connected to an output terminal OUT connected to a word line WL via an n-channel MOS transistor Q2 as a transfer gate. The output terminal OUT is provided with a discharging n-channel MOS transistor Q3.

The above basic configuration is the same as the conventional one. This embodiment differs from the prior art in that the p-type well in which the transfer gate MOS transistor Q2 is formed is commonly connected to the gate electrode. Since a clock φ1 which becomes a positive “H” level at the time of charge transfer is applied to the gate electrode of this MOS transistor, this clock φ1 is simultaneously applied to the P-type well. Since a positive potential is applied to the p-type well in this way, the p-type well is separated from other circuit elements and made exclusively for the transfer gate MOS transistor,
Further, it is necessary that a potential equal to or higher than φ1−Vb (Vb is a built-in voltage of a pn junction) is applied to the n-type substrate (or n-type well) on which the p-type well is formed.

3 and 4 show the transfer gate MOS of this embodiment.
9 is a structural example of a transistor Q2. FIG. 3 shows a gate electrode 13 and a dedicated p-type well 12 formed in an n-type substrate 11.
MOS transistor Q having source and drain diffusion layers 14 and 15
Forming two. The p-type well 12 is commonly connected to the gate electrode 13 via the p ⁺ -type layer 16. FIG. 4 shows a p-type substrate
An n-type well 22 is formed in 21, and a dedicated p-type well 23 is formed in the n-type well 22, where a gate electrode 24,
An n-channel MOS transistor Q2 having source and drain diffusion layers 25 and 26 is formed. 3, the p-type well 23 is commonly connected to the gate electrode 24 via the p ⁺ -type layer 27. Vcc is applied to the n-type well 22 via the n + -type layer 28. In the structure of FIG.
First, in the structure of FIG. 4, it is necessary to apply a predetermined positive bias to each of the n-type wells 22 as described above.
In particular, the structure shown in FIG. 4 is advantageous in that since the n-type well 22 is separated from the others, it can easily cope with the case where the clock φ1 has a boosted potential of Vcc or more.

FIG. 2 shows signal waveforms for explaining the operation of the word line drive circuit of this embodiment. The clocks φ1, φ2, φ3 are all initially at “L” level. Therefore, MOS transistors Q2Q3
Is off, and the node N of the capacitor C is charged to Vcc-Vth by the MOS transistor Q1. Next, the clocks φ1 and φ2 change from “L” level to “H” level. As a result, the potential of the node N is boosted to Vcc or higher by the action of the capacitor C, and is supplied to the output terminal OUT via the transfer gate MOS transistor Q2 which is turned on. At this time, the clock φ1 is applied to the p-type well of the MOS transistor Q2 simultaneously with the gate. As a result, a forward bias is applied between the p-type well and the source, and charging is performed directly on the output terminal OUT by the clock φ2 at the same time as charging by the channel current. This is preferable because high-speed charging is possible.

In this way, the potential boosted to Vcc or higher is applied to the word line. By returning the clocks φ1 and φ2 to “L” level and setting the clock φ3 to “H” level, the transfer gate MOS
The transistor Q2 is turned off, the discharging MOS transistor Q3 is turned on, and the word line WL is discharged to "L" level.

According to this embodiment, during charge transfer by the booster circuit, the clock φ is applied to the p-type well of the transfer gate MOS transistor Q2.
As a result of applying the “H” level of 1 at the same time, a so-called back gate bias is not applied, so that a decrease in threshold voltage and a resulting decrease in current are prevented. Therefore transfer gate MOS
If the size of the transistor is the same as the conventional one, the charge transfer is performed at a higher speed than the conventional one, and the size of the MOS transistor can be reduced in order to perform the charge transfer at the same speed as the conventional one. Alternatively, the capacity of the boosting capacitor can be reduced.

Next, some other embodiments of the present invention will be described. In the following embodiments, portions corresponding to FIG. 1 are denoted by the same reference numerals as in FIG. 1, and detailed description is omitted.

FIG. 5 shows an embodiment in which, in order to apply a positive potential to the p-type well of the transfer gate MOS transistor Q2, a driver DV controlled not by the clock φ1 but by the clock φ1 is provided.

The structure of the transfer gate MOS transistor Q2 in this embodiment is as shown in FIG. 6 or FIG. Its basic structure is the same as FIG. 3 or FIG.

In this embodiment, if the power supply used for the driver DV is Vcc, the potential applied to the p-type well is Vcc regardless of the value of the clock φ1. Therefore, even when the clock φ1 is stepped up to Vcc or more, the potential of the n-type substrate (or n-type well) on which the p-type well is formed may be Vcc.

FIG. 8 shows a word line drive circuit of still another embodiment,
In addition to the configuration of FIG. 5, a delay element DR is interposed in the gate of the transfer gate MOS transistor Q2.

In the case of this embodiment, when the clock φ1 rises, first, a charging current flows from the p-type well of the MOS transistor Q2 to the output terminal OUT via the source, and after a certain delay time, the MOS transistor Q2 is turned on to turn on the channel current. The charge transfer is performed in the form of

According to this embodiment, the same effect as that of the previous embodiment can be obtained.

[Effects of the Invention] As described above, according to the present invention, the gate width of the transfer gate MOS transistor can be reduced or the boosting capacitor can be reduced without impairing the high-speed access performance.

[Brief description of the drawings]

FIG. 1 is a diagram showing a main part configuration of a word line driving circuit according to one embodiment of the present invention, FIG. 2 is a diagram showing signal waveforms for explaining the operation thereof, FIG. 3 and FIG. FIG. 5 is a diagram showing an example of a cross-sectional structure of a transfer gate MOS transistor portion in the example. FIG. 5 is a diagram showing a main part configuration of a word line drive circuit of another embodiment. FIGS. 6 and 7 are transfer gate MOS transistor portions thereof. FIG. 8 is a diagram showing a main part configuration of a word line driving circuit according to still another embodiment, FIG. 9 is a diagram showing a main part configuration of a conventional word line driving circuit, FIG. 10 is a signal waveform diagram for explaining the operation. Q1 ... Charge n-channel MOS transistor, C ... Boost capacitor, Q2 ... Transfer gate n-channel MOS transistor, Q3 ... Discharge n-channel MOS transistor
DV: driver, DR: delay element, 11: n-type substrate, 12
... p-type well, 13 ... gate electrode, 14, 15 ... source,
Drain diffusion layer, 16 ...... p ⁺ -type layer, 21 ...... p-type substrate, 22
... n-type well, 23 ... p-type well, 24 ... gate electrode, 25, 26 ... source and drain diffusion layers, 27 ... p ⁺ -type layer, 28 ... n ⁺ -type layer.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/8242 G11C 11/34

Claims (3)

(57) [Claims] 1. A circuit comprising a MOS transistor formed on a semiconductor substrate, comprising: at least one nMOS transistor;
The p-type semiconductor region below the channel of the n-type transistor is electrically insulated from the p-type semiconductor region below the channel of all other nMOS-type elements, and the first signal is delayed to the gate electrode of the nMOS-type transistor. The first signal is amplified by a buffer circuit, and a signal obtained by amplifying the first signal by p
A semiconductor circuit, wherein the threshold value when the nuclear transistor is turned on is made lower than the threshold value when the nuclear transistor is turned off by being supplied to the type semiconductor region. 2. The source potential of said nMOS type transistor is:
2. The semiconductor circuit according to claim 1, wherein the power supply potential is not a fixed power supply potential but a potential that changes according to a second signal different from the signal. 3. The semiconductor circuit according to claim 2, wherein a drain of said nMOS type transistor is connected to a word line connected to memory cells arranged in an array.